usbdrvasm15.inc 17 KB

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  1. /* Name: usbdrvasm15.inc
  2. * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
  3. * Author: contributed by V. Bosch
  4. * Creation Date: 2007-08-06
  5. * Tabsize: 4
  6. * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
  7. * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
  8. */
  9. /* Do not link this file! Link usbdrvasm.S instead, which includes the
  10. * appropriate implementation!
  11. */
  12. /*
  13. General Description:
  14. This file is the 15 MHz version of the asssembler part of the USB driver. It
  15. requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC
  16. oscillator).
  17. See usbdrv.h for a description of the entire driver.
  18. Since almost all of this code is timing critical, don't change unless you
  19. really know what you are doing! Many parts require not only a maximum number
  20. of CPU cycles, but even an exact number of cycles!
  21. */
  22. ;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
  23. ;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte
  24. ; Numbers in brackets are clocks counted from center of last sync bit
  25. ; when instruction starts
  26. ;----------------------------------------------------------------------------
  27. ; order of registers pushed:
  28. ; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4
  29. ;----------------------------------------------------------------------------
  30. USB_INTR_VECTOR:
  31. push YL ;2 push only what is necessary to sync with edge ASAP
  32. in YL, SREG ;1
  33. push YL ;2
  34. ;----------------------------------------------------------------------------
  35. ; Synchronize with sync pattern:
  36. ;
  37. ; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
  38. ; sync up with J to K edge during sync pattern -- use fastest possible loops
  39. ;The first part waits at most 1 bit long since we must be in sync pattern.
  40. ;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
  41. ;waitForJ, ensure that this prerequisite is met.
  42. waitForJ:
  43. inc YL
  44. sbis USBIN, USBMINUS
  45. brne waitForJ ; just make sure we have ANY timeout
  46. ;-------------------------------------------------------------------------------
  47. ; The following code results in a sampling window of < 1/4 bit
  48. ; which meets the spec.
  49. ;-------------------------------------------------------------------------------
  50. waitForK: ;-
  51. sbis USBIN, USBMINUS ;1 [00] <-- sample
  52. rjmp foundK ;2 [01]
  53. sbis USBIN, USBMINUS ; <-- sample
  54. rjmp foundK
  55. sbis USBIN, USBMINUS ; <-- sample
  56. rjmp foundK
  57. sbis USBIN, USBMINUS ; <-- sample
  58. rjmp foundK
  59. sbis USBIN, USBMINUS ; <-- sample
  60. rjmp foundK
  61. sbis USBIN, USBMINUS ; <-- sample
  62. rjmp foundK
  63. #if USB_COUNT_SOF
  64. lds YL, usbSofCount
  65. inc YL
  66. sts usbSofCount, YL
  67. #endif /* USB_COUNT_SOF */
  68. #ifdef USB_SOF_HOOK
  69. USB_SOF_HOOK
  70. #endif
  71. rjmp sofError
  72. ;------------------------------------------------------------------------------
  73. ; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for
  74. ; center sampling]
  75. ; we have 1 bit time for setup purposes, then sample again.
  76. ; Numbers in brackets are cycles from center of first sync (double K)
  77. ; bit after the instruction
  78. ;------------------------------------------------------------------------------
  79. foundK: ;- [02]
  80. lds YL, usbInputBufOffset;2 [03+04] tx loop
  81. push YH ;2 [05+06]
  82. clr YH ;1 [07]
  83. subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init]
  84. sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init]
  85. push shift ;2 [10+11]
  86. ser shift ;1 [12]
  87. sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early)
  88. rjmp haveTwoBitsK ;2 [00] [14]
  89. pop shift ;2 [15+16] undo the push from before
  90. pop YH ;2 [17+18] undo the push from before
  91. rjmp waitForK ;2 [19+20] this was not the end of sync, retry
  92. ; The entire loop from waitForK until rjmp waitForK above must not exceed two
  93. ; bit times (= 20 cycles).
  94. ;----------------------------------------------------------------------------
  95. ; push more registers and initialize values while we sample the first bits:
  96. ;----------------------------------------------------------------------------
  97. haveTwoBitsK: ;- [01]
  98. push x1 ;2 [02+03]
  99. push x2 ;2 [04+05]
  100. push x3 ;2 [06+07]
  101. push bitcnt ;2 [08+09]
  102. in x1, USBIN ;1 [00] [10] <-- sample bit 0
  103. bst x1, USBMINUS ;1 [01]
  104. bld shift, 0 ;1 [02]
  105. push cnt ;2 [03+04]
  106. ldi cnt, USB_BUFSIZE ;1 [05]
  107. push x4 ;2 [06+07] tx loop
  108. rjmp rxLoop ;2 [08]
  109. ;----------------------------------------------------------------------------
  110. ; Receiver loop (numbers in brackets are cycles within byte after instr)
  111. ;----------------------------------------------------------------------------
  112. unstuff0: ;- [07] (branch taken)
  113. andi x3, ~0x01 ;1 [08]
  114. mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit
  115. in x2, USBIN ;1 [00] [10] <-- sample bit 1 again
  116. andi x2, USBMASK ;1 [01]
  117. breq se0Hop ;1 [02] SE0 check for bit 1
  118. ori shift, 0x01 ;1 [03] 0b00000001
  119. nop ;1 [04]
  120. rjmp didUnstuff0 ;2 [05]
  121. ;-----------------------------------------------------
  122. unstuff1: ;- [05] (branch taken)
  123. mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit
  124. andi x3, ~0x02 ;1 [07]
  125. ori shift, 0x02 ;1 [08] 0b00000010
  126. nop ;1 [09]
  127. in x1, USBIN ;1 [00] [10] <-- sample bit 2 again
  128. andi x1, USBMASK ;1 [01]
  129. breq se0Hop ;1 [02] SE0 check for bit 2
  130. rjmp didUnstuff1 ;2 [03]
  131. ;-----------------------------------------------------
  132. unstuff2: ;- [05] (branch taken)
  133. andi x3, ~0x04 ;1 [06]
  134. ori shift, 0x04 ;1 [07] 0b00000100
  135. mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit
  136. nop ;1 [09]
  137. in x2, USBIN ;1 [00] [10] <-- sample bit 3
  138. andi x2, USBMASK ;1 [01]
  139. breq se0Hop ;1 [02] SE0 check for bit 3
  140. rjmp didUnstuff2 ;2 [03]
  141. ;-----------------------------------------------------
  142. unstuff3: ;- [00] [10] (branch taken)
  143. in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late
  144. andi x2, USBMASK ;1 [02]
  145. breq se0Hop ;1 [03] SE0 check for stuffed bit 3
  146. andi x3, ~0x08 ;1 [04]
  147. ori shift, 0x08 ;1 [05] 0b00001000
  148. rjmp didUnstuff3 ;2 [06]
  149. ;----------------------------------------------------------------------------
  150. ; extra jobs done during bit interval:
  151. ;
  152. ; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs],
  153. ; overflow check, jump to the head of rxLoop
  154. ; bit 1: SE0 check
  155. ; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long]
  156. ; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long]
  157. ; bit 4: SE0 check, none
  158. ; bit 5: SE0 check, none
  159. ; bit 6: SE0 check, none
  160. ; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others
  161. ;----------------------------------------------------------------------------
  162. rxLoop: ;- [09]
  163. in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed)
  164. andi x2, USBMASK ;1 [01]
  165. brne SkipSe0Hop ;1 [02]
  166. se0Hop: ;- [02]
  167. rjmp se0 ;2 [03] SE0 check for bit 1
  168. SkipSe0Hop: ;- [03]
  169. ser x3 ;1 [04]
  170. andi shift, 0xf9 ;1 [05] 0b11111001
  171. breq unstuff0 ;1 [06]
  172. didUnstuff0: ;- [06]
  173. eor x1, x2 ;1 [07]
  174. bst x1, USBMINUS ;1 [08]
  175. bld shift, 1 ;1 [09]
  176. in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed)
  177. andi x1, USBMASK ;1 [01]
  178. breq se0Hop ;1 [02] SE0 check for bit 2
  179. andi shift, 0xf3 ;1 [03] 0b11110011
  180. breq unstuff1 ;1 [04] do remaining work for bit 1
  181. didUnstuff1: ;- [04]
  182. eor x2, x1 ;1 [05]
  183. bst x2, USBMINUS ;1 [06]
  184. bld shift, 2 ;1 [07]
  185. nop2 ;2 [08+09]
  186. in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed)
  187. andi x2, USBMASK ;1 [01]
  188. breq se0Hop ;1 [02] SE0 check for bit 3
  189. andi shift, 0xe7 ;1 [03] 0b11100111
  190. breq unstuff2 ;1 [04]
  191. didUnstuff2: ;- [04]
  192. eor x1, x2 ;1 [05]
  193. bst x1, USBMINUS ;1 [06]
  194. bld shift, 3 ;1 [07]
  195. didUnstuff3: ;- [07]
  196. andi shift, 0xcf ;1 [08] 0b11001111
  197. breq unstuff3 ;1 [09]
  198. in x1, USBIN ;1 [00] [10] <-- sample bit 4
  199. andi x1, USBMASK ;1 [01]
  200. breq se0Hop ;1 [02] SE0 check for bit 4
  201. eor x2, x1 ;1 [03]
  202. bst x2, USBMINUS ;1 [04]
  203. bld shift, 4 ;1 [05]
  204. didUnstuff4: ;- [05]
  205. andi shift, 0x9f ;1 [06] 0b10011111
  206. breq unstuff4 ;1 [07]
  207. nop2 ;2 [08+09]
  208. in x2, USBIN ;1 [00] [10] <-- sample bit 5
  209. andi x2, USBMASK ;1 [01]
  210. breq se0 ;1 [02] SE0 check for bit 5
  211. eor x1, x2 ;1 [03]
  212. bst x1, USBMINUS ;1 [04]
  213. bld shift, 5 ;1 [05]
  214. didUnstuff5: ;- [05]
  215. andi shift, 0x3f ;1 [06] 0b00111111
  216. breq unstuff5 ;1 [07]
  217. nop2 ;2 [08+09]
  218. in x1, USBIN ;1 [00] [10] <-- sample bit 6
  219. andi x1, USBMASK ;1 [01]
  220. breq se0 ;1 [02] SE0 check for bit 6
  221. eor x2, x1 ;1 [03]
  222. bst x2, USBMINUS ;1 [04]
  223. bld shift, 6 ;1 [05]
  224. didUnstuff6: ;- [05]
  225. cpi shift, 0x02 ;1 [06] 0b00000010
  226. brlo unstuff6 ;1 [07]
  227. nop2 ;2 [08+09]
  228. in x2, USBIN ;1 [00] [10] <-- sample bit 7
  229. andi x2, USBMASK ;1 [01]
  230. breq se0 ;1 [02] SE0 check for bit 7
  231. eor x1, x2 ;1 [03]
  232. bst x1, USBMINUS ;1 [04]
  233. bld shift, 7 ;1 [05]
  234. didUnstuff7: ;- [05]
  235. cpi shift, 0x04 ;1 [06] 0b00000100
  236. brlo unstuff7 ;1 [07]
  237. eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others
  238. nop ;1 [09]
  239. in x1, USBIN ;1 [00] [10] <-- sample bit 0
  240. st y+, x3 ;2 [01+02] store data
  241. eor x2, x1 ;1 [03]
  242. bst x2, USBMINUS ;1 [04]
  243. bld shift, 0 ;1 [05]
  244. subi cnt, 1 ;1 [06]
  245. brcs overflow ;1 [07]
  246. rjmp rxLoop ;2 [08]
  247. ;-----------------------------------------------------
  248. unstuff4: ;- [08]
  249. andi x3, ~0x10 ;1 [09]
  250. in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4
  251. andi x1, USBMASK ;1 [01]
  252. breq se0 ;1 [02] SE0 check for stuffed bit 4
  253. ori shift, 0x10 ;1 [03]
  254. rjmp didUnstuff4 ;2 [04]
  255. ;-----------------------------------------------------
  256. unstuff5: ;- [08]
  257. ori shift, 0x20 ;1 [09]
  258. in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5
  259. andi x2, USBMASK ;1 [01]
  260. breq se0 ;1 [02] SE0 check for stuffed bit 5
  261. andi x3, ~0x20 ;1 [03]
  262. rjmp didUnstuff5 ;2 [04]
  263. ;-----------------------------------------------------
  264. unstuff6: ;- [08]
  265. andi x3, ~0x40 ;1 [09]
  266. in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6
  267. andi x1, USBMASK ;1 [01]
  268. breq se0 ;1 [02] SE0 check for stuffed bit 6
  269. ori shift, 0x40 ;1 [03]
  270. rjmp didUnstuff6 ;2 [04]
  271. ;-----------------------------------------------------
  272. unstuff7: ;- [08]
  273. andi x3, ~0x80 ;1 [09]
  274. in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7
  275. andi x2, USBMASK ;1 [01]
  276. breq se0 ;1 [02] SE0 check for stuffed bit 7
  277. ori shift, 0x80 ;1 [03]
  278. rjmp didUnstuff7 ;2 [04]
  279. macro POP_STANDARD ; 16 cycles
  280. pop x4
  281. pop cnt
  282. pop bitcnt
  283. pop x3
  284. pop x2
  285. pop x1
  286. pop shift
  287. pop YH
  288. endm
  289. macro POP_RETI ; 5 cycles
  290. pop YL
  291. out SREG, YL
  292. pop YL
  293. endm
  294. #include "asmcommon.inc"
  295. ;---------------------------------------------------------------------------
  296. ; USB spec says:
  297. ; idle = J
  298. ; J = (D+ = 0), (D- = 1)
  299. ; K = (D+ = 1), (D- = 0)
  300. ; Spec allows 7.5 bit times from EOP to SOP for replies
  301. ;---------------------------------------------------------------------------
  302. bitstuffN: ;- [04]
  303. eor x1, x4 ;1 [05]
  304. clr x2 ;1 [06]
  305. nop ;1 [07]
  306. rjmp didStuffN ;1 [08]
  307. ;---------------------------------------------------------------------------
  308. bitstuff6: ;- [04]
  309. eor x1, x4 ;1 [05]
  310. clr x2 ;1 [06]
  311. rjmp didStuff6 ;1 [07]
  312. ;---------------------------------------------------------------------------
  313. bitstuff7: ;- [02]
  314. eor x1, x4 ;1 [03]
  315. clr x2 ;1 [06]
  316. nop ;1 [05]
  317. rjmp didStuff7 ;1 [06]
  318. ;---------------------------------------------------------------------------
  319. sendNakAndReti: ;- [-19]
  320. ldi x3, USBPID_NAK ;1 [-18]
  321. rjmp sendX3AndReti ;1 [-17]
  322. ;---------------------------------------------------------------------------
  323. sendAckAndReti: ;- [-17]
  324. ldi cnt, USBPID_ACK ;1 [-16]
  325. sendCntAndReti: ;- [-16]
  326. mov x3, cnt ;1 [-15]
  327. sendX3AndReti: ;- [-15]
  328. ldi YL, 20 ;1 [-14] x3==r20 address is 20
  329. ldi YH, 0 ;1 [-13]
  330. ldi cnt, 2 ;1 [-12]
  331. ; rjmp usbSendAndReti fallthrough
  332. ;---------------------------------------------------------------------------
  333. ;usbSend:
  334. ;pointer to data in 'Y'
  335. ;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
  336. ;uses: x1...x4, btcnt, shift, cnt, Y
  337. ;Numbers in brackets are time since first bit of sync pattern is sent
  338. ;We need not to match the transfer rate exactly because the spec demands
  339. ;only 1.5% precision anyway.
  340. usbSendAndReti: ;- [-13] 13 cycles until SOP
  341. in x2, USBDDR ;1 [-12]
  342. ori x2, USBMASK ;1 [-11]
  343. sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups)
  344. in x1, USBOUT ;1 [-08] port mirror for tx loop
  345. out USBDDR, x2 ;1 [-07] <- acquire bus
  346. ; need not init x2 (bitstuff history) because sync starts with 0
  347. ldi x4, USBMASK ;1 [-06] exor mask
  348. ldi shift, 0x80 ;1 [-05] sync byte is first byte sent
  349. ldi bitcnt, 6 ;1 [-04]
  350. txBitLoop: ;- [-04] [06]
  351. sbrs shift, 0 ;1 [-03] [07]
  352. eor x1, x4 ;1 [-02] [08]
  353. ror shift ;1 [-01] [09]
  354. didStuffN: ;- [09]
  355. out USBOUT, x1 ;1 [00] [10] <-- out N
  356. ror x2 ;1 [01]
  357. cpi x2, 0xfc ;1 [02]
  358. brcc bitstuffN ;1 [03]
  359. dec bitcnt ;1 [04]
  360. brne txBitLoop ;1 [05]
  361. sbrs shift, 0 ;1 [06]
  362. eor x1, x4 ;1 [07]
  363. ror shift ;1 [08]
  364. didStuff6: ;- [08]
  365. nop ;1 [09]
  366. out USBOUT, x1 ;1 [00] [10] <-- out 6
  367. ror x2 ;1 [01]
  368. cpi x2, 0xfc ;1 [02]
  369. brcc bitstuff6 ;1 [03]
  370. sbrs shift, 0 ;1 [04]
  371. eor x1, x4 ;1 [05]
  372. ror shift ;1 [06]
  373. ror x2 ;1 [07]
  374. didStuff7: ;- [07]
  375. ldi bitcnt, 6 ;1 [08]
  376. cpi x2, 0xfc ;1 [09]
  377. out USBOUT, x1 ;1 [00] [10] <-- out 7
  378. brcc bitstuff7 ;1 [01]
  379. ld shift, y+ ;2 [02+03]
  380. dec cnt ;1 [04]
  381. brne txBitLoop ;1 [05]
  382. makeSE0:
  383. cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles]
  384. lds x2, usbNewDeviceAddr;2 [07+08]
  385. lsl x2 ;1 [09] we compare with left shifted address
  386. ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
  387. ;set address only after data packet was sent, not after handshake
  388. out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle
  389. subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3
  390. sbci YH, 0 ;1 [02]
  391. breq skipAddrAssign ;1 [03]
  392. sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer
  393. ;----------------------------------------------------------------------------
  394. ;end of usbDeviceAddress transfer
  395. skipAddrAssign: ;- [03/04]
  396. ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [05] int0 occurred during TX -- clear pending flag
  397. USB_STORE_PENDING(x2) ;1 [06]
  398. ori x1, USBIDLE ;1 [07]
  399. in x2, USBDDR ;1 [08]
  400. cbr x2, USBMASK ;1 [09] set both pins to input
  401. mov x3, x1 ;1 [10]
  402. cbr x3, USBMASK ;1 [11] configure no pullup on both pins
  403. ldi x4, 3 ;1 [12]
  404. se0Delay: ;- [12] [15]
  405. dec x4 ;1 [13] [16]
  406. brne se0Delay ;1 [14] [17]
  407. nop2 ;2 [18+19]
  408. out USBOUT, x1 ;1 [20] <--out J (idle) -- end of SE0 (EOP sig.)
  409. out USBDDR, x2 ;1 [21] <--release bus now
  410. out USBOUT, x3 ;1 [22] <--ensure no pull-up resistors are active
  411. rjmp doReturn ;1 [23]
  412. ;---------------------------------------------------------------------------