usbdrvasm12.inc 15 KB

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  1. /* Name: usbdrvasm12.inc
  2. * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
  3. * Author: Christian Starkjohann
  4. * Creation Date: 2004-12-29
  5. * Tabsize: 4
  6. * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
  7. * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
  8. */
  9. /* Do not link this file! Link usbdrvasm.S instead, which includes the
  10. * appropriate implementation!
  11. */
  12. /*
  13. General Description:
  14. This file is the 12 MHz version of the asssembler part of the USB driver. It
  15. requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC
  16. oscillator).
  17. See usbdrv.h for a description of the entire driver.
  18. Since almost all of this code is timing critical, don't change unless you
  19. really know what you are doing! Many parts require not only a maximum number
  20. of CPU cycles, but even an exact number of cycles!
  21. Timing constraints according to spec (in bit times):
  22. timing subject min max CPUcycles
  23. ---------------------------------------------------------------------------
  24. EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128
  25. EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60
  26. DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60
  27. */
  28. ;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
  29. ;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
  30. ;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable
  31. ;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes
  32. ;Numbers in brackets are maximum cycles since SOF.
  33. USB_INTR_VECTOR:
  34. ;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt
  35. push YL ;2 [35] push only what is necessary to sync with edge ASAP
  36. in YL, SREG ;1 [37]
  37. push YL ;2 [39]
  38. ;----------------------------------------------------------------------------
  39. ; Synchronize with sync pattern:
  40. ;----------------------------------------------------------------------------
  41. ;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
  42. ;sync up with J to K edge during sync pattern -- use fastest possible loops
  43. ;The first part waits at most 1 bit long since we must be in sync pattern.
  44. ;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
  45. ;waitForJ, ensure that this prerequisite is met.
  46. waitForJ:
  47. inc YL
  48. sbis USBIN, USBMINUS
  49. brne waitForJ ; just make sure we have ANY timeout
  50. waitForK:
  51. ;The following code results in a sampling window of 1/4 bit which meets the spec.
  52. sbis USBIN, USBMINUS
  53. rjmp foundK
  54. sbis USBIN, USBMINUS
  55. rjmp foundK
  56. sbis USBIN, USBMINUS
  57. rjmp foundK
  58. sbis USBIN, USBMINUS
  59. rjmp foundK
  60. sbis USBIN, USBMINUS
  61. rjmp foundK
  62. #if USB_COUNT_SOF
  63. lds YL, usbSofCount
  64. inc YL
  65. sts usbSofCount, YL
  66. #endif /* USB_COUNT_SOF */
  67. #ifdef USB_SOF_HOOK
  68. USB_SOF_HOOK
  69. #endif
  70. rjmp sofError
  71. foundK:
  72. ;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling]
  73. ;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
  74. ;are cycles from center of first sync (double K) bit after the instruction
  75. push YH ;2 [2]
  76. lds YL, usbInputBufOffset;2 [4]
  77. clr YH ;1 [5]
  78. subi YL, lo8(-(usbRxBuf));1 [6]
  79. sbci YH, hi8(-(usbRxBuf));1 [7]
  80. sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early]
  81. rjmp haveTwoBitsK ;2 [10]
  82. pop YH ;2 [11] undo the push from before
  83. rjmp waitForK ;2 [13] this was not the end of sync, retry
  84. haveTwoBitsK:
  85. ;----------------------------------------------------------------------------
  86. ; push more registers and initialize values while we sample the first bits:
  87. ;----------------------------------------------------------------------------
  88. push shift ;2 [16]
  89. push x1 ;2 [12]
  90. push x2 ;2 [14]
  91. in x1, USBIN ;1 [17] <-- sample bit 0
  92. ldi shift, 0xff ;1 [18]
  93. bst x1, USBMINUS ;1 [19]
  94. bld shift, 0 ;1 [20]
  95. push x3 ;2 [22]
  96. push cnt ;2 [24]
  97. in x2, USBIN ;1 [25] <-- sample bit 1
  98. ser x3 ;1 [26] [inserted init instruction]
  99. eor x1, x2 ;1 [27]
  100. bst x1, USBMINUS ;1 [28]
  101. bld shift, 1 ;1 [29]
  102. ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction]
  103. rjmp rxbit2 ;2 [32]
  104. ;----------------------------------------------------------------------------
  105. ; Receiver loop (numbers in brackets are cycles within byte after instr)
  106. ;----------------------------------------------------------------------------
  107. unstuff0: ;1 (branch taken)
  108. andi x3, ~0x01 ;1 [15]
  109. mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit
  110. in x2, USBIN ;1 [17] <-- sample bit 1 again
  111. ori shift, 0x01 ;1 [18]
  112. rjmp didUnstuff0 ;2 [20]
  113. unstuff1: ;1 (branch taken)
  114. mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit
  115. andi x3, ~0x02 ;1 [22]
  116. ori shift, 0x02 ;1 [23]
  117. nop ;1 [24]
  118. in x1, USBIN ;1 [25] <-- sample bit 2 again
  119. rjmp didUnstuff1 ;2 [27]
  120. unstuff2: ;1 (branch taken)
  121. andi x3, ~0x04 ;1 [29]
  122. ori shift, 0x04 ;1 [30]
  123. mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit
  124. nop ;1 [32]
  125. in x2, USBIN ;1 [33] <-- sample bit 3
  126. rjmp didUnstuff2 ;2 [35]
  127. unstuff3: ;1 (branch taken)
  128. in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late]
  129. andi x3, ~0x08 ;1 [35]
  130. ori shift, 0x08 ;1 [36]
  131. rjmp didUnstuff3 ;2 [38]
  132. unstuff4: ;1 (branch taken)
  133. andi x3, ~0x10 ;1 [40]
  134. in x1, USBIN ;1 [41] <-- sample stuffed bit 4
  135. ori shift, 0x10 ;1 [42]
  136. rjmp didUnstuff4 ;2 [44]
  137. unstuff5: ;1 (branch taken)
  138. andi x3, ~0x20 ;1 [48]
  139. in x2, USBIN ;1 [49] <-- sample stuffed bit 5
  140. ori shift, 0x20 ;1 [50]
  141. rjmp didUnstuff5 ;2 [52]
  142. unstuff6: ;1 (branch taken)
  143. andi x3, ~0x40 ;1 [56]
  144. in x1, USBIN ;1 [57] <-- sample stuffed bit 6
  145. ori shift, 0x40 ;1 [58]
  146. rjmp didUnstuff6 ;2 [60]
  147. ; extra jobs done during bit interval:
  148. ; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs]
  149. ; bit 1: se0 check
  150. ; bit 2: overflow check
  151. ; bit 3: recovery from delay [bit 0 tasks took too long]
  152. ; bit 4: none
  153. ; bit 5: none
  154. ; bit 6: none
  155. ; bit 7: jump, eor
  156. rxLoop:
  157. eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others
  158. in x1, USBIN ;1 [1] <-- sample bit 0
  159. st y+, x3 ;2 [3] store data
  160. ser x3 ;1 [4]
  161. nop ;1 [5]
  162. eor x2, x1 ;1 [6]
  163. bst x2, USBMINUS;1 [7]
  164. bld shift, 0 ;1 [8]
  165. in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed)
  166. andi x2, USBMASK ;1 [10]
  167. breq se0 ;1 [11] SE0 check for bit 1
  168. andi shift, 0xf9 ;1 [12]
  169. didUnstuff0:
  170. breq unstuff0 ;1 [13]
  171. eor x1, x2 ;1 [14]
  172. bst x1, USBMINUS;1 [15]
  173. bld shift, 1 ;1 [16]
  174. rxbit2:
  175. in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed)
  176. andi shift, 0xf3 ;1 [18]
  177. breq unstuff1 ;1 [19] do remaining work for bit 1
  178. didUnstuff1:
  179. subi cnt, 1 ;1 [20]
  180. brcs overflow ;1 [21] loop control
  181. eor x2, x1 ;1 [22]
  182. bst x2, USBMINUS;1 [23]
  183. bld shift, 2 ;1 [24]
  184. in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed)
  185. andi shift, 0xe7 ;1 [26]
  186. breq unstuff2 ;1 [27]
  187. didUnstuff2:
  188. eor x1, x2 ;1 [28]
  189. bst x1, USBMINUS;1 [29]
  190. bld shift, 3 ;1 [30]
  191. didUnstuff3:
  192. andi shift, 0xcf ;1 [31]
  193. breq unstuff3 ;1 [32]
  194. in x1, USBIN ;1 [33] <-- sample bit 4
  195. eor x2, x1 ;1 [34]
  196. bst x2, USBMINUS;1 [35]
  197. bld shift, 4 ;1 [36]
  198. didUnstuff4:
  199. andi shift, 0x9f ;1 [37]
  200. breq unstuff4 ;1 [38]
  201. nop2 ;2 [40]
  202. in x2, USBIN ;1 [41] <-- sample bit 5
  203. eor x1, x2 ;1 [42]
  204. bst x1, USBMINUS;1 [43]
  205. bld shift, 5 ;1 [44]
  206. didUnstuff5:
  207. andi shift, 0x3f ;1 [45]
  208. breq unstuff5 ;1 [46]
  209. nop2 ;2 [48]
  210. in x1, USBIN ;1 [49] <-- sample bit 6
  211. eor x2, x1 ;1 [50]
  212. bst x2, USBMINUS;1 [51]
  213. bld shift, 6 ;1 [52]
  214. didUnstuff6:
  215. cpi shift, 0x02 ;1 [53]
  216. brlo unstuff6 ;1 [54]
  217. nop2 ;2 [56]
  218. in x2, USBIN ;1 [57] <-- sample bit 7
  219. eor x1, x2 ;1 [58]
  220. bst x1, USBMINUS;1 [59]
  221. bld shift, 7 ;1 [60]
  222. didUnstuff7:
  223. cpi shift, 0x04 ;1 [61]
  224. brsh rxLoop ;2 [63] loop control
  225. unstuff7:
  226. andi x3, ~0x80 ;1 [63]
  227. ori shift, 0x80 ;1 [64]
  228. in x2, USBIN ;1 [65] <-- sample stuffed bit 7
  229. nop ;1 [66]
  230. rjmp didUnstuff7 ;2 [68]
  231. macro POP_STANDARD ; 12 cycles
  232. pop cnt
  233. pop x3
  234. pop x2
  235. pop x1
  236. pop shift
  237. pop YH
  238. endm
  239. macro POP_RETI ; 5 cycles
  240. pop YL
  241. out SREG, YL
  242. pop YL
  243. endm
  244. #include "asmcommon.inc"
  245. ;----------------------------------------------------------------------------
  246. ; Transmitting data
  247. ;----------------------------------------------------------------------------
  248. txByteLoop:
  249. txBitloop:
  250. stuffN1Delay: ; [03]
  251. ror shift ;[-5] [11] [59]
  252. brcc doExorN1 ;[-4] [60]
  253. subi x4, 1 ;[-3]
  254. brne commonN1 ;[-2]
  255. lsl shift ;[-1] compensate ror after rjmp stuffDelay
  256. nop ;[00] stuffing consists of just waiting 8 cycles
  257. rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear
  258. sendNakAndReti: ;0 [-19] 19 cycles until SOP
  259. ldi x3, USBPID_NAK ;1 [-18]
  260. rjmp usbSendX3 ;2 [-16]
  261. sendAckAndReti: ;0 [-19] 19 cycles until SOP
  262. ldi x3, USBPID_ACK ;1 [-18]
  263. rjmp usbSendX3 ;2 [-16]
  264. sendCntAndReti: ;0 [-17] 17 cycles until SOP
  265. mov x3, cnt ;1 [-16]
  266. usbSendX3: ;0 [-16]
  267. ldi YL, 20 ;1 [-15] 'x3' is R20
  268. ldi YH, 0 ;1 [-14]
  269. ldi cnt, 2 ;1 [-13]
  270. ; rjmp usbSendAndReti fallthrough
  271. ; USB spec says:
  272. ; idle = J
  273. ; J = (D+ = 0), (D- = 1) or USBOUT = 0x01
  274. ; K = (D+ = 1), (D- = 0) or USBOUT = 0x02
  275. ; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles)
  276. ;usbSend:
  277. ;pointer to data in 'Y'
  278. ;number of bytes in 'cnt' -- including sync byte
  279. ;uses: x1...x2, x4, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x4 = bitstuff cnt]
  280. ;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction)
  281. usbSendAndReti:
  282. in x2, USBDDR ;[-12] 12 cycles until SOP
  283. ori x2, USBMASK ;[-11]
  284. sbi USBOUT, USBMINUS ;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
  285. out USBDDR, x2 ;[-8] <--- acquire bus
  286. in x1, USBOUT ;[-7] port mirror for tx loop
  287. ldi shift, 0x40 ;[-6] sync byte is first byte sent (we enter loop after ror)
  288. ldi x2, USBMASK ;[-5]
  289. push x4 ;[-4]
  290. doExorN1:
  291. eor x1, x2 ;[-2] [06] [62]
  292. ldi x4, 6 ;[-1] [07] [63]
  293. commonN1:
  294. stuffN2Delay:
  295. out USBOUT, x1 ;[00] [08] [64] <--- set bit
  296. ror shift ;[01]
  297. brcc doExorN2 ;[02]
  298. subi x4, 1 ;[03]
  299. brne commonN2 ;[04]
  300. lsl shift ;[05] compensate ror after rjmp stuffDelay
  301. rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear
  302. doExorN2:
  303. eor x1, x2 ;[04] [12]
  304. ldi x4, 6 ;[05] [13]
  305. commonN2:
  306. nop ;[06] [14]
  307. subi cnt, 171 ;[07] [15] trick: (3 * 171) & 0xff = 1
  308. out USBOUT, x1 ;[08] [16] <--- set bit
  309. brcs txBitloop ;[09] [25] [41]
  310. stuff6Delay:
  311. ror shift ;[42] [50]
  312. brcc doExor6 ;[43]
  313. subi x4, 1 ;[44]
  314. brne common6 ;[45]
  315. lsl shift ;[46] compensate ror after rjmp stuffDelay
  316. nop ;[47] stuffing consists of just waiting 8 cycles
  317. rjmp stuff6Delay ;[48] after ror, C bit is reliably clear
  318. doExor6:
  319. eor x1, x2 ;[45] [53]
  320. ldi x4, 6 ;[46]
  321. common6:
  322. stuff7Delay:
  323. ror shift ;[47] [55]
  324. out USBOUT, x1 ;[48] <--- set bit
  325. brcc doExor7 ;[49]
  326. subi x4, 1 ;[50]
  327. brne common7 ;[51]
  328. lsl shift ;[52] compensate ror after rjmp stuffDelay
  329. rjmp stuff7Delay ;[53] after ror, C bit is reliably clear
  330. doExor7:
  331. eor x1, x2 ;[51] [59]
  332. ldi x4, 6 ;[52]
  333. common7:
  334. ld shift, y+ ;[53]
  335. tst cnt ;[55]
  336. out USBOUT, x1 ;[56] <--- set bit
  337. brne txByteLoop ;[57]
  338. ;make SE0:
  339. cbr x1, USBMASK ;[58] prepare SE0 [spec says EOP may be 15 to 18 cycles]
  340. lds x2, usbNewDeviceAddr;[59]
  341. lsl x2 ;[61] we compare with left shifted address
  342. subi YL, 2 + 20 ;[62] Only assign address on data packets, not ACK/NAK in x3
  343. sbci YH, 0 ;[63]
  344. out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle
  345. ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
  346. ;set address only after data packet was sent, not after handshake
  347. breq skipAddrAssign ;[01]
  348. sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer
  349. skipAddrAssign:
  350. ;end of usbDeviceAddress transfer
  351. ldi x2, 1<<USB_INTR_PENDING_BIT;[03] int0 occurred during TX -- clear pending flag
  352. USB_STORE_PENDING(x2) ;[04]
  353. ori x1, USBIDLE ;[05]
  354. in x2, USBDDR ;[06]
  355. cbr x2, USBMASK ;[07] set both pins to input
  356. mov x3, x1 ;[08]
  357. cbr x3, USBMASK ;[09] configure no pullup on both pins
  358. pop x4 ;[10]
  359. nop2 ;[12]
  360. nop2 ;[14]
  361. out USBOUT, x1 ;[16] <-- out J (idle) -- end of SE0 (EOP signal)
  362. out USBDDR, x2 ;[17] <-- release bus now
  363. out USBOUT, x3 ;[18] <-- ensure no pull-up resistors are active
  364. rjmp doReturn