main.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432
  1. #include <avr/io.h>
  2. #include <avr/interrupt.h> /* for sei() */
  3. #include <util/delay.h> /* for _delay_ms() */
  4. #include <stdlib.h>
  5. #include <avr/pgmspace.h> /* required by usbdrv.h */
  6. #include "usbdrv.h"
  7. #include "oddebug.h" /* This is also an example for using debug
  8. * macros */
  9. #include "config.h"
  10. #include "requests.h" /* The custom request numbers we use */
  11. #include "uart.h"
  12. #include "sram.h"
  13. #include "debug.h"
  14. #include "dump.h"
  15. #include "crc.h"
  16. #include "usb_bulk.h"
  17. #include "timer.h"
  18. #include "watchdog.h"
  19. extern FILE uart_stdout;
  20. uint8_t debug_level = ( DEBUG | DEBUG_USB | DEBUG_CRC );
  21. uint8_t read_buffer[TRANSFER_BUFFER_SIZE];
  22. uint32_t req_addr = 0;
  23. uint32_t req_addr_end = 0;
  24. uint32_t req_size;
  25. uint8_t req_bank;
  26. uint32_t req_bank_size;
  27. uint16_t req_bank_cnt;
  28. uint8_t req_state = REQ_STATUS_IDLE;
  29. uint8_t rx_remaining = 0;
  30. uint8_t tx_remaining = 0;
  31. uint16_t sync_errors = 0;
  32. uint8_t tx_buffer[32];
  33. uint8_t data_buffer[4];
  34. uint32_t addr;
  35. uint16_t crc = 0;
  36. usbMsgLen_t usbFunctionSetup(uchar data[8])
  37. {
  38. usbRequest_t *rq = (void *) data;
  39. uint8_t ret_len = 0;
  40. /*
  41. * -------------------------------------------------------------------------
  42. */
  43. if (rq->bRequest == USB_UPLOAD_INIT) {
  44. if (req_state != REQ_STATUS_IDLE){
  45. debug(DEBUG_USB,"USB_UPLOAD_INIT: ERROR state is not REQ_STATUS_IDLE\n");
  46. return 0;
  47. }
  48. req_bank = 0;
  49. rx_remaining = 0;
  50. req_bank_size = (uint32_t)1 << rq->wValue.word;
  51. sync_errors = 0;
  52. crc = 0;
  53. debug(DEBUG_USB,"USB_UPLOAD_INIT: bank_size=0x%08lx\n", req_bank_size);
  54. /*
  55. * -------------------------------------------------------------------------
  56. */
  57. } else if (rq->bRequest == USB_UPLOAD_ADDR) {
  58. req_state = REQ_STATUS_UPLOAD;
  59. req_addr = rq->wValue.word;
  60. req_addr = req_addr << 16;
  61. req_addr = req_addr | rq->wIndex.word;
  62. if (rx_remaining) {
  63. sync_errors++;
  64. debug
  65. (DEBUG_USB,"USB_UPLOAD_ADDR: Out of sync addr=0x%lx remain=%i packet=%i sync_error=%i\n",
  66. req_addr, rx_remaining, rq->wLength.word, sync_errors);
  67. ret_len = 0;
  68. }
  69. rx_remaining = rq->wLength.word;
  70. ret_len = USB_MAX_TRANS;
  71. if (req_addr && (req_addr % 0x1000) == 0) {
  72. debug(DEBUG_USB,"USB_UPLOAD_ADDR: bank=0x%02x addr=0x%08lx crc=%04x\n",
  73. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  74. }
  75. if (req_addr && req_addr % req_bank_size == 0) {
  76. debug(DEBUG_USB,"USB_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx\n",
  77. req_bank, req_addr);
  78. req_bank++;
  79. }
  80. ret_len = USB_MAX_TRANS;
  81. /*
  82. * -------------------------------------------------------------------------
  83. */
  84. } else if (rq->bRequest == USB_DOWNLOAD_INIT) {
  85. debug(DEBUG_USB,"USB_DOWNLOAD_INIT\n");
  86. /*
  87. * -------------------------------------------------------------------------
  88. */
  89. } else if (rq->bRequest == USB_DOWNLOAD_ADDR) {
  90. debug(DEBUG_USB,"USB_DOWNLOAD_ADDR\n");
  91. /*
  92. * -------------------------------------------------------------------------
  93. */
  94. } else if (rq->bRequest == USB_BULK_UPLOAD_INIT) {
  95. req_bank = 0;
  96. rx_remaining = 0;
  97. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: %i %i\n",rq->wValue.word, rq->wIndex.word);
  98. req_bank_size = (uint32_t)(1L << rq->wValue.word);
  99. req_bank_cnt = rq->wIndex.word;
  100. req_addr_end = (uint32_t)req_bank_size * req_bank_cnt;
  101. sync_errors = 0;
  102. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: bank_size=0x%08lx bank_cnt=0x%x end_addr=0x%08lx\n",
  103. req_bank_size, req_bank_cnt, req_addr_end);
  104. if (req_addr == 0x000000){
  105. timer_start();
  106. }
  107. /*
  108. * -------------------------------------------------------------------------
  109. */
  110. } else if (rq->bRequest == USB_BULK_UPLOAD_ADDR) {
  111. req_state = REQ_STATUS_BULK_UPLOAD;
  112. req_addr = rq->wValue.word;
  113. req_addr = req_addr << 16;
  114. req_addr = req_addr | rq->wIndex.word;
  115. sram_bulk_write_start(req_addr);
  116. rx_remaining = rq->wLength.word;
  117. if (req_addr && req_addr % req_bank_size == 0) {
  118. debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  119. req_bank, req_addr,timer_stop());
  120. req_bank++;
  121. timer_start();
  122. }
  123. ret_len = USB_MAX_TRANS;
  124. /*
  125. * -------------------------------------------------------------------------
  126. */
  127. } else if (rq->bRequest == USB_BULK_UPLOAD_NEXT) {
  128. req_state = REQ_STATUS_BULK_UPLOAD;
  129. req_addr = rq->wValue.word;
  130. req_addr = req_addr << 16;
  131. req_addr = req_addr | rq->wIndex.word;
  132. rx_remaining = rq->wLength.word;
  133. #if 0
  134. if (req_addr && (req_addr % 0x1000) == 0) {
  135. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: bank=0x%02x addr=0x%08lx crc=%04x\n",
  136. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  137. }
  138. sram_bulk_write_start(req_addr);
  139. #endif
  140. if (req_addr && ( req_addr % req_bank_size) == 0) {
  141. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  142. req_bank, req_addr,timer_stop());
  143. req_bank++;
  144. timer_start();
  145. }
  146. ret_len = USB_MAX_TRANS;
  147. /*
  148. * -------------------------------------------------------------------------
  149. */
  150. } else if (rq->bRequest == USB_BULK_UPLOAD_END) {
  151. if (req_state != REQ_STATUS_BULK_UPLOAD){
  152. debug(DEBUG_USB,"USB_BULK_UPLOAD_END: ERROR state is not REQ_STATUS_BULK_UPLOAD\n");
  153. return 0;
  154. }
  155. debug(DEBUG_USB,"USB_BULK_UPLOAD_END:\n");
  156. req_state = REQ_STATUS_IDLE;
  157. sram_bulk_write_end();
  158. ret_len = 0;
  159. /*
  160. * -------------------------------------------------------------------------
  161. */
  162. } else if (rq->bRequest == USB_CRC) {
  163. req_addr = rq->wValue.word;
  164. req_addr = req_addr << 16;
  165. req_addr = req_addr | rq->wIndex.word;
  166. debug(DEBUG_USB,"USB_CRC: addr=0x%08lx \n", req_addr);
  167. crc_check_bulk_memory(0x000000, req_addr, req_bank_size);
  168. ret_len = 0;
  169. /*
  170. * -------------------------------------------------------------------------
  171. */
  172. } else if (rq->bRequest == USB_MODE_SNES) {
  173. req_state = REQ_STATUS_SNES;
  174. debug(DEBUG_USB,"USB_MODE_SNES:\n");
  175. ret_len = 0;
  176. /*
  177. * -------------------------------------------------------------------------
  178. */
  179. } else if (rq->bRequest == USB_MODE_AVR) {
  180. req_state = REQ_STATUS_AVR;
  181. debug(DEBUG_USB,"USB_MODE_AVR:\n");
  182. ret_len = 0;
  183. /*
  184. * -------------------------------------------------------------------------
  185. */
  186. } else if (rq->bRequest == USB_AVR_RESET) {
  187. debug(DEBUG_USB,"USB_AVR_RESET:\n");
  188. soft_reset();
  189. ret_len = 0;
  190. /*
  191. * -------------------------------------------------------------------------
  192. */
  193. } else if (rq->bRequest == USB_CRC_ADDR) {
  194. req_state = REQ_STATUS_CRC;
  195. req_addr = rq->wValue.word;
  196. req_addr = req_addr << 16;
  197. req_addr = req_addr | rq->wIndex.word;
  198. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%i\n", req_addr,
  199. rq->wLength.word);
  200. req_size = rq->wLength.word;
  201. req_size = req_size << 2;
  202. tx_remaining = 2;
  203. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%li\n", req_addr, req_size);
  204. crc = crc_check_memory_range(req_addr, req_size, read_buffer);
  205. tx_buffer[0] = crc & 0xff;
  206. tx_buffer[1] = (crc >> 8) & 0xff;
  207. ret_len = 2;
  208. req_state = REQ_STATUS_IDLE;
  209. }
  210. usbMsgPtr = data_buffer;
  211. return ret_len; /* default for not implemented requests: return
  212. * no data back to host */
  213. }
  214. /*
  215. * -------------------------------------------------------------------------
  216. */
  217. void test_read_write(){
  218. uint8_t i;
  219. uint32_t addr;
  220. avr_bus_active();
  221. addr = 0x000000;
  222. i = 1;
  223. while (addr++ <= 0x0000ff){
  224. sram_write(addr,i++);
  225. }
  226. addr = 0x000000;
  227. while (addr++ <= 0x0000ff){
  228. printf("read addr=0x%08lx %x\n",addr,sram_read(addr));
  229. }
  230. }
  231. void test_bulk_read_write(){
  232. uint8_t i;
  233. uint32_t addr;
  234. avr_bus_active();
  235. addr = 0x000000;
  236. i = 0;
  237. sram_bulk_write_start(addr);
  238. while (addr++ <= 0x8000){
  239. sram_bulk_write(i++);
  240. sram_bulk_write_next();
  241. }
  242. sram_bulk_write_end();
  243. addr = 0x000000;
  244. sram_bulk_read_start(addr);
  245. while (addr <= 0x8000){
  246. printf("addr=0x%08lx %x\n",addr,sram_bulk_read());
  247. sram_bulk_read_next();
  248. addr++;
  249. }
  250. sram_bulk_read_end();
  251. }
  252. void test_non_zero_memory(uint32_t bottom_addr,uint32_t top_addr)
  253. {
  254. uint32_t addr = 0;
  255. uint8_t c;
  256. sram_bulk_read_start(bottom_addr);
  257. for (addr = bottom_addr; addr < top_addr; addr++) {
  258. c = sram_bulk_read();
  259. if (c!=0xff)
  260. printf("addr=0x%08lx c=0x%x\n",addr,c);
  261. sram_bulk_read_next();
  262. }
  263. sram_bulk_read_end();
  264. }
  265. void test_crc(){
  266. printf("test_crc: clear\n");
  267. avr_bus_active();
  268. sram_bulk_set(0x000000,0x10000,0xff);
  269. printf("test_crc: crc\n");
  270. crc_check_bulk_memory(0x000000,0x10000,0x8000);
  271. printf("test_crc: check\n");
  272. test_non_zero_memory(0x000000,0x10000);
  273. }
  274. int main(void)
  275. {
  276. uint8_t i;
  277. uint8_t c;
  278. uart_init();
  279. stdout = &uart_stdout;
  280. system_init();
  281. printf("Sytem start\n");
  282. #if 0
  283. wdt_init();
  284. printf("Watchdog init\n");
  285. #endif
  286. #if 0
  287. test_read_write();
  288. test_bulk_read_write();
  289. test_crc();
  290. while(1);
  291. #endif
  292. usbInit();
  293. printf("USB init\n");
  294. usbDeviceDisconnect(); /* enforce re-enumeration, do this while
  295. * interrupts are disabled! */
  296. cli();
  297. printf("USB disconnect\n");
  298. i = 10;
  299. while (--i) { /* fake USB disconnect for > 250 ms */
  300. led_on();
  301. _delay_ms(35);
  302. led_off();
  303. _delay_ms(65);
  304. }
  305. led_on();
  306. usbDeviceConnect();
  307. printf("USB connect\n");
  308. while (1){
  309. avr_bus_active();
  310. printf("Activate AVR bus\n");
  311. printf("IRQ off\n");
  312. snes_irq_lo();
  313. snes_irq_off();
  314. printf("Set Snes lowrom\n");
  315. snes_lorom();
  316. printf("Disable snes WR\n");
  317. snes_wr_disable();
  318. sei();
  319. printf("USB poll\n");
  320. while (req_state != REQ_STATUS_SNES){
  321. usbPoll();
  322. }
  323. printf("USB poll done\n");
  324. #if 0
  325. crc_check_bulk_memory(0x000000, req_addr_end, req_bank_size);
  326. #endif
  327. snes_irq_lo();
  328. snes_irq_off();
  329. printf("IRQ off\n");
  330. if (req_bank_size == 0x8000){
  331. snes_lorom();
  332. printf("Set Snes lowrom \n");
  333. } else {
  334. snes_hirom();
  335. printf("Set Snes hirom \n");
  336. }
  337. snes_wr_disable();
  338. printf("Disable snes WR\n");
  339. snes_bus_active();
  340. printf("Activate Snes bus\n");
  341. while (req_state != REQ_STATUS_AVR){
  342. usbPoll();
  343. #if 0
  344. i = 20;
  345. while (--i) { /* fake USB disconnect for > 250 ms */
  346. _delay_ms(100);
  347. }
  348. printf("Send IRQ\n");
  349. snes_irq_lo();
  350. snes_irq_on();
  351. _delay_ms(1);
  352. //avr_bus_active();
  353. //c = sram_bulk_read();
  354. //snes_bus_active();
  355. snes_irq_off();
  356. //sram_bulk_read_start(0x003000);
  357. //printf("Read 0x3000=%c\n",c);
  358. #endif
  359. }
  360. }
  361. return 0;
  362. }