main.c 15 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. *
  11. * www.optixx.org
  12. *
  13. *
  14. * Version: 1.0
  15. * Created: 07/21/2009 03:32:16 PM
  16. * Author: david@optixx.org
  17. *
  18. * =====================================================================================
  19. */
  20. #include <avr/io.h>
  21. #include <avr/interrupt.h> /* for sei() */
  22. #include <util/delay.h> /* for _delay_ms() */
  23. #include <stdlib.h>
  24. #include <avr/pgmspace.h> /* required by usbdrv.h */
  25. #include <avr/eeprom.h>
  26. #include "usbdrv.h"
  27. #include "oddebug.h" /* This is also an example for using debug
  28. * macros */
  29. #include "config.h"
  30. #include "requests.h" /* The custom request numbers we use */
  31. #include "uart.h"
  32. #include "sram.h"
  33. #include "debug.h"
  34. #include "dump.h"
  35. #include "crc.h"
  36. #include "usb_bulk.h"
  37. #include "timer.h"
  38. #include "watchdog.h"
  39. #include "huffman-decode.h"
  40. #include "rle.h"
  41. #include "loader.h"
  42. extern const char _rom[] PROGMEM;
  43. extern FILE uart_stdout;
  44. uint8_t debug_level = ( DEBUG | DEBUG_USB | DEBUG_CRC );
  45. uint8_t read_buffer[TRANSFER_BUFFER_SIZE];
  46. uint32_t req_addr = 0;
  47. uint32_t req_addr_end = 0;
  48. uint32_t req_size;
  49. uint8_t req_bank;
  50. uint32_t req_bank_size;
  51. uint16_t req_bank_cnt;
  52. uint8_t req_state = REQ_STATUS_IDLE;
  53. uint8_t rx_remaining = 0;
  54. uint8_t tx_remaining = 0;
  55. uint16_t sync_errors = 0;
  56. uint8_t tx_buffer[32];
  57. uint8_t data_buffer[4];
  58. uint32_t addr;
  59. uint16_t crc = 0;
  60. usbMsgLen_t usbFunctionSetup(uchar data[8])
  61. {
  62. usbRequest_t *rq = (void *) data;
  63. uint8_t ret_len = 0;
  64. /*
  65. * -------------------------------------------------------------------------
  66. */
  67. if (rq->bRequest == USB_UPLOAD_INIT) {
  68. if (req_state != REQ_STATUS_IDLE){
  69. debug(DEBUG_USB,"USB_UPLOAD_INIT: ERROR state is not REQ_STATUS_IDLE\n");
  70. return 0;
  71. }
  72. req_bank = 0;
  73. rx_remaining = 0;
  74. req_bank_size = (uint32_t)1 << rq->wValue.word;
  75. sync_errors = 0;
  76. crc = 0;
  77. debug(DEBUG_USB,"USB_UPLOAD_INIT: bank_size=0x%08lx\n", req_bank_size);
  78. /*
  79. * -------------------------------------------------------------------------
  80. */
  81. } else if (rq->bRequest == USB_UPLOAD_ADDR) {
  82. req_state = REQ_STATUS_UPLOAD;
  83. req_addr = rq->wValue.word;
  84. req_addr = req_addr << 16;
  85. req_addr = req_addr | rq->wIndex.word;
  86. if (rx_remaining) {
  87. sync_errors++;
  88. debug
  89. (DEBUG_USB,"USB_UPLOAD_ADDR: Out of sync addr=0x%lx remain=%i packet=%i sync_error=%i\n",
  90. req_addr, rx_remaining, rq->wLength.word, sync_errors);
  91. ret_len = 0;
  92. }
  93. rx_remaining = rq->wLength.word;
  94. ret_len = USB_MAX_TRANS;
  95. if (req_addr && (req_addr % 0x1000) == 0) {
  96. debug(DEBUG_USB,"USB_UPLOAD_ADDR: bank=0x%02x addr=0x%08lx crc=%04x\n",
  97. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  98. }
  99. if (req_addr && req_addr % req_bank_size == 0) {
  100. debug(DEBUG_USB,"USB_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx\n",
  101. req_bank, req_addr);
  102. req_bank++;
  103. }
  104. ret_len = USB_MAX_TRANS;
  105. /*
  106. * -------------------------------------------------------------------------
  107. */
  108. } else if (rq->bRequest == USB_DOWNLOAD_INIT) {
  109. debug(DEBUG_USB,"USB_DOWNLOAD_INIT\n");
  110. /*
  111. * -------------------------------------------------------------------------
  112. */
  113. } else if (rq->bRequest == USB_DOWNLOAD_ADDR) {
  114. debug(DEBUG_USB,"USB_DOWNLOAD_ADDR\n");
  115. /*
  116. * -------------------------------------------------------------------------
  117. */
  118. } else if (rq->bRequest == USB_BULK_UPLOAD_INIT) {
  119. req_bank = 0;
  120. rx_remaining = 0;
  121. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: %i %i\n",rq->wValue.word, rq->wIndex.word);
  122. req_bank_size = (uint32_t)(1L << rq->wValue.word);
  123. req_bank_cnt = rq->wIndex.word;
  124. req_addr_end = (uint32_t)req_bank_size * req_bank_cnt;
  125. sync_errors = 0;
  126. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: bank_size=0x%08lx bank_cnt=0x%x end_addr=0x%08lx\n",
  127. req_bank_size, req_bank_cnt, req_addr_end);
  128. if (req_addr == 0x000000){
  129. timer_start();
  130. }
  131. /*
  132. * -------------------------------------------------------------------------
  133. */
  134. } else if (rq->bRequest == USB_BULK_UPLOAD_ADDR) {
  135. req_state = REQ_STATUS_BULK_UPLOAD;
  136. req_addr = rq->wValue.word;
  137. req_addr = req_addr << 16;
  138. req_addr = req_addr | rq->wIndex.word;
  139. sram_bulk_write_start(req_addr);
  140. rx_remaining = rq->wLength.word;
  141. if (req_addr && req_addr % req_bank_size == 0) {
  142. debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  143. req_bank, req_addr,timer_stop());
  144. req_bank++;
  145. timer_start();
  146. }
  147. ret_len = USB_MAX_TRANS;
  148. /*
  149. * -------------------------------------------------------------------------
  150. */
  151. } else if (rq->bRequest == USB_BULK_UPLOAD_NEXT) {
  152. req_state = REQ_STATUS_BULK_UPLOAD;
  153. req_addr = rq->wValue.word;
  154. req_addr = req_addr << 16;
  155. req_addr = req_addr | rq->wIndex.word;
  156. rx_remaining = rq->wLength.word;
  157. #if 0
  158. if (req_addr && (req_addr % 0x1000) == 0) {
  159. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: bank=0x%02x addr=0x%08lx crc=%04x\n",
  160. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  161. }
  162. sram_bulk_write_start(req_addr);
  163. #endif
  164. if (req_addr && ( req_addr % req_bank_size) == 0) {
  165. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  166. req_bank, req_addr,timer_stop());
  167. req_bank++;
  168. timer_start();
  169. }
  170. ret_len = USB_MAX_TRANS;
  171. /*
  172. * -------------------------------------------------------------------------
  173. */
  174. } else if (rq->bRequest == USB_BULK_UPLOAD_END) {
  175. if (req_state != REQ_STATUS_BULK_UPLOAD){
  176. debug(DEBUG_USB,"USB_BULK_UPLOAD_END: ERROR state is not REQ_STATUS_BULK_UPLOAD\n");
  177. return 0;
  178. }
  179. debug(DEBUG_USB,"USB_BULK_UPLOAD_END:\n");
  180. req_state = REQ_STATUS_IDLE;
  181. sram_bulk_write_end();
  182. ret_len = 0;
  183. /*
  184. * -------------------------------------------------------------------------
  185. */
  186. } else if (rq->bRequest == USB_CRC) {
  187. req_addr = rq->wValue.word;
  188. req_addr = req_addr << 16;
  189. req_addr = req_addr | rq->wIndex.word;
  190. debug(DEBUG_USB,"USB_CRC: addr=0x%08lx \n", req_addr);
  191. crc_check_bulk_memory(0x000000, req_addr, req_bank_size);
  192. ret_len = 0;
  193. /*
  194. * -------------------------------------------------------------------------
  195. */
  196. } else if (rq->bRequest == USB_MODE_SNES) {
  197. req_state = REQ_STATUS_SNES;
  198. debug(DEBUG_USB,"USB_MODE_SNES:\n");
  199. ret_len = 0;
  200. /*
  201. * -------------------------------------------------------------------------
  202. */
  203. } else if (rq->bRequest == USB_MODE_AVR) {
  204. req_state = REQ_STATUS_AVR;
  205. debug(DEBUG_USB,"USB_MODE_AVR:\n");
  206. ret_len = 0;
  207. /*
  208. * -------------------------------------------------------------------------
  209. */
  210. } else if (rq->bRequest == USB_AVR_RESET) {
  211. debug(DEBUG_USB,"USB_AVR_RESET:\n");
  212. soft_reset();
  213. ret_len = 0;
  214. /*
  215. * -------------------------------------------------------------------------
  216. */
  217. } else if (rq->bRequest == USB_CRC_ADDR) {
  218. req_state = REQ_STATUS_CRC;
  219. req_addr = rq->wValue.word;
  220. req_addr = req_addr << 16;
  221. req_addr = req_addr | rq->wIndex.word;
  222. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%i\n", req_addr,
  223. rq->wLength.word);
  224. req_size = rq->wLength.word;
  225. req_size = req_size << 2;
  226. tx_remaining = 2;
  227. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%li\n", req_addr, req_size);
  228. crc = crc_check_memory_range(req_addr, req_size, read_buffer);
  229. tx_buffer[0] = crc & 0xff;
  230. tx_buffer[1] = (crc >> 8) & 0xff;
  231. ret_len = 2;
  232. req_state = REQ_STATUS_IDLE;
  233. }
  234. usbMsgPtr = data_buffer;
  235. return ret_len; /* default for not implemented requests: return
  236. * no data back to host */
  237. }
  238. /*
  239. * -------------------------------------------------------------------------
  240. */
  241. void test_read_write(){
  242. uint8_t i;
  243. uint32_t addr;
  244. avr_bus_active();
  245. addr = 0x000000;
  246. i = 1;
  247. while (addr++ <= 0x0000ff){
  248. sram_write(addr,i++);
  249. }
  250. addr = 0x000000;
  251. while (addr++ <= 0x0000ff){
  252. printf("read addr=0x%08lx %x\n",addr,sram_read(addr));
  253. }
  254. }
  255. void test_bulk_read_write(){
  256. uint8_t i;
  257. uint32_t addr;
  258. avr_bus_active();
  259. addr = 0x000000;
  260. i = 0;
  261. sram_bulk_write_start(addr);
  262. while (addr++ <= 0x8000){
  263. sram_bulk_write(i++);
  264. sram_bulk_write_next();
  265. }
  266. sram_bulk_write_end();
  267. addr = 0x000000;
  268. sram_bulk_read_start(addr);
  269. while (addr <= 0x8000){
  270. printf("addr=0x%08lx %x\n",addr,sram_bulk_read());
  271. sram_bulk_read_next();
  272. addr++;
  273. }
  274. sram_bulk_read_end();
  275. }
  276. void test_non_zero_memory(uint32_t bottom_addr,uint32_t top_addr)
  277. {
  278. uint32_t addr = 0;
  279. uint8_t c;
  280. sram_bulk_read_start(bottom_addr);
  281. for (addr = bottom_addr; addr < top_addr; addr++) {
  282. c = sram_bulk_read();
  283. if (c!=0xff)
  284. printf("addr=0x%08lx c=0x%x\n",addr,c);
  285. sram_bulk_read_next();
  286. }
  287. sram_bulk_read_end();
  288. }
  289. void test_crc(){
  290. printf("test_crc: clear\n");
  291. avr_bus_active();
  292. sram_bulk_set(0x000000,0x10000,0xff);
  293. printf("test_crc: crc\n");
  294. crc_check_bulk_memory(0x000000,0x10000,0x8000);
  295. printf("test_crc: check\n");
  296. test_non_zero_memory(0x000000,0x10000);
  297. }
  298. uint16_t read_byte_pgm(uint16_t addr){
  299. return pgm_read_byte((PGM_VOID_P)addr);
  300. }
  301. uint16_t read_byte_ee(uint16_t addr){
  302. return eeprom_read_byte((uint8_t*)addr);
  303. }
  304. void decompress(PGM_VOID_P addr, uint16_t(*fp)(uint16_t)){
  305. uint16_t c;
  306. uint32_t i = 0;
  307. huffman_dec_ctx_t ctx;
  308. huffman_dec_init(&ctx, fp);
  309. huffman_dec_set_addr(&ctx, (uint16_t)addr);
  310. while(1){
  311. i++;
  312. c=huffman_dec_byte(&ctx);
  313. if (i%1024==0)
  314. printf(".");
  315. if(c>0xff){
  316. return;
  317. }
  318. c&=0xff;
  319. sram_bulk_write(c);
  320. }
  321. }
  322. void decompress_huffman(void){
  323. printf("Decompress Rom %p to 0x000000\n",(void*)_rom);
  324. sram_bulk_write_start(0x000000);
  325. decompress(&_rom,read_byte_pgm);
  326. sram_bulk_write_end();
  327. printf("Done\n");
  328. }
  329. void send_reset(){
  330. printf("Reset Snes\n");
  331. snes_reset_on();
  332. snes_reset_lo();
  333. _delay_ms(2);
  334. snes_reset_hi();
  335. snes_reset_off();
  336. }
  337. void send_irq(){
  338. snes_irq_on();
  339. snes_irq_lo();
  340. _delay_us(20);
  341. snes_irq_hi();
  342. snes_irq_off();
  343. }
  344. void set_rom_mode(){
  345. if (req_bank_size == 0x8000){
  346. snes_lorom();
  347. printf("Set Snes lowrom \n");
  348. } else {
  349. snes_hirom();
  350. printf("Set Snes hirom \n");
  351. }
  352. }
  353. void usb_connect(){
  354. uint8_t i = 0;
  355. printf("USB init\n");
  356. usbDeviceDisconnect(); /* enforce re-enumeration, do this while */
  357. cli();
  358. printf("USB disconnect\n");
  359. i = 10;
  360. while (--i) { /* fake USB disconnect for > 250 ms */
  361. led_on();
  362. _delay_ms(35);
  363. led_off();
  364. _delay_ms(65);
  365. }
  366. led_on();
  367. usbDeviceConnect();
  368. printf("USB connect\n");
  369. }
  370. void boot_startup_rom(){
  371. uint8_t i = 0;
  372. printf("Activate AVR bus\n");
  373. avr_bus_active();
  374. printf("IRQ off\n");
  375. snes_irq_lo();
  376. snes_irq_off();
  377. snes_lorom();
  378. printf("Set Snes lowrom \n");
  379. /*
  380. printf("Set Snes hirom\n");
  381. snes_hirom();
  382. printf("Disable snes WR\n");
  383. snes_wr_disable();
  384. printf("IRQ off\n");
  385. snes_irq_lo();
  386. snes_irq_off();
  387. */
  388. rle_decode(&_rom, ROM_SIZE, 0x000000);
  389. dump_memory(0x10000 - 0x100, 0x10000);
  390. snes_reset_hi();
  391. snes_reset_off();
  392. snes_irq_lo();
  393. snes_irq_off();
  394. printf("IRQ off\n");
  395. snes_hirom();
  396. snes_wr_disable();
  397. printf("Disable snes WR\n");
  398. snes_bus_active();
  399. printf("Activate Snes bus\n");
  400. _delay_ms(100);
  401. printf("Reset Snes\n");
  402. send_reset();
  403. i = 20;
  404. printf("Wait");
  405. while (--i){
  406. _delay_ms(500);
  407. printf(".");
  408. }
  409. printf("\n");
  410. }
  411. int main(void)
  412. {
  413. uint8_t i;
  414. uint16_t irq_count = 0;
  415. uart_init();
  416. stdout = &uart_stdout;
  417. printf("Sytem start\n");
  418. system_init();
  419. #if 0
  420. test_read_write();
  421. test_bulk_read_write();
  422. test_crc();
  423. while(1);
  424. #endif
  425. printf("Boot startup rom\n");
  426. boot_startup_rom();
  427. usbInit();
  428. usb_connect();
  429. while (1){
  430. avr_bus_active();
  431. printf("Activate AVR bus\n");
  432. printf("IRQ off\n");
  433. snes_irq_lo();
  434. snes_irq_off();
  435. printf("Set Snes lowrom\n");
  436. snes_lorom();
  437. printf("Disable snes WR\n");
  438. snes_wr_disable();
  439. sei();
  440. printf("USB poll\n");
  441. while (req_state != REQ_STATUS_SNES){
  442. usbPoll();
  443. }
  444. printf("USB poll done\n");
  445. snes_reset_hi();
  446. snes_reset_off();
  447. snes_irq_lo();
  448. snes_irq_off();
  449. printf("IRQ off\n");
  450. set_rom_mode();
  451. snes_wr_disable();
  452. printf("Disable snes WR\n");
  453. snes_bus_active();
  454. printf("Activate Snes bus\n");
  455. _delay_ms(100);
  456. printf("Reset Snes\n");
  457. send_reset();
  458. printf("Poll\n");
  459. while (req_state != REQ_STATUS_AVR){
  460. usbPoll();
  461. #if 1
  462. i = 10;
  463. while (--i) { /* fake USB disconnect for > 250 ms */
  464. _delay_ms(100);
  465. }
  466. printf("Send IRQ %i\n",++irq_count);
  467. send_irq();
  468. #endif
  469. #if 0
  470. avr_bus_active();
  471. sram_bulk_read_start(0x003000);
  472. c = sram_bulk_read();
  473. i = 5;
  474. while (--i) {
  475. _delay_ms(500);
  476. printf("Wait to switch to snes mode %i\n", i);
  477. }
  478. if (req_bank_size == 0x8000){
  479. snes_lorom();
  480. printf("Set Snes lowrom \n");
  481. } else {
  482. snes_hirom();
  483. printf("Set Snes hirom \n");
  484. }
  485. snes_wr_disable();
  486. printf("Disable snes WR\n");
  487. snes_bus_active();
  488. printf("Activate Snes bus\n");
  489. printf("Read 0x3000=%c\n",c);
  490. #endif
  491. }
  492. }
  493. return 0;
  494. }