main.c 15 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. *
  11. * www.optixx.org
  12. *
  13. *
  14. * Version: 1.0
  15. * Created: 07/21/2009 03:32:16 PM
  16. * Author: david@optixx.org
  17. *
  18. * =====================================================================================
  19. */
  20. #include <avr/io.h>
  21. #include <avr/interrupt.h> /* for sei() */
  22. #include <util/delay.h> /* for _delay_ms() */
  23. #include <stdlib.h>
  24. #include <avr/pgmspace.h> /* required by usbdrv.h */
  25. #include <avr/eeprom.h>
  26. #include "usbdrv.h"
  27. #include "oddebug.h" /* This is also an example for using debug
  28. * macros */
  29. #include "config.h"
  30. #include "requests.h" /* The custom request numbers we use */
  31. #include "uart.h"
  32. #include "sram.h"
  33. #include "debug.h"
  34. #include "dump.h"
  35. #include "crc.h"
  36. #include "usb_bulk.h"
  37. #include "timer.h"
  38. #include "watchdog.h"
  39. #include "huffman-decode.h"
  40. #include "rle.h"
  41. extern const char _rom[] PROGMEM;
  42. extern FILE uart_stdout;
  43. uint8_t debug_level = ( DEBUG | DEBUG_USB | DEBUG_CRC );
  44. uint8_t read_buffer[TRANSFER_BUFFER_SIZE];
  45. uint32_t req_addr = 0;
  46. uint32_t req_addr_end = 0;
  47. uint32_t req_size;
  48. uint8_t req_bank;
  49. uint32_t req_bank_size;
  50. uint16_t req_bank_cnt;
  51. uint8_t req_state = REQ_STATUS_IDLE;
  52. uint8_t rx_remaining = 0;
  53. uint8_t tx_remaining = 0;
  54. uint16_t sync_errors = 0;
  55. uint8_t tx_buffer[32];
  56. uint8_t data_buffer[4];
  57. uint32_t addr;
  58. uint16_t crc = 0;
  59. usbMsgLen_t usbFunctionSetup(uchar data[8])
  60. {
  61. usbRequest_t *rq = (void *) data;
  62. uint8_t ret_len = 0;
  63. /*
  64. * -------------------------------------------------------------------------
  65. */
  66. if (rq->bRequest == USB_UPLOAD_INIT) {
  67. if (req_state != REQ_STATUS_IDLE){
  68. debug(DEBUG_USB,"USB_UPLOAD_INIT: ERROR state is not REQ_STATUS_IDLE\n");
  69. return 0;
  70. }
  71. req_bank = 0;
  72. rx_remaining = 0;
  73. req_bank_size = (uint32_t)1 << rq->wValue.word;
  74. sync_errors = 0;
  75. crc = 0;
  76. debug(DEBUG_USB,"USB_UPLOAD_INIT: bank_size=0x%08lx\n", req_bank_size);
  77. /*
  78. * -------------------------------------------------------------------------
  79. */
  80. } else if (rq->bRequest == USB_UPLOAD_ADDR) {
  81. req_state = REQ_STATUS_UPLOAD;
  82. req_addr = rq->wValue.word;
  83. req_addr = req_addr << 16;
  84. req_addr = req_addr | rq->wIndex.word;
  85. if (rx_remaining) {
  86. sync_errors++;
  87. debug
  88. (DEBUG_USB,"USB_UPLOAD_ADDR: Out of sync addr=0x%lx remain=%i packet=%i sync_error=%i\n",
  89. req_addr, rx_remaining, rq->wLength.word, sync_errors);
  90. ret_len = 0;
  91. }
  92. rx_remaining = rq->wLength.word;
  93. ret_len = USB_MAX_TRANS;
  94. if (req_addr && (req_addr % 0x1000) == 0) {
  95. debug(DEBUG_USB,"USB_UPLOAD_ADDR: bank=0x%02x addr=0x%08lx crc=%04x\n",
  96. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  97. }
  98. if (req_addr && req_addr % req_bank_size == 0) {
  99. debug(DEBUG_USB,"USB_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx\n",
  100. req_bank, req_addr);
  101. req_bank++;
  102. }
  103. ret_len = USB_MAX_TRANS;
  104. /*
  105. * -------------------------------------------------------------------------
  106. */
  107. } else if (rq->bRequest == USB_DOWNLOAD_INIT) {
  108. debug(DEBUG_USB,"USB_DOWNLOAD_INIT\n");
  109. /*
  110. * -------------------------------------------------------------------------
  111. */
  112. } else if (rq->bRequest == USB_DOWNLOAD_ADDR) {
  113. debug(DEBUG_USB,"USB_DOWNLOAD_ADDR\n");
  114. /*
  115. * -------------------------------------------------------------------------
  116. */
  117. } else if (rq->bRequest == USB_BULK_UPLOAD_INIT) {
  118. req_bank = 0;
  119. rx_remaining = 0;
  120. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: %i %i\n",rq->wValue.word, rq->wIndex.word);
  121. req_bank_size = (uint32_t)(1L << rq->wValue.word);
  122. req_bank_cnt = rq->wIndex.word;
  123. req_addr_end = (uint32_t)req_bank_size * req_bank_cnt;
  124. sync_errors = 0;
  125. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: bank_size=0x%08lx bank_cnt=0x%x end_addr=0x%08lx\n",
  126. req_bank_size, req_bank_cnt, req_addr_end);
  127. if (req_addr == 0x000000){
  128. timer_start();
  129. }
  130. /*
  131. * -------------------------------------------------------------------------
  132. */
  133. } else if (rq->bRequest == USB_BULK_UPLOAD_ADDR) {
  134. req_state = REQ_STATUS_BULK_UPLOAD;
  135. req_addr = rq->wValue.word;
  136. req_addr = req_addr << 16;
  137. req_addr = req_addr | rq->wIndex.word;
  138. sram_bulk_write_start(req_addr);
  139. rx_remaining = rq->wLength.word;
  140. if (req_addr && req_addr % req_bank_size == 0) {
  141. debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  142. req_bank, req_addr,timer_stop());
  143. req_bank++;
  144. timer_start();
  145. }
  146. ret_len = USB_MAX_TRANS;
  147. /*
  148. * -------------------------------------------------------------------------
  149. */
  150. } else if (rq->bRequest == USB_BULK_UPLOAD_NEXT) {
  151. req_state = REQ_STATUS_BULK_UPLOAD;
  152. req_addr = rq->wValue.word;
  153. req_addr = req_addr << 16;
  154. req_addr = req_addr | rq->wIndex.word;
  155. rx_remaining = rq->wLength.word;
  156. #if 0
  157. if (req_addr && (req_addr % 0x1000) == 0) {
  158. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: bank=0x%02x addr=0x%08lx crc=%04x\n",
  159. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  160. }
  161. sram_bulk_write_start(req_addr);
  162. #endif
  163. if (req_addr && ( req_addr % req_bank_size) == 0) {
  164. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  165. req_bank, req_addr,timer_stop());
  166. req_bank++;
  167. timer_start();
  168. }
  169. ret_len = USB_MAX_TRANS;
  170. /*
  171. * -------------------------------------------------------------------------
  172. */
  173. } else if (rq->bRequest == USB_BULK_UPLOAD_END) {
  174. if (req_state != REQ_STATUS_BULK_UPLOAD){
  175. debug(DEBUG_USB,"USB_BULK_UPLOAD_END: ERROR state is not REQ_STATUS_BULK_UPLOAD\n");
  176. return 0;
  177. }
  178. debug(DEBUG_USB,"USB_BULK_UPLOAD_END:\n");
  179. req_state = REQ_STATUS_IDLE;
  180. sram_bulk_write_end();
  181. ret_len = 0;
  182. /*
  183. * -------------------------------------------------------------------------
  184. */
  185. } else if (rq->bRequest == USB_CRC) {
  186. req_addr = rq->wValue.word;
  187. req_addr = req_addr << 16;
  188. req_addr = req_addr | rq->wIndex.word;
  189. debug(DEBUG_USB,"USB_CRC: addr=0x%08lx \n", req_addr);
  190. crc_check_bulk_memory(0x000000, req_addr, req_bank_size);
  191. ret_len = 0;
  192. /*
  193. * -------------------------------------------------------------------------
  194. */
  195. } else if (rq->bRequest == USB_MODE_SNES) {
  196. req_state = REQ_STATUS_SNES;
  197. debug(DEBUG_USB,"USB_MODE_SNES:\n");
  198. ret_len = 0;
  199. /*
  200. * -------------------------------------------------------------------------
  201. */
  202. } else if (rq->bRequest == USB_MODE_AVR) {
  203. req_state = REQ_STATUS_AVR;
  204. debug(DEBUG_USB,"USB_MODE_AVR:\n");
  205. ret_len = 0;
  206. /*
  207. * -------------------------------------------------------------------------
  208. */
  209. } else if (rq->bRequest == USB_AVR_RESET) {
  210. debug(DEBUG_USB,"USB_AVR_RESET:\n");
  211. soft_reset();
  212. ret_len = 0;
  213. /*
  214. * -------------------------------------------------------------------------
  215. */
  216. } else if (rq->bRequest == USB_CRC_ADDR) {
  217. req_state = REQ_STATUS_CRC;
  218. req_addr = rq->wValue.word;
  219. req_addr = req_addr << 16;
  220. req_addr = req_addr | rq->wIndex.word;
  221. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%i\n", req_addr,
  222. rq->wLength.word);
  223. req_size = rq->wLength.word;
  224. req_size = req_size << 2;
  225. tx_remaining = 2;
  226. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%li\n", req_addr, req_size);
  227. crc = crc_check_memory_range(req_addr, req_size, read_buffer);
  228. tx_buffer[0] = crc & 0xff;
  229. tx_buffer[1] = (crc >> 8) & 0xff;
  230. ret_len = 2;
  231. req_state = REQ_STATUS_IDLE;
  232. }
  233. usbMsgPtr = data_buffer;
  234. return ret_len; /* default for not implemented requests: return
  235. * no data back to host */
  236. }
  237. /*
  238. * -------------------------------------------------------------------------
  239. */
  240. void test_read_write(){
  241. uint8_t i;
  242. uint32_t addr;
  243. avr_bus_active();
  244. addr = 0x000000;
  245. i = 1;
  246. while (addr++ <= 0x0000ff){
  247. sram_write(addr,i++);
  248. }
  249. addr = 0x000000;
  250. while (addr++ <= 0x0000ff){
  251. printf("read addr=0x%08lx %x\n",addr,sram_read(addr));
  252. }
  253. }
  254. void test_bulk_read_write(){
  255. uint8_t i;
  256. uint32_t addr;
  257. avr_bus_active();
  258. addr = 0x000000;
  259. i = 0;
  260. sram_bulk_write_start(addr);
  261. while (addr++ <= 0x8000){
  262. sram_bulk_write(i++);
  263. sram_bulk_write_next();
  264. }
  265. sram_bulk_write_end();
  266. addr = 0x000000;
  267. sram_bulk_read_start(addr);
  268. while (addr <= 0x8000){
  269. printf("addr=0x%08lx %x\n",addr,sram_bulk_read());
  270. sram_bulk_read_next();
  271. addr++;
  272. }
  273. sram_bulk_read_end();
  274. }
  275. void test_non_zero_memory(uint32_t bottom_addr,uint32_t top_addr)
  276. {
  277. uint32_t addr = 0;
  278. uint8_t c;
  279. sram_bulk_read_start(bottom_addr);
  280. for (addr = bottom_addr; addr < top_addr; addr++) {
  281. c = sram_bulk_read();
  282. if (c!=0xff)
  283. printf("addr=0x%08lx c=0x%x\n",addr,c);
  284. sram_bulk_read_next();
  285. }
  286. sram_bulk_read_end();
  287. }
  288. void test_crc(){
  289. printf("test_crc: clear\n");
  290. avr_bus_active();
  291. sram_bulk_set(0x000000,0x10000,0xff);
  292. printf("test_crc: crc\n");
  293. crc_check_bulk_memory(0x000000,0x10000,0x8000);
  294. printf("test_crc: check\n");
  295. test_non_zero_memory(0x000000,0x10000);
  296. }
  297. uint16_t read_byte_pgm(uint16_t addr){
  298. return pgm_read_byte((PGM_VOID_P)addr);
  299. }
  300. uint16_t read_byte_ee(uint16_t addr){
  301. return eeprom_read_byte((uint8_t*)addr);
  302. }
  303. void decompress(PGM_VOID_P addr, uint16_t(*fp)(uint16_t)){
  304. uint16_t c;
  305. uint32_t i = 0;
  306. huffman_dec_ctx_t ctx;
  307. huffman_dec_init(&ctx, fp);
  308. huffman_dec_set_addr(&ctx, (uint16_t)addr);
  309. while(1){
  310. i++;
  311. c=huffman_dec_byte(&ctx);
  312. if (i%1024==0)
  313. printf(".");
  314. if(c>0xff){
  315. return;
  316. }
  317. c&=0xff;
  318. sram_bulk_write(c);
  319. }
  320. }
  321. void decompress_huffman(void){
  322. printf("Decompress Rom %p to 0x000000\n",(void*)_rom);
  323. sram_bulk_write_start(0x000000);
  324. decompress(&_rom,read_byte_pgm);
  325. sram_bulk_write_end();
  326. printf("Done\n");
  327. }
  328. void decompress_rle(void){
  329. rle_decode(&_rom,30180,0x000000);
  330. printf("Done\n");
  331. }
  332. void boot_startup_rom(){
  333. uint8_t i = 0;
  334. printf("Activate AVR bus\n");
  335. avr_bus_active();
  336. printf("IRQ off\n");
  337. snes_irq_lo();
  338. snes_irq_off();
  339. snes_lorom();
  340. printf("Set Snes lowrom \n");
  341. /*
  342. printf("Set Snes hirom\n");
  343. snes_hirom();
  344. printf("Disable snes WR\n");
  345. snes_wr_disable();
  346. printf("IRQ off\n");
  347. snes_irq_lo();
  348. snes_irq_off();
  349. */
  350. decompress_rle();
  351. dump_memory(0x10000 - 0x100, 0x10000);
  352. //crc_check_bulk_memory(0x00000, 0x10000, 0x8000);
  353. snes_reset_hi();
  354. snes_reset_off();
  355. snes_irq_lo();
  356. snes_irq_off();
  357. printf("IRQ off\n");
  358. snes_hirom();
  359. snes_wr_disable();
  360. printf("Disable snes WR\n");
  361. snes_bus_active();
  362. printf("Activate Snes bus\n");
  363. _delay_ms(100);
  364. printf("Reset Snes\n");
  365. send_reset();
  366. i = 20;
  367. printf("Wait");
  368. while (--i){
  369. _delay_ms(500);
  370. printf(".");
  371. }
  372. printf("\n");
  373. }
  374. void send_reset(){
  375. printf("Reset Snes\n");
  376. snes_reset_on();
  377. snes_reset_lo();
  378. _delay_ms(2);
  379. snes_reset_hi();
  380. snes_reset_off();
  381. }
  382. void send_irq(){
  383. snes_irq_on();
  384. snes_irq_lo();
  385. _delay_us(20);
  386. snes_irq_hi();
  387. snes_irq_off();
  388. }
  389. void set_rom_mode(){
  390. if (req_bank_size == 0x8000){
  391. snes_lorom();
  392. printf("Set Snes lowrom \n");
  393. } else {
  394. snes_hirom();
  395. printf("Set Snes hirom \n");
  396. }
  397. }
  398. void usb_connect(){
  399. uint8_t i = 0;
  400. printf("USB init\n");
  401. usbDeviceDisconnect(); /* enforce re-enumeration, do this while */
  402. cli();
  403. printf("USB disconnect\n");
  404. i = 10;
  405. while (--i) { /* fake USB disconnect for > 250 ms */
  406. led_on();
  407. _delay_ms(35);
  408. led_off();
  409. _delay_ms(65);
  410. }
  411. led_on();
  412. usbDeviceConnect();
  413. printf("USB connect\n");
  414. }
  415. int main(void)
  416. {
  417. uint8_t i;
  418. uint16_t irq_count = 0;
  419. uart_init();
  420. stdout = &uart_stdout;
  421. printf("Sytem start\n");
  422. system_init();
  423. #if 0
  424. test_read_write();
  425. test_bulk_read_write();
  426. test_crc();
  427. while(1);
  428. #endif
  429. printf("Boot startup rom\n");
  430. boot_startup_rom();
  431. usbInit();
  432. usb_connect();
  433. while (1){
  434. avr_bus_active();
  435. printf("Activate AVR bus\n");
  436. printf("IRQ off\n");
  437. snes_irq_lo();
  438. snes_irq_off();
  439. printf("Set Snes lowrom\n");
  440. snes_lorom();
  441. printf("Disable snes WR\n");
  442. snes_wr_disable();
  443. sei();
  444. printf("USB poll\n");
  445. while (req_state != REQ_STATUS_SNES){
  446. usbPoll();
  447. }
  448. printf("USB poll done\n");
  449. snes_reset_hi();
  450. snes_reset_off();
  451. snes_irq_lo();
  452. snes_irq_off();
  453. printf("IRQ off\n");
  454. set_rom_mode();
  455. snes_wr_disable();
  456. printf("Disable snes WR\n");
  457. snes_bus_active();
  458. printf("Activate Snes bus\n");
  459. _delay_ms(100);
  460. printf("Reset Snes\n");
  461. send_reset();
  462. printf("Poll\n");
  463. while (req_state != REQ_STATUS_AVR){
  464. usbPoll();
  465. #if 1
  466. i = 10;
  467. while (--i) { /* fake USB disconnect for > 250 ms */
  468. _delay_ms(100);
  469. }
  470. printf("Send IRQ %i\n",++irq_count);
  471. send_irq();
  472. #endif
  473. #if 0
  474. avr_bus_active();
  475. sram_bulk_read_start(0x003000);
  476. c = sram_bulk_read();
  477. i = 5;
  478. while (--i) {
  479. _delay_ms(500);
  480. printf("Wait to switch to snes mode %i\n", i);
  481. }
  482. if (req_bank_size == 0x8000){
  483. snes_lorom();
  484. printf("Set Snes lowrom \n");
  485. } else {
  486. snes_hirom();
  487. printf("Set Snes hirom \n");
  488. }
  489. snes_wr_disable();
  490. printf("Disable snes WR\n");
  491. snes_bus_active();
  492. printf("Activate Snes bus\n");
  493. printf("Read 0x3000=%c\n",c);
  494. #endif
  495. }
  496. }
  497. return 0;
  498. }