sram.c 8.5 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * .d8888b 88888b. .d88b. .d8888b 888d888 8888b. 88888b.d88b.
  5. * 88K 888 "88b d8P Y8b 88K 888P" "88b 888 "888 "88b
  6. * "Y8888b. 888 888 88888888 "Y8888b. 888 .d888888 888 888 888
  7. * X88 888 888 Y8b. X88 888 888 888 888 888 888
  8. * 88888P' 888 888 "Y8888 88888P' 888 "Y888888 888 888 888
  9. *
  10. * www.optixx.org
  11. *
  12. *
  13. * Version: 1.0
  14. * Created: 07/21/2009 03:32:16 PM
  15. * Author: david@optixx.org
  16. *
  17. * =====================================================================================
  18. */
  19. #include <stdlib.h>
  20. #include <stdint.h>
  21. #include <avr/io.h>
  22. #include <util/delay.h> /* for _delay_ms() */
  23. #include "config.h"
  24. #include "sram.h"
  25. #include "uart.h"
  26. #include "debug.h"
  27. void system_init(void)
  28. {
  29. /*-------------------------------------------------*/
  30. DDRA = 0x00;
  31. PORTA = 0x00;
  32. /*-------------------------------------------------*/
  33. DDRC |= ( (1 << AVR_ADDR_LATCH_PIN)
  34. | (1 << AVR_ADDR_SCK_PIN)
  35. | (1 << AVR_ADDR_SER_PIN)
  36. | (1 << AVR_ADDR_LOAD_PIN)
  37. | (1 << AVR_ADDR_DOWN_PIN)
  38. | (1 << AVR_ADDR_UP_PIN));
  39. DDRC &= ~ (1 << SNES_WR_PIN);
  40. PORTC &= ~((1 << AVR_ADDR_LATCH_PIN)
  41. | (1 << AVR_ADDR_SCK_PIN)
  42. | (1 << SNES_WR_PIN));
  43. PORTC |= ( (1 << AVR_ADDR_DOWN_PIN)
  44. | (1 << AVR_ADDR_UP_PIN)
  45. | (1 << AVR_ADDR_LOAD_PIN));
  46. //| (1 << SNES_WR_PIN));
  47. /*-------------------------------------------------*/
  48. DDRB |= ( (1 << AVR_RD_PIN)
  49. | (1 << AVR_WR_PIN)
  50. | (1 << AVR_CS_PIN)
  51. | (1 << SNES_IRQ_PIN));
  52. PORTB |= ( (1 << AVR_RD_PIN)
  53. | (1 << AVR_WR_PIN)
  54. | (1 << AVR_CS_PIN)
  55. | (1 << SNES_IRQ_PIN));
  56. /*-------------------------------------------------*/
  57. DDRD |= ( (1 << AVR_SNES_SW_PIN)
  58. | (1 << HI_LOROM_SW_PIN)
  59. | (1 << SNES_WR_EN_PIN));
  60. PORTD |= (1 << HI_LOROM_SW_PIN);
  61. PORTD &= ~((1 << AVR_SNES_SW_PIN)
  62. | (1 << SNES_WR_EN_PIN));
  63. /*-------------------------------------------------*/
  64. }
  65. void sreg_set(uint32_t addr)
  66. {
  67. uint8_t i = 24;
  68. debug(DEBUG_SREG,"sreg_set: addr=0x%08lx",addr);
  69. while(i--) {
  70. if ((addr & ( 1L << i))){
  71. debug(DEBUG_SREG,"1");
  72. AVR_ADDR_SER_PORT |= ( 1 << AVR_ADDR_SER_PIN);
  73. } else {
  74. AVR_ADDR_SER_PORT &= ~( 1 << AVR_ADDR_SER_PIN);
  75. debug(DEBUG_SREG,"0");
  76. }
  77. AVR_ADDR_SCK_PORT |= (1 << AVR_ADDR_SCK_PIN);
  78. AVR_ADDR_SCK_PORT &= ~(1 << AVR_ADDR_SCK_PIN);
  79. }
  80. debug(DEBUG_SREG,"\n");
  81. AVR_ADDR_LATCH_PORT |= (1 << AVR_ADDR_LATCH_PIN);
  82. AVR_ADDR_LATCH_PORT &= ~(1 << AVR_ADDR_LATCH_PIN);
  83. counter_load();
  84. }
  85. void sram_bulk_read_start(uint32_t addr)
  86. {
  87. debug(DEBUG_SRAM,"sram_bulk_read_start: addr=0x%08lx\n\r", addr);
  88. avr_data_in();
  89. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  90. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  91. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  92. sreg_set(addr);
  93. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  94. asm volatile ("nop");
  95. asm volatile ("nop");
  96. asm volatile ("nop");
  97. asm volatile ("nop");
  98. asm volatile ("nop");
  99. asm volatile ("nop");
  100. }
  101. inline void sram_bulk_read_next(void)
  102. {
  103. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  104. counter_up();
  105. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  106. asm volatile ("nop");
  107. asm volatile ("nop");
  108. asm volatile ("nop");
  109. asm volatile ("nop");
  110. asm volatile ("nop");
  111. asm volatile ("nop");
  112. }
  113. inline uint8_t sram_bulk_read(void)
  114. {
  115. return AVR_DATA_PIN;
  116. }
  117. void sram_bulk_read_end(void)
  118. {
  119. debug(DEBUG_SRAM,"sram_bulk_read_end:\n");
  120. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  121. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  122. avr_data_in();
  123. }
  124. uint8_t sram_read(uint32_t addr)
  125. {
  126. uint8_t byte;
  127. debug(DEBUG_SRAM_RAW,"sram_read: addr=0x%08lx\n\r", addr);
  128. avr_data_in();
  129. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  130. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  131. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  132. sreg_set(addr);
  133. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  134. asm volatile ("nop");
  135. asm volatile ("nop");
  136. asm volatile ("nop");
  137. asm volatile ("nop");
  138. asm volatile ("nop");
  139. asm volatile ("nop");
  140. byte = AVR_DATA_PIN;
  141. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  142. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  143. avr_data_in();
  144. return byte;
  145. }
  146. void sram_bulk_write_start(uint32_t addr)
  147. {
  148. debug(DEBUG_SRAM,"sram_bulk_write_start: addr=0x%08lx\n\r", addr);
  149. avr_data_out();
  150. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  151. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  152. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  153. sreg_set(addr);
  154. AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
  155. }
  156. inline void sram_bulk_write_next(void)
  157. {
  158. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  159. counter_up();
  160. AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
  161. }
  162. inline void sram_bulk_write( uint8_t data)
  163. {
  164. AVR_DATA_PORT = data;
  165. }
  166. void sram_bulk_write_end(void)
  167. {
  168. debug(DEBUG_SRAM,"sram_bulk_write_end:");
  169. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  170. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  171. avr_data_in();
  172. }
  173. void sram_write(uint32_t addr, uint8_t data)
  174. {
  175. debug(DEBUG_SRAM_RAW,"sram_write: addr=0x%08lx data=%x\n\r", addr, data);
  176. avr_data_out();
  177. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  178. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  179. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  180. sreg_set(addr);
  181. AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
  182. AVR_DATA_PORT = data;
  183. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  184. asm volatile ("nop");
  185. asm volatile ("nop");
  186. asm volatile ("nop");
  187. asm volatile ("nop");
  188. asm volatile ("nop");
  189. asm volatile ("nop");
  190. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  191. avr_data_in();
  192. }
  193. void sram_bulk_copy(uint32_t addr, uint8_t * src, uint32_t len)
  194. {
  195. uint32_t i;
  196. uint8_t *ptr = src;
  197. debug(DEBUG_SRAM,"sram_copy: addr=0x%08lx src=0x%p len=%li\n\r", addr,src,len);
  198. sram_bulk_write_start(addr);
  199. for (i = addr; i < (addr + len); i++){
  200. sram_bulk_write(*ptr++);
  201. sram_bulk_write_next();
  202. }
  203. sram_bulk_write_end();
  204. }
  205. void sram_bulk_read_buffer(uint32_t addr, uint8_t * dst, uint32_t len)
  206. {
  207. uint32_t i;
  208. uint8_t *ptr = dst;
  209. debug(DEBUG_SRAM,"sram_bulk_read_buffer: addr=0x%08lx dst=0x%p len=%li\n\r", addr,dst,len);
  210. sram_bulk_read_start(addr);
  211. for (i = addr; i < (addr + len); i++) {
  212. *ptr = sram_bulk_read();
  213. sram_bulk_read_next();
  214. ptr++;
  215. }
  216. sram_bulk_read_end();
  217. }
  218. void sram_bulk_set(uint32_t addr, uint32_t len,uint8_t value){
  219. uint32_t i;
  220. debug(DEBUG_SRAM,"sram_bulk_set: addr=0x%08lx len=%li\n\r", addr,len);
  221. sram_bulk_write_start(addr);
  222. for (i = addr; i < (addr + len); i++) {
  223. if (0 == i % 0xfff)
  224. debug(DEBUG_SRAM,"sram_bulk_set: addr=0x%08lx\n\r", i);
  225. sram_bulk_write(value);
  226. sram_bulk_write_next();
  227. }
  228. sram_bulk_write_end();
  229. }
  230. void sram_setr(uint32_t addr, uint32_t len,uint8_t value)
  231. {
  232. uint32_t i;
  233. debug(DEBUG_SRAM,"sram_clear: addr=0x%08lx len=%li\n\r", addr,len);
  234. for (i = addr; i < (addr + len); i++) {
  235. if (0 == i % 0xfff)
  236. debug(DEBUG_SRAM,"sram_clear: addr=0x%08lx\n\r", i);
  237. sram_write(i, value);
  238. }
  239. }
  240. void sram_copy(uint32_t addr, uint8_t * src, uint32_t len)
  241. {
  242. uint32_t i;
  243. uint8_t *ptr = src;
  244. debug(DEBUG_SRAM,"sram_copy: addr=0x%08lx src=0x%p len=%li\n\r", addr,src,len);
  245. for (i = addr; i < (addr + len); i++)
  246. sram_write(i, *ptr++);
  247. }
  248. void sram_read_buffer(uint32_t addr, uint8_t * dst, uint32_t len)
  249. {
  250. uint32_t i;
  251. uint8_t *ptr = dst;
  252. debug(DEBUG_SRAM,"sram_read_buffer: addr=0x%08lx dst=0x%p len=%li\n\r", addr,dst,len);
  253. for (i = addr; i < (addr + len); i++) {
  254. *ptr = sram_read(i);
  255. ptr++;
  256. }
  257. }
  258. uint8_t sram_check(uint8_t * buffer, uint32_t len)
  259. {
  260. uint16_t cnt;
  261. debug(DEBUG_SRAM,"sram_check: len=%li\n\r",len);
  262. for (cnt = 0; cnt < len; cnt++)
  263. if (buffer[cnt])
  264. return 1;
  265. return 0;
  266. }