crc.c 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115
  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. *
  11. * www.optixx.org
  12. *
  13. *
  14. * Version: 1.0
  15. * Created: 07/21/2009 03:32:16 PM
  16. * Author: david@optixx.org
  17. *
  18. * =====================================================================================
  19. */
  20. #include <stdlib.h>
  21. #include <stdint.h>
  22. #include "crc.h"
  23. #include "uart.h"
  24. #include "config.h"
  25. #include "sram.h"
  26. #include "debug.h"
  27. #include "info.h"
  28. extern FILE uart_stdout;
  29. uint16_t crc_xmodem_update(uint16_t crc, uint8_t data)
  30. {
  31. int i;
  32. crc = crc ^ ((uint16_t) data << 8);
  33. for (i = 0; i < 8; i++) {
  34. if (crc & 0x8000)
  35. crc = (crc << 1) ^ 0x1021;
  36. else
  37. crc <<= 1;
  38. }
  39. return crc;
  40. }
  41. uint16_t do_crc(uint8_t * data, uint16_t size)
  42. {
  43. uint16_t crc = 0;
  44. uint16_t i;
  45. for (i = 0; i < size; i++) {
  46. crc = crc_xmodem_update(crc, data[i]);
  47. }
  48. return crc;
  49. }
  50. uint16_t do_crc_update(uint16_t crc, uint8_t * data, uint16_t size)
  51. {
  52. uint16_t i;
  53. for (i = 0; i < size; i++)
  54. crc = crc_xmodem_update(crc, data[i]);
  55. return crc;
  56. }
  57. uint16_t crc_check_bulk_memory(uint32_t bottom_addr, uint32_t top_addr,
  58. uint32_t bank_size)
  59. {
  60. uint16_t crc = 0;
  61. uint32_t addr = 0;
  62. uint8_t req_bank = 0;
  63. sram_bulk_read_start(bottom_addr);
  64. debug_P(DEBUG_CRC,
  65. PSTR
  66. ("crc_check_bulk_memory: bottom_addr=0x%08lx top_addr=0x%08lx\n"),
  67. bottom_addr, top_addr);
  68. for (addr = bottom_addr; addr < top_addr; addr++) {
  69. if (addr && ((addr % bank_size) == 0)) {
  70. debug_P(DEBUG_CRC,
  71. PSTR
  72. ("crc_check_bulk_memory: bank=0x%02x addr=0x%08lx crc=0x%04x\n"),
  73. req_bank, addr, crc);
  74. req_bank++;
  75. crc = 0;
  76. }
  77. crc = crc_xmodem_update(crc, sram_bulk_read());
  78. sram_bulk_read_next();
  79. }
  80. if (addr % 0x8000 == 0)
  81. debug_P(DEBUG_CRC,
  82. PSTR
  83. ("crc_check_bulk_memory: bank=0x%02x addr=0x%08lx crc=0x%04x\n"),
  84. req_bank, addr, crc);
  85. sram_bulk_read_end();
  86. return crc;
  87. }
  88. uint16_t crc_check_memory_range(uint32_t start_addr, uint32_t size,
  89. uint8_t * buffer)
  90. {
  91. uint16_t crc = 0;
  92. uint32_t addr;
  93. for (addr = start_addr; addr < start_addr + size;
  94. addr += TRANSFER_BUFFER_SIZE) {
  95. sram_bulk_copy_into_buffer(addr, buffer, TRANSFER_BUFFER_SIZE);
  96. crc = do_crc_update(crc, buffer, TRANSFER_BUFFER_SIZE);
  97. }
  98. return crc;
  99. }