sram.h 7.1 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. * ___.
  11. * __ __ _____\_ |__
  12. * | | \/ ___/| __ \
  13. * | | /\___ \ | \_\ \
  14. * |____//____ >|___ /
  15. * \/ \/
  16. *
  17. * www.optixx.org
  18. *
  19. *
  20. * Version: 1.0
  21. * Created: 07/21/2009 03:32:16 PM
  22. * Author: david@optixx.org
  23. *
  24. * =====================================================================================
  25. */
  26. #ifndef __SRAM_H__
  27. #define __SRAM_H__
  28. #include <stdlib.h>
  29. #include <stdint.h>
  30. #include <avr/io.h>
  31. /* ---------------------------- PORT A ---------------------------- */
  32. #define AVR_DATA_PORT PORTA
  33. #define AVR_DATA_DIR DDRA
  34. #define AVR_DATA_PIN PINA
  35. #define avr_data_in() ((AVR_DATA_DIR = 0x00),\
  36. (AVR_DATA_PORT = 0x00))
  37. #define avr_data_out() (AVR_DATA_DIR = 0xff)
  38. #define LED_PORT PORTC
  39. #define LED_DIR DDRC
  40. #define LED_PIN PC7
  41. #define led_on() ((LED_PORT &=~ (1 << LED_PIN)),\
  42. (LED_DIR &=~ (1 << LED_PIN)))
  43. #define led_off() ((LED_PORT &=~ (1 << LED_PIN)),\
  44. (LED_DIR |= (1 << LED_PIN)))
  45. /* ---------------------------- PORT B ---------------------------- */
  46. #define AVR_PORT PORTB
  47. #define AVR_DIR DDRB
  48. #define AVR_RD_PORT PORTB
  49. #define AVR_RD_DIR DDRB
  50. #define AVR_RD_PIN PB2
  51. #define avr_rd_hi() (AVR_RD_PORT |= (1 << AVR_RD_PIN))
  52. #define avr_rd_lo() (AVR_RD_PORT &= ~(1 << AVR_RD_PIN))
  53. #define AVR_WR_PORT PORTB
  54. #define AVR_WR_DIR DDRB
  55. #define AVR_WR_PIN PB1
  56. #define avr_wr_hi() (AVR_WR_PORT |= (1 << AVR_WR_PIN))
  57. #define avr_wr_lo() (AVR_WR_PORT &= ~(1 << AVR_WR_PIN))
  58. #define AVR_CS_PORT PORTB
  59. #define AVR_CS_DIR DDRB
  60. #define AVR_CS_PIN PB0
  61. #define avr_cs_hi() (AVR_CS_PORT |= (1 << AVR_CS_PIN))
  62. #define avr_cs_lo() (AVR_CS_PORT &= ~(1 << AVR_CS_PIN))
  63. #define SNES_IRQ_PORT PORTB
  64. #define SNES_IRQ_DIR DDRB
  65. #define SNES_IRQ_PIN PB3
  66. #define snes_irq_on() (SNES_IRQ_DIR |= (1 << SNES_IRQ_PIN))
  67. #define snes_irq_hi() (SNES_IRQ_PORT |= (1 << SNES_IRQ_PIN))
  68. #define snes_irq_off() (SNES_IRQ_DIR &= ~(1 << SNES_IRQ_PIN))
  69. #define snes_irq_lo() (SNES_IRQ_PORT &= ~(1 << SNES_IRQ_PIN))
  70. #define SNES_RESET_PORT PORTB
  71. #define SNES_RESET_DIR DDRB
  72. #define SNES_RESET_PIN PB4
  73. #define snes_reset_on() (SNES_RESET_DIR |= (1 << SNES_RESET_PIN))
  74. #define snes_reset_hi() (SNES_RESET_PORT |= (1 << SNES_RESET_PIN))
  75. #define snes_reset_off() (SNES_RESET_DIR &= ~(1 << SNES_RESET_PIN))
  76. #define snes_reset_lo() (SNES_RESET_PORT &= ~(1 << SNES_RESET_PIN))
  77. /* ---------------------------- PORT C ---------------------------- */
  78. #define AVR_ADDR_PORT PORTC
  79. #define AVR_ADDR_DIR DDRC
  80. #define AVR_ADDR_LATCH_PORT PORTC
  81. #define AVR_ADDR_LATCH_DIR DDRC
  82. #define AVR_ADDR_LATCH_PIN PC6
  83. #define avr_addr_latch_hi() (AVR_ADDR_LATCH_PORT |= (1 << AVR_ADDR_LATCH_PIN)))
  84. #define avr_addr_latch_lo() (AVR_ADDR_LATCH_PORT &= ~(1 << AVR_ADDR_LATCH_PIN)))
  85. #define AVR_ADDR_SCK_PORT PORTC
  86. #define AVR_ADDR_SCK_DIR DDRC
  87. #define AVR_ADDR_SCK_PIN PC5
  88. #define avr_addr_sck_hi() (AVR_ADDR_SCK_PORT |= (1 << AVR_ADDR_SCK_PIN)))
  89. #define avr_addr_sck_lo() (AVR_ADDR_SCK_PORT &= ~(1 << AVR_ADDR_SCK_PIN)))
  90. #define AVR_ADDR_SER_PORT PORTC
  91. #define AVR_ADDR_SER_DIR DDRC
  92. #define AVR_ADDR_SER_PIN PC4
  93. #define avr_addr_ser_hi() (AVR_ADDR_SER_PORT |= (1 << AVR_ADDR_SER_PIN)))
  94. #define avr_addr_ser_lo() (AVR_ADDR_SER_PORT &= ~(1 << AVR_ADDR_SER_PIN)))
  95. #define AVR_ADDR_LOAD_PORT PORTC
  96. #define AVR_ADDR_LOAD_DIR DDRC
  97. #define AVR_ADDR_LOAD_PIN PC2
  98. #define counter_load() ((AVR_ADDR_LOAD_PORT &= ~(1 << AVR_ADDR_LOAD_PIN)),\
  99. (AVR_ADDR_LOAD_PORT |= (1 << AVR_ADDR_LOAD_PIN)))
  100. #define AVR_ADDR_DOWN_PORT PORTC
  101. #define AVR_ADDR_DOWN_DIR DDRC
  102. #define AVR_ADDR_DOWN_PIN PC1
  103. #define counter_down() ((AVR_ADDR_DOWN_PORT &= ~(1 << AVR_ADDR_DOWN_PIN)),\
  104. (AVR_ADDR_DOWN_PORT |= (1 << AVR_ADDR_DOWN_PIN)))
  105. #define AVR_ADDR_UP_PORT PORTC
  106. #define AVR_ADDR_UP_DIR DDRC
  107. #define AVR_ADDR_UP_PIN PC0
  108. #define counter_up() ((AVR_ADDR_UP_PORT &= ~(1 << AVR_ADDR_UP_PIN)),\
  109. (AVR_ADDR_UP_PORT |= (1 << AVR_ADDR_UP_PIN)))
  110. #define SNES_WR_PORT PORTC
  111. #define SNES_WR_DIR DDRC
  112. #define SNES_WR_PIN PC3
  113. /* ---------------------------- PORT D ---------------------------- */
  114. #define AVR_SNES_PORT PORTD
  115. #define AVR_SNES_DIR DDRD
  116. #define AVR_SNES_SW_PORT PORTD
  117. #define AVR_SNES_SW_DIR DDRD
  118. #define AVR_SNES_SW_PIN PD5
  119. #define avr_bus_active() ((AVR_SNES_SW_PORT &= ~(1 << AVR_SNES_SW_PIN)),\
  120. (HI_LOROM_SW_PORT |= (1 << HI_LOROM_SW_PIN)),\
  121. (AVR_CS_DIR |= (1 << AVR_CS_PIN)))
  122. #define snes_bus_active() ((AVR_SNES_SW_PORT |= (1 << AVR_SNES_SW_PIN)),\
  123. (AVR_CS_DIR &= ~(1 << AVR_CS_PIN)))
  124. #define HI_LOROM_SW_PORT PORTD
  125. #define HI_LOROM_SW_DIR DDRD
  126. #define HI_LOROM_SW_PIN PD6
  127. #define snes_hirom() (HI_LOROM_SW_PORT &= ~(1 << HI_LOROM_SW_PIN))
  128. #define snes_lorom() (HI_LOROM_SW_PORT |= (1 << HI_LOROM_SW_PIN))
  129. #define SNES_WR_EN_PORT PORTD
  130. #define SNES_WR_EN_DIR DDRD
  131. #define SNES_WR_EN_PIN PD7
  132. #define snes_wr_disable() (SNES_WR_EN_PORT &= ~(1 << SNES_WR_EN_PIN))
  133. #define snes_wr_enable() (SNES_WR_EN_PORT |= (1 << SNES_WR_EN_PIN))
  134. void system_init(void);
  135. void sreg_set(uint32_t addr);
  136. uint8_t sram_read(uint32_t addr);
  137. void sram_write(uint32_t addr, uint8_t data);
  138. void sram_set(uint32_t addr, uint32_t len, uint8_t value);
  139. void sram_copy(uint32_t addr,uint8_t *src, uint32_t len);
  140. void sram_read_buffer(uint32_t addr,uint8_t *dst, uint32_t len);
  141. void sram_bulk_read_start(uint32_t addr);
  142. inline void sram_bulk_read_next(void);
  143. inline void sram_bulk_read_end(void);
  144. uint8_t sram_bulk_read(void);
  145. void sram_bulk_write_start(uint32_t addr);
  146. inline void sram_bulk_write_next(void);
  147. inline void sram_bulk_write_end(void);
  148. void sram_bulk_write(uint8_t data);
  149. void sram_bulk_copy(uint32_t addr, uint8_t * src, uint32_t len);
  150. void sram_bulk_read_buffer(uint32_t addr, uint8_t * dst, uint32_t len);
  151. void sram_bulk_set(uint32_t addr, uint32_t len,uint8_t value);
  152. #endif