sram.c 8.6 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. * ___.
  11. * __ __ _____\_ |__
  12. * | | \/ ___/| __ \
  13. * | | /\___ \ | \_\ \
  14. * |____//____ >|___ /
  15. * \/ \/
  16. *
  17. * www.optixx.org
  18. *
  19. *
  20. * Version: 1.0
  21. * Created: 07/21/2009 03:32:16 PM
  22. * Author: david@optixx.org
  23. *
  24. * =====================================================================================
  25. */
  26. #include <stdlib.h>
  27. #include <stdint.h>
  28. #include <avr/io.h>
  29. #include <util/delay.h> /* for _delay_ms() */
  30. #include "config.h"
  31. #include "sram.h"
  32. #include "uart.h"
  33. #include "debug.h"
  34. void system_init(void)
  35. {
  36. /*-------------------------------------------------*/
  37. DDRA = 0x00;
  38. PORTA = 0x00;
  39. /*-------------------------------------------------*/
  40. DDRC |= ( (1 << AVR_ADDR_LATCH_PIN)
  41. | (1 << AVR_ADDR_SCK_PIN)
  42. | (1 << AVR_ADDR_SER_PIN)
  43. | (1 << AVR_ADDR_LOAD_PIN)
  44. | (1 << AVR_ADDR_DOWN_PIN)
  45. | (1 << AVR_ADDR_UP_PIN));
  46. DDRC &= ~ (1 << SNES_WR_PIN);
  47. PORTC &= ~((1 << AVR_ADDR_LATCH_PIN)
  48. | (1 << AVR_ADDR_SCK_PIN)
  49. | (1 << SNES_WR_PIN));
  50. PORTC |= ( (1 << AVR_ADDR_DOWN_PIN)
  51. | (1 << AVR_ADDR_UP_PIN)
  52. | (1 << AVR_ADDR_LOAD_PIN));
  53. //| (1 << SNES_WR_PIN));
  54. /*-------------------------------------------------*/
  55. DDRB |= ( (1 << AVR_RD_PIN)
  56. | (1 << AVR_WR_PIN)
  57. | (1 << AVR_CS_PIN)
  58. | (1 << SNES_IRQ_PIN));
  59. PORTB |= ( (1 << AVR_RD_PIN)
  60. | (1 << AVR_WR_PIN)
  61. | (1 << AVR_CS_PIN)
  62. | (1 << SNES_IRQ_PIN));
  63. /*-------------------------------------------------*/
  64. DDRD |= ( (1 << AVR_SNES_SW_PIN)
  65. | (1 << HI_LOROM_SW_PIN)
  66. | (1 << SNES_WR_EN_PIN));
  67. PORTD |= (1 << HI_LOROM_SW_PIN);
  68. PORTD &= ~((1 << AVR_SNES_SW_PIN)
  69. | (1 << SNES_WR_EN_PIN));
  70. /*-------------------------------------------------*/
  71. }
  72. void sreg_set(uint32_t addr)
  73. {
  74. uint8_t i = 24;
  75. debug(DEBUG_SREG,"sreg_set: addr=0x%08lx",addr);
  76. while(i--) {
  77. if ((addr & ( 1L << i))){
  78. debug(DEBUG_SREG,"1");
  79. AVR_ADDR_SER_PORT |= ( 1 << AVR_ADDR_SER_PIN);
  80. } else {
  81. AVR_ADDR_SER_PORT &= ~( 1 << AVR_ADDR_SER_PIN);
  82. debug(DEBUG_SREG,"0");
  83. }
  84. AVR_ADDR_SCK_PORT |= (1 << AVR_ADDR_SCK_PIN);
  85. AVR_ADDR_SCK_PORT &= ~(1 << AVR_ADDR_SCK_PIN);
  86. }
  87. debug(DEBUG_SREG,"\n");
  88. AVR_ADDR_LATCH_PORT |= (1 << AVR_ADDR_LATCH_PIN);
  89. AVR_ADDR_LATCH_PORT &= ~(1 << AVR_ADDR_LATCH_PIN);
  90. counter_load();
  91. }
  92. void sram_bulk_read_start(uint32_t addr)
  93. {
  94. debug(DEBUG_SRAM,"sram_bulk_read_start: addr=0x%08lx\n\r", addr);
  95. avr_data_in();
  96. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  97. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  98. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  99. sreg_set(addr);
  100. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  101. asm volatile ("nop");
  102. asm volatile ("nop");
  103. asm volatile ("nop");
  104. asm volatile ("nop");
  105. asm volatile ("nop");
  106. asm volatile ("nop");
  107. }
  108. inline void sram_bulk_read_next(void)
  109. {
  110. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  111. counter_up();
  112. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  113. asm volatile ("nop");
  114. asm volatile ("nop");
  115. asm volatile ("nop");
  116. asm volatile ("nop");
  117. asm volatile ("nop");
  118. asm volatile ("nop");
  119. }
  120. inline uint8_t sram_bulk_read(void)
  121. {
  122. return AVR_DATA_PIN;
  123. }
  124. void sram_bulk_read_end(void)
  125. {
  126. debug(DEBUG_SRAM,"sram_bulk_read_end:\n");
  127. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  128. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  129. avr_data_in();
  130. }
  131. uint8_t sram_read(uint32_t addr)
  132. {
  133. uint8_t byte;
  134. debug(DEBUG_SRAM_RAW,"sram_read: addr=0x%08lx\n\r", addr);
  135. avr_data_in();
  136. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  137. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  138. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  139. sreg_set(addr);
  140. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  141. asm volatile ("nop");
  142. asm volatile ("nop");
  143. asm volatile ("nop");
  144. asm volatile ("nop");
  145. asm volatile ("nop");
  146. asm volatile ("nop");
  147. byte = AVR_DATA_PIN;
  148. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  149. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  150. avr_data_in();
  151. return byte;
  152. }
  153. void sram_bulk_write_start(uint32_t addr)
  154. {
  155. debug(DEBUG_SRAM,"sram_bulk_write_start: addr=0x%08lx\n\r", addr);
  156. avr_data_out();
  157. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  158. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  159. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  160. sreg_set(addr);
  161. AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
  162. }
  163. inline void sram_bulk_write_next(void)
  164. {
  165. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  166. counter_up();
  167. AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
  168. }
  169. inline void sram_bulk_write( uint8_t data)
  170. {
  171. AVR_DATA_PORT = data;
  172. }
  173. void sram_bulk_write_end(void)
  174. {
  175. debug(DEBUG_SRAM,"sram_bulk_write_end:");
  176. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  177. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  178. avr_data_in();
  179. }
  180. void sram_write(uint32_t addr, uint8_t data)
  181. {
  182. debug(DEBUG_SRAM_RAW,"sram_write: addr=0x%08lx data=%x\n\r", addr, data);
  183. avr_data_out();
  184. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  185. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  186. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  187. sreg_set(addr);
  188. AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
  189. AVR_DATA_PORT = data;
  190. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  191. asm volatile ("nop");
  192. asm volatile ("nop");
  193. asm volatile ("nop");
  194. asm volatile ("nop");
  195. asm volatile ("nop");
  196. asm volatile ("nop");
  197. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  198. avr_data_in();
  199. }
  200. void sram_bulk_copy(uint32_t addr, uint8_t * src, uint32_t len)
  201. {
  202. uint32_t i;
  203. uint8_t *ptr = src;
  204. debug(DEBUG_SRAM,"sram_copy: addr=0x%08lx src=0x%p len=%li\n\r", addr,src,len);
  205. sram_bulk_write_start(addr);
  206. for (i = addr; i < (addr + len); i++){
  207. sram_bulk_write(*ptr++);
  208. sram_bulk_write_next();
  209. }
  210. sram_bulk_write_end();
  211. }
  212. void sram_bulk_read_buffer(uint32_t addr, uint8_t * dst, uint32_t len)
  213. {
  214. uint32_t i;
  215. uint8_t *ptr = dst;
  216. debug(DEBUG_SRAM,"sram_bulk_read_buffer: addr=0x%08lx dst=0x%p len=%li\n\r", addr,dst,len);
  217. sram_bulk_read_start(addr);
  218. for (i = addr; i < (addr + len); i++) {
  219. *ptr = sram_bulk_read();
  220. sram_bulk_read_next();
  221. ptr++;
  222. }
  223. sram_bulk_read_end();
  224. }
  225. void sram_bulk_set(uint32_t addr, uint32_t len,uint8_t value){
  226. uint32_t i;
  227. debug(DEBUG_SRAM,"sram_bulk_set: addr=0x%08lx len=%li\n\r", addr,len);
  228. sram_bulk_write_start(addr);
  229. for (i = addr; i < (addr + len); i++) {
  230. if (0 == i % 0xfff)
  231. debug(DEBUG_SRAM,"sram_bulk_set: addr=0x%08lx\n\r", i);
  232. sram_bulk_write(value);
  233. sram_bulk_write_next();
  234. }
  235. sram_bulk_write_end();
  236. }
  237. void sram_setr(uint32_t addr, uint32_t len,uint8_t value)
  238. {
  239. uint32_t i;
  240. debug(DEBUG_SRAM,"sram_clear: addr=0x%08lx len=%li\n\r", addr,len);
  241. for (i = addr; i < (addr + len); i++) {
  242. if (0 == i % 0xfff)
  243. debug(DEBUG_SRAM,"sram_clear: addr=0x%08lx\n\r", i);
  244. sram_write(i, value);
  245. }
  246. }
  247. void sram_copy(uint32_t addr, uint8_t * src, uint32_t len)
  248. {
  249. uint32_t i;
  250. uint8_t *ptr = src;
  251. debug(DEBUG_SRAM,"sram_copy: addr=0x%08lx src=0x%p len=%li\n\r", addr,src,len);
  252. for (i = addr; i < (addr + len); i++)
  253. sram_write(i, *ptr++);
  254. }
  255. void sram_read_buffer(uint32_t addr, uint8_t * dst, uint32_t len)
  256. {
  257. uint32_t i;
  258. uint8_t *ptr = dst;
  259. debug(DEBUG_SRAM,"sram_read_buffer: addr=0x%08lx dst=0x%p len=%li\n\r", addr,dst,len);
  260. for (i = addr; i < (addr + len); i++) {
  261. *ptr = sram_read(i);
  262. ptr++;
  263. }
  264. }
  265. uint8_t sram_check(uint8_t * buffer, uint32_t len)
  266. {
  267. uint16_t cnt;
  268. debug(DEBUG_SRAM,"sram_check: len=%li\n\r",len);
  269. for (cnt = 0; cnt < len; cnt++)
  270. if (buffer[cnt])
  271. return 1;
  272. return 0;
  273. }