main.c 15 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. * ___.
  11. * __ __ _____\_ |__
  12. * | | \/ ___/| __ \
  13. * | | /\___ \ | \_\ \
  14. * |____//____ >|___ /
  15. * \/ \/
  16. *
  17. * www.optixx.org
  18. *
  19. *
  20. * Version: 1.0
  21. * Created: 07/21/2009 03:32:16 PM
  22. * Author: david@optixx.org
  23. *
  24. * =====================================================================================
  25. */
  26. #include <avr/io.h>
  27. #include <avr/interrupt.h> /* for sei() */
  28. #include <util/delay.h> /* for _delay_ms() */
  29. #include <stdlib.h>
  30. #include <avr/pgmspace.h> /* required by usbdrv.h */
  31. #include <avr/eeprom.h>
  32. #include "usbdrv.h"
  33. #include "oddebug.h" /* This is also an example for using debug
  34. * macros */
  35. #include "config.h"
  36. #include "requests.h" /* The custom request numbers we use */
  37. #include "uart.h"
  38. #include "sram.h"
  39. #include "debug.h"
  40. #include "dump.h"
  41. #include "crc.h"
  42. #include "usb_bulk.h"
  43. #include "timer.h"
  44. #include "watchdog.h"
  45. #include "huffman-decode.h"
  46. #include "rle.h"
  47. extern const char _rom[] PROGMEM;
  48. extern FILE uart_stdout;
  49. uint8_t debug_level = ( DEBUG | DEBUG_USB | DEBUG_CRC );
  50. uint8_t read_buffer[TRANSFER_BUFFER_SIZE];
  51. uint32_t req_addr = 0;
  52. uint32_t req_addr_end = 0;
  53. uint32_t req_size;
  54. uint8_t req_bank;
  55. uint32_t req_bank_size;
  56. uint16_t req_bank_cnt;
  57. uint8_t req_state = REQ_STATUS_IDLE;
  58. uint8_t rx_remaining = 0;
  59. uint8_t tx_remaining = 0;
  60. uint16_t sync_errors = 0;
  61. uint8_t tx_buffer[32];
  62. uint8_t data_buffer[4];
  63. uint32_t addr;
  64. uint16_t crc = 0;
  65. usbMsgLen_t usbFunctionSetup(uchar data[8])
  66. {
  67. usbRequest_t *rq = (void *) data;
  68. uint8_t ret_len = 0;
  69. /*
  70. * -------------------------------------------------------------------------
  71. */
  72. if (rq->bRequest == USB_UPLOAD_INIT) {
  73. if (req_state != REQ_STATUS_IDLE){
  74. debug(DEBUG_USB,"USB_UPLOAD_INIT: ERROR state is not REQ_STATUS_IDLE\n");
  75. return 0;
  76. }
  77. req_bank = 0;
  78. rx_remaining = 0;
  79. req_bank_size = (uint32_t)1 << rq->wValue.word;
  80. sync_errors = 0;
  81. crc = 0;
  82. debug(DEBUG_USB,"USB_UPLOAD_INIT: bank_size=0x%08lx\n", req_bank_size);
  83. /*
  84. * -------------------------------------------------------------------------
  85. */
  86. } else if (rq->bRequest == USB_UPLOAD_ADDR) {
  87. req_state = REQ_STATUS_UPLOAD;
  88. req_addr = rq->wValue.word;
  89. req_addr = req_addr << 16;
  90. req_addr = req_addr | rq->wIndex.word;
  91. if (rx_remaining) {
  92. sync_errors++;
  93. debug
  94. (DEBUG_USB,"USB_UPLOAD_ADDR: Out of sync addr=0x%lx remain=%i packet=%i sync_error=%i\n",
  95. req_addr, rx_remaining, rq->wLength.word, sync_errors);
  96. ret_len = 0;
  97. }
  98. rx_remaining = rq->wLength.word;
  99. ret_len = USB_MAX_TRANS;
  100. if (req_addr && (req_addr % 0x1000) == 0) {
  101. debug(DEBUG_USB,"USB_UPLOAD_ADDR: bank=0x%02x addr=0x%08lx crc=%04x\n",
  102. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  103. }
  104. if (req_addr && req_addr % req_bank_size == 0) {
  105. debug(DEBUG_USB,"USB_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx\n",
  106. req_bank, req_addr);
  107. req_bank++;
  108. }
  109. ret_len = USB_MAX_TRANS;
  110. /*
  111. * -------------------------------------------------------------------------
  112. */
  113. } else if (rq->bRequest == USB_DOWNLOAD_INIT) {
  114. debug(DEBUG_USB,"USB_DOWNLOAD_INIT\n");
  115. /*
  116. * -------------------------------------------------------------------------
  117. */
  118. } else if (rq->bRequest == USB_DOWNLOAD_ADDR) {
  119. debug(DEBUG_USB,"USB_DOWNLOAD_ADDR\n");
  120. /*
  121. * -------------------------------------------------------------------------
  122. */
  123. } else if (rq->bRequest == USB_BULK_UPLOAD_INIT) {
  124. req_bank = 0;
  125. rx_remaining = 0;
  126. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: %i %i\n",rq->wValue.word, rq->wIndex.word);
  127. req_bank_size = (uint32_t)(1L << rq->wValue.word);
  128. req_bank_cnt = rq->wIndex.word;
  129. req_addr_end = (uint32_t)req_bank_size * req_bank_cnt;
  130. sync_errors = 0;
  131. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: bank_size=0x%08lx bank_cnt=0x%x end_addr=0x%08lx\n",
  132. req_bank_size, req_bank_cnt, req_addr_end);
  133. if (req_addr == 0x000000){
  134. timer_start();
  135. }
  136. /*
  137. * -------------------------------------------------------------------------
  138. */
  139. } else if (rq->bRequest == USB_BULK_UPLOAD_ADDR) {
  140. req_state = REQ_STATUS_BULK_UPLOAD;
  141. req_addr = rq->wValue.word;
  142. req_addr = req_addr << 16;
  143. req_addr = req_addr | rq->wIndex.word;
  144. sram_bulk_write_start(req_addr);
  145. rx_remaining = rq->wLength.word;
  146. if (req_addr && req_addr % req_bank_size == 0) {
  147. debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  148. req_bank, req_addr,timer_stop());
  149. req_bank++;
  150. timer_start();
  151. }
  152. ret_len = USB_MAX_TRANS;
  153. /*
  154. * -------------------------------------------------------------------------
  155. */
  156. } else if (rq->bRequest == USB_BULK_UPLOAD_NEXT) {
  157. req_state = REQ_STATUS_BULK_UPLOAD;
  158. req_addr = rq->wValue.word;
  159. req_addr = req_addr << 16;
  160. req_addr = req_addr | rq->wIndex.word;
  161. rx_remaining = rq->wLength.word;
  162. #if 0
  163. if (req_addr && (req_addr % 0x1000) == 0) {
  164. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: bank=0x%02x addr=0x%08lx crc=%04x\n",
  165. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  166. }
  167. sram_bulk_write_start(req_addr);
  168. #endif
  169. if (req_addr && ( req_addr % req_bank_size) == 0) {
  170. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  171. req_bank, req_addr,timer_stop());
  172. req_bank++;
  173. timer_start();
  174. }
  175. ret_len = USB_MAX_TRANS;
  176. /*
  177. * -------------------------------------------------------------------------
  178. */
  179. } else if (rq->bRequest == USB_BULK_UPLOAD_END) {
  180. if (req_state != REQ_STATUS_BULK_UPLOAD){
  181. debug(DEBUG_USB,"USB_BULK_UPLOAD_END: ERROR state is not REQ_STATUS_BULK_UPLOAD\n");
  182. return 0;
  183. }
  184. debug(DEBUG_USB,"USB_BULK_UPLOAD_END:\n");
  185. req_state = REQ_STATUS_IDLE;
  186. sram_bulk_write_end();
  187. ret_len = 0;
  188. /*
  189. * -------------------------------------------------------------------------
  190. */
  191. } else if (rq->bRequest == USB_CRC) {
  192. req_addr = rq->wValue.word;
  193. req_addr = req_addr << 16;
  194. req_addr = req_addr | rq->wIndex.word;
  195. debug(DEBUG_USB,"USB_CRC: addr=0x%08lx \n", req_addr);
  196. crc_check_bulk_memory(0x000000, req_addr, req_bank_size);
  197. ret_len = 0;
  198. /*
  199. * -------------------------------------------------------------------------
  200. */
  201. } else if (rq->bRequest == USB_MODE_SNES) {
  202. req_state = REQ_STATUS_SNES;
  203. debug(DEBUG_USB,"USB_MODE_SNES:\n");
  204. ret_len = 0;
  205. /*
  206. * -------------------------------------------------------------------------
  207. */
  208. } else if (rq->bRequest == USB_MODE_AVR) {
  209. req_state = REQ_STATUS_AVR;
  210. debug(DEBUG_USB,"USB_MODE_AVR:\n");
  211. ret_len = 0;
  212. /*
  213. * -------------------------------------------------------------------------
  214. */
  215. } else if (rq->bRequest == USB_AVR_RESET) {
  216. debug(DEBUG_USB,"USB_AVR_RESET:\n");
  217. soft_reset();
  218. ret_len = 0;
  219. /*
  220. * -------------------------------------------------------------------------
  221. */
  222. } else if (rq->bRequest == USB_CRC_ADDR) {
  223. req_state = REQ_STATUS_CRC;
  224. req_addr = rq->wValue.word;
  225. req_addr = req_addr << 16;
  226. req_addr = req_addr | rq->wIndex.word;
  227. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%i\n", req_addr,
  228. rq->wLength.word);
  229. req_size = rq->wLength.word;
  230. req_size = req_size << 2;
  231. tx_remaining = 2;
  232. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%li\n", req_addr, req_size);
  233. crc = crc_check_memory_range(req_addr, req_size, read_buffer);
  234. tx_buffer[0] = crc & 0xff;
  235. tx_buffer[1] = (crc >> 8) & 0xff;
  236. ret_len = 2;
  237. req_state = REQ_STATUS_IDLE;
  238. }
  239. usbMsgPtr = data_buffer;
  240. return ret_len; /* default for not implemented requests: return
  241. * no data back to host */
  242. }
  243. /*
  244. * -------------------------------------------------------------------------
  245. */
  246. void test_read_write(){
  247. uint8_t i;
  248. uint32_t addr;
  249. avr_bus_active();
  250. addr = 0x000000;
  251. i = 1;
  252. while (addr++ <= 0x0000ff){
  253. sram_write(addr,i++);
  254. }
  255. addr = 0x000000;
  256. while (addr++ <= 0x0000ff){
  257. printf("read addr=0x%08lx %x\n",addr,sram_read(addr));
  258. }
  259. }
  260. void test_bulk_read_write(){
  261. uint8_t i;
  262. uint32_t addr;
  263. avr_bus_active();
  264. addr = 0x000000;
  265. i = 0;
  266. sram_bulk_write_start(addr);
  267. while (addr++ <= 0x8000){
  268. sram_bulk_write(i++);
  269. sram_bulk_write_next();
  270. }
  271. sram_bulk_write_end();
  272. addr = 0x000000;
  273. sram_bulk_read_start(addr);
  274. while (addr <= 0x8000){
  275. printf("addr=0x%08lx %x\n",addr,sram_bulk_read());
  276. sram_bulk_read_next();
  277. addr++;
  278. }
  279. sram_bulk_read_end();
  280. }
  281. void test_non_zero_memory(uint32_t bottom_addr,uint32_t top_addr)
  282. {
  283. uint32_t addr = 0;
  284. uint8_t c;
  285. sram_bulk_read_start(bottom_addr);
  286. for (addr = bottom_addr; addr < top_addr; addr++) {
  287. c = sram_bulk_read();
  288. if (c!=0xff)
  289. printf("addr=0x%08lx c=0x%x\n",addr,c);
  290. sram_bulk_read_next();
  291. }
  292. sram_bulk_read_end();
  293. }
  294. void test_crc(){
  295. printf("test_crc: clear\n");
  296. avr_bus_active();
  297. sram_bulk_set(0x000000,0x10000,0xff);
  298. printf("test_crc: crc\n");
  299. crc_check_bulk_memory(0x000000,0x10000,0x8000);
  300. printf("test_crc: check\n");
  301. test_non_zero_memory(0x000000,0x10000);
  302. }
  303. uint16_t read_byte_pgm(uint16_t addr){
  304. return pgm_read_byte((PGM_VOID_P)addr);
  305. }
  306. uint16_t read_byte_ee(uint16_t addr){
  307. return eeprom_read_byte((uint8_t*)addr);
  308. }
  309. void decompress(PGM_VOID_P addr, uint16_t(*fp)(uint16_t)){
  310. uint16_t c;
  311. uint32_t i = 0;
  312. huffman_dec_ctx_t ctx;
  313. huffman_dec_init(&ctx, fp);
  314. huffman_dec_set_addr(&ctx, (uint16_t)addr);
  315. while(1){
  316. i++;
  317. c=huffman_dec_byte(&ctx);
  318. if (i%1024==0)
  319. printf(".");
  320. if(c>0xff){
  321. return;
  322. }
  323. c&=0xff;
  324. sram_bulk_write(c);
  325. }
  326. }
  327. void decompress_huffman(void){
  328. printf("Decompress Rom %p to 0x000000\n",(void*)_rom);
  329. sram_bulk_write_start(0x000000);
  330. decompress(&_rom,read_byte_pgm);
  331. sram_bulk_write_end();
  332. printf("Done\n");
  333. }
  334. void decompress_rle(void){
  335. rle_decode(&_rom,30180,0x000000);
  336. printf("Done\n");
  337. }
  338. void boot_startup_rom(){
  339. uint8_t i = 0;
  340. printf("Activate AVR bus\n");
  341. avr_bus_active();
  342. printf("IRQ off\n");
  343. snes_irq_lo();
  344. snes_irq_off();
  345. snes_lorom();
  346. printf("Set Snes lowrom \n");
  347. /*
  348. printf("Set Snes hirom\n");
  349. snes_hirom();
  350. printf("Disable snes WR\n");
  351. snes_wr_disable();
  352. printf("IRQ off\n");
  353. snes_irq_lo();
  354. snes_irq_off();
  355. */
  356. decompress_rle();
  357. dump_memory(0x10000 - 0x100, 0x10000);
  358. //crc_check_bulk_memory(0x00000, 0x10000, 0x8000);
  359. snes_reset_hi();
  360. snes_reset_off();
  361. snes_irq_lo();
  362. snes_irq_off();
  363. printf("IRQ off\n");
  364. snes_hirom();
  365. snes_wr_disable();
  366. printf("Disable snes WR\n");
  367. snes_bus_active();
  368. printf("Activate Snes bus\n");
  369. _delay_ms(100);
  370. printf("Reset Snes\n");
  371. send_reset();
  372. i = 20;
  373. printf("Wait");
  374. while (--i){
  375. _delay_ms(500);
  376. printf(".");
  377. }
  378. printf("\n");
  379. }
  380. void send_reset(){
  381. printf("Reset Snes\n");
  382. snes_reset_on();
  383. snes_reset_lo();
  384. _delay_ms(2);
  385. snes_reset_hi();
  386. snes_reset_off();
  387. }
  388. void send_irq(){
  389. snes_irq_on();
  390. snes_irq_lo();
  391. _delay_us(20);
  392. snes_irq_hi();
  393. snes_irq_off();
  394. }
  395. void set_rom_mode(){
  396. if (req_bank_size == 0x8000){
  397. snes_lorom();
  398. printf("Set Snes lowrom \n");
  399. } else {
  400. snes_hirom();
  401. printf("Set Snes hirom \n");
  402. }
  403. }
  404. void usb_connect(){
  405. uint8_t i = 0;
  406. printf("USB init\n");
  407. usbDeviceDisconnect(); /* enforce re-enumeration, do this while */
  408. cli();
  409. printf("USB disconnect\n");
  410. i = 10;
  411. while (--i) { /* fake USB disconnect for > 250 ms */
  412. led_on();
  413. _delay_ms(35);
  414. led_off();
  415. _delay_ms(65);
  416. }
  417. led_on();
  418. usbDeviceConnect();
  419. printf("USB connect\n");
  420. }
  421. int main(void)
  422. {
  423. uint8_t i;
  424. uint16_t irq_count = 0;
  425. uart_init();
  426. stdout = &uart_stdout;
  427. printf("Sytem start\n");
  428. system_init();
  429. #if 0
  430. test_read_write();
  431. test_bulk_read_write();
  432. test_crc();
  433. while(1);
  434. #endif
  435. printf("Boot startup rom\n");
  436. boot_startup_rom();
  437. usbInit();
  438. usb_connect();
  439. while (1){
  440. avr_bus_active();
  441. printf("Activate AVR bus\n");
  442. printf("IRQ off\n");
  443. snes_irq_lo();
  444. snes_irq_off();
  445. printf("Set Snes lowrom\n");
  446. snes_lorom();
  447. printf("Disable snes WR\n");
  448. snes_wr_disable();
  449. sei();
  450. printf("USB poll\n");
  451. while (req_state != REQ_STATUS_SNES){
  452. usbPoll();
  453. }
  454. printf("USB poll done\n");
  455. snes_reset_hi();
  456. snes_reset_off();
  457. snes_irq_lo();
  458. snes_irq_off();
  459. printf("IRQ off\n");
  460. set_rom_mode();
  461. snes_wr_disable();
  462. printf("Disable snes WR\n");
  463. snes_bus_active();
  464. printf("Activate Snes bus\n");
  465. _delay_ms(100);
  466. printf("Reset Snes\n");
  467. send_reset();
  468. printf("Poll\n");
  469. while (req_state != REQ_STATUS_AVR){
  470. usbPoll();
  471. #if 1
  472. i = 10;
  473. while (--i) { /* fake USB disconnect for > 250 ms */
  474. _delay_ms(100);
  475. }
  476. printf("Send IRQ %i\n",++irq_count);
  477. send_irq();
  478. #endif
  479. #if 0
  480. avr_bus_active();
  481. sram_bulk_read_start(0x003000);
  482. c = sram_bulk_read();
  483. i = 5;
  484. while (--i) {
  485. _delay_ms(500);
  486. printf("Wait to switch to snes mode %i\n", i);
  487. }
  488. if (req_bank_size == 0x8000){
  489. snes_lorom();
  490. printf("Set Snes lowrom \n");
  491. } else {
  492. snes_hirom();
  493. printf("Set Snes hirom \n");
  494. }
  495. snes_wr_disable();
  496. printf("Disable snes WR\n");
  497. snes_bus_active();
  498. printf("Activate Snes bus\n");
  499. printf("Read 0x3000=%c\n",c);
  500. #endif
  501. }
  502. }
  503. return 0;
  504. }