sram.c 8.5 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. *
  11. * www.optixx.org
  12. *
  13. *
  14. * Version: 1.0
  15. * Created: 07/21/2009 03:32:16 PM
  16. * Author: david@optixx.org
  17. *
  18. * =====================================================================================
  19. */
  20. #include <stdlib.h>
  21. #include <stdint.h>
  22. #include <avr/io.h>
  23. #include <util/delay.h> /* for _delay_ms() */
  24. #include "config.h"
  25. #include "sram.h"
  26. #include "uart.h"
  27. #include "debug.h"
  28. #include "info.h"
  29. void system_init(void)
  30. {
  31. /*-------------------------------------------------*/
  32. DDRA = 0x00;
  33. PORTA = 0x00;
  34. /*-------------------------------------------------*/
  35. DDRC |= ( (1 << AVR_ADDR_LATCH_PIN)
  36. | (1 << AVR_ADDR_SCK_PIN)
  37. | (1 << AVR_ADDR_SER_PIN)
  38. | (1 << AVR_ADDR_LOAD_PIN)
  39. | (1 << AVR_ADDR_DOWN_PIN)
  40. | (1 << AVR_ADDR_UP_PIN));
  41. DDRC &= ~ (1 << SNES_WR_PIN);
  42. PORTC &= ~((1 << AVR_ADDR_LATCH_PIN)
  43. | (1 << AVR_ADDR_SCK_PIN)
  44. | (1 << SNES_WR_PIN));
  45. PORTC |= ( (1 << AVR_ADDR_DOWN_PIN)
  46. | (1 << AVR_ADDR_UP_PIN)
  47. | (1 << AVR_ADDR_LOAD_PIN));
  48. //| (1 << SNES_WR_PIN));
  49. /*-------------------------------------------------*/
  50. DDRB |= ( (1 << AVR_RD_PIN)
  51. | (1 << AVR_WR_PIN)
  52. | (1 << AVR_CS_PIN)
  53. | (1 << SNES_IRQ_PIN));
  54. PORTB |= ( (1 << AVR_RD_PIN)
  55. | (1 << AVR_WR_PIN)
  56. | (1 << AVR_CS_PIN)
  57. | (1 << SNES_IRQ_PIN));
  58. /*-------------------------------------------------*/
  59. DDRD |= ( (1 << AVR_SNES_SW_PIN)
  60. | (1 << HI_LOROM_SW_PIN)
  61. | (1 << SNES_WR_EN_PIN));
  62. PORTD |= (1 << HI_LOROM_SW_PIN);
  63. PORTD &= ~((1 << AVR_SNES_SW_PIN)
  64. | (1 << SNES_WR_EN_PIN));
  65. /*-------------------------------------------------*/
  66. }
  67. void sreg_set(uint32_t addr)
  68. {
  69. uint8_t i = 24;
  70. debug(DEBUG_SREG,"sreg_set: addr=0x%08lx",addr);
  71. while(i--) {
  72. if ((addr & ( 1L << i))){
  73. debug(DEBUG_SREG,"1");
  74. AVR_ADDR_SER_PORT |= ( 1 << AVR_ADDR_SER_PIN);
  75. } else {
  76. AVR_ADDR_SER_PORT &= ~( 1 << AVR_ADDR_SER_PIN);
  77. debug(DEBUG_SREG,"0");
  78. }
  79. AVR_ADDR_SCK_PORT |= (1 << AVR_ADDR_SCK_PIN);
  80. AVR_ADDR_SCK_PORT &= ~(1 << AVR_ADDR_SCK_PIN);
  81. }
  82. debug(DEBUG_SREG,"\n");
  83. AVR_ADDR_LATCH_PORT |= (1 << AVR_ADDR_LATCH_PIN);
  84. AVR_ADDR_LATCH_PORT &= ~(1 << AVR_ADDR_LATCH_PIN);
  85. counter_load();
  86. }
  87. void sram_bulk_read_start(uint32_t addr)
  88. {
  89. debug(DEBUG_SRAM,"sram_bulk_read_start: addr=0x%08lx\n\r", addr);
  90. avr_data_in();
  91. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  92. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  93. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  94. sreg_set(addr);
  95. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  96. asm volatile ("nop");
  97. asm volatile ("nop");
  98. asm volatile ("nop");
  99. asm volatile ("nop");
  100. asm volatile ("nop");
  101. asm volatile ("nop");
  102. }
  103. inline void sram_bulk_read_next(void)
  104. {
  105. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  106. counter_up();
  107. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  108. asm volatile ("nop");
  109. asm volatile ("nop");
  110. asm volatile ("nop");
  111. asm volatile ("nop");
  112. asm volatile ("nop");
  113. asm volatile ("nop");
  114. }
  115. inline uint8_t sram_bulk_read(void)
  116. {
  117. return AVR_DATA_PIN;
  118. }
  119. void sram_bulk_read_end(void)
  120. {
  121. debug(DEBUG_SRAM,"sram_bulk_read_end:\n");
  122. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  123. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  124. avr_data_in();
  125. }
  126. uint8_t sram_read(uint32_t addr)
  127. {
  128. uint8_t byte;
  129. debug(DEBUG_SRAM_RAW,"sram_read: addr=0x%08lx\n\r", addr);
  130. avr_data_in();
  131. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  132. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  133. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  134. sreg_set(addr);
  135. AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
  136. asm volatile ("nop");
  137. asm volatile ("nop");
  138. asm volatile ("nop");
  139. asm volatile ("nop");
  140. asm volatile ("nop");
  141. asm volatile ("nop");
  142. byte = AVR_DATA_PIN;
  143. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  144. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  145. avr_data_in();
  146. return byte;
  147. }
  148. void sram_bulk_write_start(uint32_t addr)
  149. {
  150. debug(DEBUG_SRAM,"sram_bulk_write_start: addr=0x%08lx\n\r", addr);
  151. avr_data_out();
  152. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  153. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  154. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  155. sreg_set(addr);
  156. AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
  157. }
  158. inline void sram_bulk_write_next(void)
  159. {
  160. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  161. counter_up();
  162. AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
  163. }
  164. inline void sram_bulk_write( uint8_t data)
  165. {
  166. AVR_DATA_PORT = data;
  167. }
  168. void sram_bulk_write_end(void)
  169. {
  170. debug(DEBUG_SRAM,"sram_bulk_write_end:");
  171. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  172. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  173. avr_data_in();
  174. }
  175. void sram_write(uint32_t addr, uint8_t data)
  176. {
  177. debug(DEBUG_SRAM_RAW,"sram_write: addr=0x%08lx data=%x\n\r", addr, data);
  178. avr_data_out();
  179. AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
  180. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  181. AVR_RD_PORT |= (1 << AVR_RD_PIN);
  182. sreg_set(addr);
  183. AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
  184. AVR_DATA_PORT = data;
  185. AVR_WR_PORT |= (1 << AVR_WR_PIN);
  186. asm volatile ("nop");
  187. asm volatile ("nop");
  188. asm volatile ("nop");
  189. asm volatile ("nop");
  190. asm volatile ("nop");
  191. asm volatile ("nop");
  192. AVR_CS_PORT |= (1 << AVR_CS_PIN);
  193. avr_data_in();
  194. }
  195. void sram_bulk_copy(uint32_t addr, uint8_t * src, uint32_t len)
  196. {
  197. uint32_t i;
  198. uint8_t *ptr = src;
  199. debug(DEBUG_SRAM,"sram_copy: addr=0x%08lx src=0x%p len=%li\n\r", addr,src,len);
  200. sram_bulk_write_start(addr);
  201. for (i = addr; i < (addr + len); i++){
  202. sram_bulk_write(*ptr++);
  203. sram_bulk_write_next();
  204. }
  205. sram_bulk_write_end();
  206. }
  207. void sram_bulk_read_buffer(uint32_t addr, uint8_t * dst, uint32_t len)
  208. {
  209. uint32_t i;
  210. uint8_t *ptr = dst;
  211. debug(DEBUG_SRAM,"sram_bulk_read_buffer: addr=0x%08lx dst=0x%p len=%li\n\r", addr,dst,len);
  212. sram_bulk_read_start(addr);
  213. for (i = addr; i < (addr + len); i++) {
  214. *ptr = sram_bulk_read();
  215. sram_bulk_read_next();
  216. ptr++;
  217. }
  218. sram_bulk_read_end();
  219. }
  220. void sram_bulk_set(uint32_t addr, uint32_t len,uint8_t value){
  221. uint32_t i;
  222. debug(DEBUG_SRAM,"sram_bulk_set: addr=0x%08lx len=%li\n\r", addr,len);
  223. sram_bulk_write_start(addr);
  224. for (i = addr; i < (addr + len); i++) {
  225. if (0 == i % 0xfff)
  226. debug(DEBUG_SRAM,"sram_bulk_set: addr=0x%08lx\n\r", i);
  227. sram_bulk_write(value);
  228. sram_bulk_write_next();
  229. }
  230. sram_bulk_write_end();
  231. }
  232. void sram_setr(uint32_t addr, uint32_t len,uint8_t value)
  233. {
  234. uint32_t i;
  235. debug(DEBUG_SRAM,"sram_clear: addr=0x%08lx len=%li\n\r", addr,len);
  236. for (i = addr; i < (addr + len); i++) {
  237. if (0 == i % 0xfff)
  238. debug(DEBUG_SRAM,"sram_clear: addr=0x%08lx\n\r", i);
  239. sram_write(i, value);
  240. }
  241. }
  242. void sram_copy(uint32_t addr, uint8_t * src, uint32_t len)
  243. {
  244. uint32_t i;
  245. uint8_t *ptr = src;
  246. debug(DEBUG_SRAM,"sram_copy: addr=0x%08lx src=0x%p len=%li\n\r", addr,src,len);
  247. for (i = addr; i < (addr + len); i++)
  248. sram_write(i, *ptr++);
  249. }
  250. void sram_read_buffer(uint32_t addr, uint8_t * dst, uint32_t len)
  251. {
  252. uint32_t i;
  253. uint8_t *ptr = dst;
  254. debug(DEBUG_SRAM,"sram_read_buffer: addr=0x%08lx dst=0x%p len=%li\n\r", addr,dst,len);
  255. for (i = addr; i < (addr + len); i++) {
  256. *ptr = sram_read(i);
  257. ptr++;
  258. }
  259. }
  260. uint8_t sram_check(uint8_t * buffer, uint32_t len)
  261. {
  262. uint16_t cnt;
  263. debug(DEBUG_SRAM,"sram_check: len=%li\n\r",len);
  264. for (cnt = 0; cnt < len; cnt++)
  265. if (buffer[cnt])
  266. return 1;
  267. return 0;
  268. }