main.c 16 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. *
  11. * www.optixx.org
  12. *
  13. *
  14. * Version: 1.0
  15. * Created: 07/21/2009 03:32:16 PM
  16. * Author: david@optixx.org
  17. *
  18. * =====================================================================================
  19. */
  20. #include <avr/io.h>
  21. #include <avr/interrupt.h> /* for sei() */
  22. #include <util/delay.h> /* for _delay_ms() */
  23. #include <stdlib.h>
  24. #include <avr/pgmspace.h> /* required by usbdrv.h */
  25. #include <avr/eeprom.h>
  26. #include "usbdrv.h"
  27. #include "oddebug.h" /* This is also an example for using debug
  28. * macros */
  29. #include "config.h"
  30. #include "requests.h" /* The custom request numbers we use */
  31. #include "uart.h"
  32. #include "sram.h"
  33. #include "debug.h"
  34. #include "info.h"
  35. #include "dump.h"
  36. #include "crc.h"
  37. #include "usb_bulk.h"
  38. #include "timer.h"
  39. #include "watchdog.h"
  40. #include "huffman-decode.h"
  41. #include "rle.h"
  42. #include "loader.h"
  43. #include "shared_memory.h"
  44. extern const char _rom[] PROGMEM;
  45. extern FILE uart_stdout;
  46. uint8_t debug_level = ( DEBUG | DEBUG_USB | DEBUG_CRC );
  47. uint8_t read_buffer[TRANSFER_BUFFER_SIZE];
  48. uint32_t req_addr = 0;
  49. uint32_t req_addr_end = 0;
  50. uint32_t req_size;
  51. uint8_t req_bank;
  52. uint32_t req_bank_size;
  53. uint16_t req_bank_cnt;
  54. uint8_t req_state = REQ_STATUS_IDLE;
  55. uint8_t rx_remaining = 0;
  56. uint8_t tx_remaining = 0;
  57. uint16_t sync_errors = 0;
  58. uint8_t tx_buffer[32];
  59. uint8_t data_buffer[4];
  60. uint32_t addr;
  61. uint16_t crc = 0;
  62. usbMsgLen_t usbFunctionSetup(uchar data[8])
  63. {
  64. usbRequest_t *rq = (void *) data;
  65. uint8_t ret_len = 0;
  66. /*
  67. * -------------------------------------------------------------------------
  68. */
  69. if (rq->bRequest == USB_UPLOAD_INIT) {
  70. if (req_state != REQ_STATUS_IDLE){
  71. debug(DEBUG_USB,"USB_UPLOAD_INIT: ERROR state is not REQ_STATUS_IDLE\n");
  72. return 0;
  73. }
  74. req_bank = 0;
  75. rx_remaining = 0;
  76. req_bank_size = (uint32_t)1 << rq->wValue.word;
  77. sync_errors = 0;
  78. crc = 0;
  79. shared_memory_put(SHARED_MEM_CMD_UPLOAD_START,0);
  80. debug(DEBUG_USB,"USB_UPLOAD_INIT: bank_size=0x%08lx\n", req_bank_size);
  81. /*
  82. * -------------------------------------------------------------------------
  83. */
  84. } else if (rq->bRequest == USB_UPLOAD_ADDR) {
  85. req_state = REQ_STATUS_UPLOAD;
  86. req_addr = rq->wValue.word;
  87. req_addr = req_addr << 16;
  88. req_addr = req_addr | rq->wIndex.word;
  89. if (rx_remaining) {
  90. sync_errors++;
  91. debug
  92. (DEBUG_USB,"USB_UPLOAD_ADDR: Out of sync addr=0x%lx remain=%i packet=%i sync_error=%i\n",
  93. req_addr, rx_remaining, rq->wLength.word, sync_errors);
  94. ret_len = 0;
  95. }
  96. rx_remaining = rq->wLength.word;
  97. ret_len = USB_MAX_TRANS;
  98. if (req_addr && (req_addr % 0x1000) == 0) {
  99. debug(DEBUG_USB,"USB_UPLOAD_ADDR: bank=0x%02x addr=0x%08lx crc=%04x\n",
  100. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  101. }
  102. if (req_addr && req_addr % req_bank_size == 0) {
  103. debug(DEBUG_USB,"USB_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx\n",
  104. req_bank, req_addr);
  105. req_bank++;
  106. shared_memory_put(SHARED_MEM_CMD_UPLOAD_PROGESS,req_bank);
  107. }
  108. ret_len = USB_MAX_TRANS;
  109. /*
  110. * -------------------------------------------------------------------------
  111. */
  112. } else if (rq->bRequest == USB_DOWNLOAD_INIT) {
  113. debug(DEBUG_USB,"USB_DOWNLOAD_INIT\n");
  114. /*
  115. * -------------------------------------------------------------------------
  116. */
  117. } else if (rq->bRequest == USB_DOWNLOAD_ADDR) {
  118. debug(DEBUG_USB,"USB_DOWNLOAD_ADDR\n");
  119. /*
  120. * -------------------------------------------------------------------------
  121. */
  122. } else if (rq->bRequest == USB_BULK_UPLOAD_INIT) {
  123. req_bank = 0;
  124. rx_remaining = 0;
  125. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: %i %i\n",rq->wValue.word, rq->wIndex.word);
  126. req_bank_size = (uint32_t)(1L << rq->wValue.word);
  127. req_bank_cnt = rq->wIndex.word;
  128. req_addr_end = (uint32_t)req_bank_size * req_bank_cnt;
  129. sync_errors = 0;
  130. debug(DEBUG_USB,"USB_BULK_UPLOAD_INIT: bank_size=0x%08lx bank_cnt=0x%x end_addr=0x%08lx\n",
  131. req_bank_size, req_bank_cnt, req_addr_end);
  132. shared_memory_put(SHARED_MEM_CMD_UPLOAD_START,0);
  133. if (req_addr == 0x000000){
  134. timer_start();
  135. }
  136. /*
  137. * -------------------------------------------------------------------------
  138. */
  139. } else if (rq->bRequest == USB_BULK_UPLOAD_ADDR) {
  140. req_state = REQ_STATUS_BULK_UPLOAD;
  141. req_addr = rq->wValue.word;
  142. req_addr = req_addr << 16;
  143. req_addr = req_addr | rq->wIndex.word;
  144. sram_bulk_write_start(req_addr);
  145. rx_remaining = rq->wLength.word;
  146. if (req_addr && req_addr % req_bank_size == 0) {
  147. #ifdef FLT_DEBUG
  148. debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  149. req_bank, req_addr,timer_stop());
  150. #else
  151. debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%i\n",
  152. req_bank, req_addr,timer_stop_int());
  153. #endif
  154. req_bank++;
  155. timer_start();
  156. }
  157. ret_len = USB_MAX_TRANS;
  158. /*
  159. * -------------------------------------------------------------------------
  160. */
  161. } else if (rq->bRequest == USB_BULK_UPLOAD_NEXT) {
  162. req_state = REQ_STATUS_BULK_UPLOAD;
  163. req_addr = rq->wValue.word;
  164. req_addr = req_addr << 16;
  165. req_addr = req_addr | rq->wIndex.word;
  166. rx_remaining = rq->wLength.word;
  167. #if 0
  168. if (req_addr && (req_addr % 0x1000) == 0) {
  169. debug(DEBUG_USB,"USB_BULK_UPLOAD_NEXT: bank=0x%02x addr=0x%08lx crc=%04x\n",
  170. req_bank, req_addr,crc_check_bulk_memory(req_addr - 0x1000,req_addr,req_bank_size));
  171. }
  172. sram_bulk_write_start(req_addr);
  173. #endif
  174. if (req_addr && ( req_addr % req_bank_size) == 0) {
  175. #ifdef FLT_DEBUG
  176. debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  177. req_bank, req_addr,timer_stop());
  178. #else
  179. debug(DEBUG_USB,"USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%i\n",
  180. req_bank, req_addr,timer_stop_int());
  181. #endif
  182. req_bank++;
  183. shared_memory_put(SHARED_MEM_CMD_UPLOAD_PROGESS,req_bank);
  184. timer_start();
  185. }
  186. ret_len = USB_MAX_TRANS;
  187. /*
  188. * -------------------------------------------------------------------------
  189. */
  190. } else if (rq->bRequest == USB_BULK_UPLOAD_END) {
  191. if (req_state != REQ_STATUS_BULK_UPLOAD){
  192. debug(DEBUG_USB,"USB_BULK_UPLOAD_END: ERROR state is not REQ_STATUS_BULK_UPLOAD\n");
  193. return 0;
  194. }
  195. debug(DEBUG_USB,"USB_BULK_UPLOAD_END:\n");
  196. req_state = REQ_STATUS_IDLE;
  197. sram_bulk_write_end();
  198. shared_memory_put(SHARED_MEM_CMD_UPLOAD_END,0);
  199. ret_len = 0;
  200. /*
  201. * -------------------------------------------------------------------------
  202. */
  203. } else if (rq->bRequest == USB_CRC) {
  204. req_addr = rq->wValue.word;
  205. req_addr = req_addr << 16;
  206. req_addr = req_addr | rq->wIndex.word;
  207. debug(DEBUG_USB,"USB_CRC: addr=0x%08lx \n", req_addr);
  208. crc_check_bulk_memory(0x000000, req_addr, req_bank_size);
  209. ret_len = 0;
  210. /*
  211. * -------------------------------------------------------------------------
  212. */
  213. } else if (rq->bRequest == USB_MODE_SNES) {
  214. req_state = REQ_STATUS_SNES;
  215. debug(DEBUG_USB,"USB_MODE_SNES:\n");
  216. ret_len = 0;
  217. /*
  218. * -------------------------------------------------------------------------
  219. */
  220. } else if (rq->bRequest == USB_MODE_AVR) {
  221. req_state = REQ_STATUS_AVR;
  222. debug(DEBUG_USB,"USB_MODE_AVR:\n");
  223. ret_len = 0;
  224. /*
  225. * -------------------------------------------------------------------------
  226. */
  227. } else if (rq->bRequest == USB_AVR_RESET) {
  228. debug(DEBUG_USB,"USB_AVR_RESET:\n");
  229. soft_reset();
  230. ret_len = 0;
  231. /*
  232. * -------------------------------------------------------------------------
  233. */
  234. } else if (rq->bRequest == USB_CRC_ADDR) {
  235. req_state = REQ_STATUS_CRC;
  236. req_addr = rq->wValue.word;
  237. req_addr = req_addr << 16;
  238. req_addr = req_addr | rq->wIndex.word;
  239. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%i\n", req_addr,
  240. rq->wLength.word);
  241. req_size = rq->wLength.word;
  242. req_size = req_size << 2;
  243. tx_remaining = 2;
  244. debug(DEBUG_USB,"USB_CRC_ADDR: addr=0x%lx size=%li\n", req_addr, req_size);
  245. crc = crc_check_memory_range(req_addr, req_size, read_buffer);
  246. tx_buffer[0] = crc & 0xff;
  247. tx_buffer[1] = (crc >> 8) & 0xff;
  248. ret_len = 2;
  249. req_state = REQ_STATUS_IDLE;
  250. }
  251. usbMsgPtr = data_buffer;
  252. return ret_len; /* default for not implemented requests: return
  253. * no data back to host */
  254. }
  255. /*
  256. * -------------------------------------------------------------------------
  257. */
  258. void test_read_write(){
  259. uint8_t i;
  260. uint32_t addr;
  261. avr_bus_active();
  262. addr = 0x000000;
  263. i = 1;
  264. while (addr++ <= 0x0000ff){
  265. sram_write(addr,i++);
  266. }
  267. addr = 0x000000;
  268. while (addr++ <= 0x0000ff){
  269. info("read addr=0x%08lx %x\n",addr,sram_read(addr));
  270. }
  271. }
  272. void test_bulk_read_write(){
  273. uint8_t i;
  274. uint32_t addr;
  275. avr_bus_active();
  276. addr = 0x000000;
  277. i = 0;
  278. sram_bulk_write_start(addr);
  279. while (addr++ <= 0x8000){
  280. sram_bulk_write(i++);
  281. sram_bulk_write_next();
  282. }
  283. sram_bulk_write_end();
  284. addr = 0x000000;
  285. sram_bulk_read_start(addr);
  286. while (addr <= 0x8000){
  287. info("addr=0x%08lx %x\n",addr,sram_bulk_read());
  288. sram_bulk_read_next();
  289. addr++;
  290. }
  291. sram_bulk_read_end();
  292. }
  293. void test_non_zero_memory(uint32_t bottom_addr,uint32_t top_addr)
  294. {
  295. uint32_t addr = 0;
  296. uint8_t c;
  297. sram_bulk_read_start(bottom_addr);
  298. for (addr = bottom_addr; addr < top_addr; addr++) {
  299. c = sram_bulk_read();
  300. if (c!=0xff)
  301. info("addr=0x%08lx c=0x%x\n",addr,c);
  302. sram_bulk_read_next();
  303. }
  304. sram_bulk_read_end();
  305. }
  306. void test_crc(){
  307. info("test_crc: clear\n");
  308. avr_bus_active();
  309. sram_bulk_set(0x000000,0x10000,0xff);
  310. info("test_crc: crc\n");
  311. crc_check_bulk_memory(0x000000,0x10000,0x8000);
  312. info("test_crc: check\n");
  313. test_non_zero_memory(0x000000,0x10000);
  314. }
  315. uint16_t read_byte_pgm(uint16_t addr){
  316. return pgm_read_byte((PGM_VOID_P)addr);
  317. }
  318. uint16_t read_byte_ee(uint16_t addr){
  319. return eeprom_read_byte((uint8_t*)addr);
  320. }
  321. void decompress(PGM_VOID_P addr, uint16_t(*fp)(uint16_t)){
  322. uint16_t c;
  323. uint32_t i = 0;
  324. huffman_dec_ctx_t ctx;
  325. huffman_dec_init(&ctx, fp);
  326. huffman_dec_set_addr(&ctx, (uint16_t)addr);
  327. while(1){
  328. i++;
  329. c=huffman_dec_byte(&ctx);
  330. if (i%1024==0)
  331. info(".");
  332. if(c>0xff){
  333. return;
  334. }
  335. c&=0xff;
  336. sram_bulk_write(c);
  337. }
  338. }
  339. void decompress_huffman(void){
  340. info("Decompress Rom %p to 0x000000\n",(void*)_rom);
  341. sram_bulk_write_start(0x000000);
  342. decompress(&_rom,read_byte_pgm);
  343. sram_bulk_write_end();
  344. info("Done\n");
  345. }
  346. void send_reset(){
  347. info("Reset Snes\n");
  348. snes_reset_on();
  349. snes_reset_lo();
  350. _delay_ms(2);
  351. snes_reset_hi();
  352. snes_reset_off();
  353. }
  354. void send_irq(){
  355. snes_irq_on();
  356. snes_irq_lo();
  357. _delay_us(20);
  358. snes_irq_hi();
  359. snes_irq_off();
  360. }
  361. void set_rom_mode(){
  362. if (req_bank_size == 0x8000){
  363. snes_lorom();
  364. info("Set Snes lowrom \n");
  365. } else {
  366. snes_hirom();
  367. info("Set Snes hirom \n");
  368. }
  369. }
  370. void usb_connect(){
  371. uint8_t i = 0;
  372. info("USB init\n");
  373. usbDeviceDisconnect(); /* enforce re-enumeration, do this while */
  374. cli();
  375. info("USB disconnect\n");
  376. i = 10;
  377. while (--i) { /* fake USB disconnect for > 250 ms */
  378. led_on();
  379. _delay_ms(35);
  380. led_off();
  381. _delay_ms(65);
  382. }
  383. led_on();
  384. usbDeviceConnect();
  385. info("USB connect\n");
  386. }
  387. void boot_startup_rom(){
  388. uint8_t i = 0;
  389. info("Activate AVR bus\n");
  390. avr_bus_active();
  391. info("IRQ off\n");
  392. snes_irq_lo();
  393. snes_irq_off();
  394. snes_lorom();
  395. info("Set Snes lowrom \n");
  396. /*
  397. info("Set Snes hirom\n");
  398. snes_hirom();
  399. info("Disable snes WR\n");
  400. snes_wr_disable();
  401. info("IRQ off\n");
  402. snes_irq_lo();
  403. snes_irq_off();
  404. */
  405. rle_decode(&_rom, ROM_SIZE, 0x000000);
  406. dump_memory(0x10000 - 0x100, 0x10000);
  407. snes_reset_hi();
  408. snes_reset_off();
  409. snes_irq_lo();
  410. snes_irq_off();
  411. info("IRQ off\n");
  412. snes_hirom();
  413. snes_wr_disable();
  414. info("Disable snes WR\n");
  415. snes_bus_active();
  416. info("Activate Snes bus\n");
  417. _delay_ms(100);
  418. info("Reset Snes\n");
  419. send_reset();
  420. #if 0
  421. i = 20;
  422. info("Wait");
  423. while (--i){
  424. _delay_ms(500);
  425. info(".");
  426. }
  427. info("\n");
  428. #endif
  429. }
  430. int main(void)
  431. {
  432. uint8_t i;
  433. uint16_t irq_count = 0;
  434. uart_init();
  435. stdout = &uart_stdout;
  436. info("Sytem start\n");
  437. system_init();
  438. #if 0
  439. test_read_write();
  440. test_bulk_read_write();
  441. test_crc();
  442. while(1);
  443. #endif
  444. info("Boot startup rom\n");
  445. boot_startup_rom();
  446. usbInit();
  447. usb_connect();
  448. while (1){
  449. avr_bus_active();
  450. info("Activate AVR bus\n");
  451. info("IRQ off\n");
  452. snes_irq_lo();
  453. snes_irq_off();
  454. info("Set Snes lowrom\n");
  455. snes_lorom();
  456. info("Disable snes WR\n");
  457. snes_wr_disable();
  458. sei();
  459. info("USB poll\n");
  460. while (req_state != REQ_STATUS_SNES){
  461. usbPoll();
  462. }
  463. shared_memory_put(SHARED_MEM_CMD_TERMINATE,0);
  464. info("USB poll done\n");
  465. snes_reset_hi();
  466. snes_reset_off();
  467. snes_irq_lo();
  468. snes_irq_off();
  469. info("IRQ off\n");
  470. set_rom_mode();
  471. snes_wr_disable();
  472. info("Disable snes WR\n");
  473. snes_bus_active();
  474. info("Activate Snes bus\n");
  475. _delay_ms(100);
  476. info("Reset Snes\n");
  477. send_reset();
  478. info("Poll\n");
  479. while (req_state != REQ_STATUS_AVR){
  480. usbPoll();
  481. #ifdef DO_IRQ
  482. i = 10;
  483. while (--i) { /* fake USB disconnect for > 250 ms */
  484. _delay_ms(100);
  485. }
  486. info("Send IRQ %i\n",++irq_count);
  487. send_irq();
  488. #endif
  489. #ifdef DO_BUS_STEALING
  490. avr_bus_active();
  491. sram_bulk_read_start(0x003000);
  492. c = sram_bulk_read();
  493. i = 5;
  494. while (--i) {
  495. _delay_ms(500);
  496. info("Wait to switch to snes mode %i\n", i);
  497. }
  498. if (req_bank_size == 0x8000){
  499. snes_lorom();
  500. info("Set Snes lowrom \n");
  501. } else {
  502. snes_hirom();
  503. info("Set Snes hirom \n");
  504. }
  505. snes_wr_disable();
  506. info("Disable snes WR\n");
  507. snes_bus_active();
  508. info("Activate Snes bus\n");
  509. info("Read 0x3000=%c\n",c);
  510. #endif
  511. }
  512. }
  513. return 0;
  514. }