main.c 11 KB

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  1. /*
  2. * =====================================================================================
  3. *
  4. * ________ .__ __ ________ ____ ________
  5. * \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
  6. * / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
  7. * / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
  8. * \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
  9. * \__> \/ \/ \/ \/ \/
  10. *
  11. * www.optixx.org
  12. *
  13. *
  14. * Version: 1.0
  15. * Created: 07/21/2009 03:32:16 PM
  16. * Author: david@optixx.org
  17. *
  18. * =====================================================================================
  19. */
  20. #include <avr/io.h>
  21. #include <avr/interrupt.h>
  22. #include <util/delay.h>
  23. #include <stdlib.h>
  24. #include <avr/pgmspace.h>
  25. #include <avr/eeprom.h>
  26. #include "usbdrv.h"
  27. #include "oddebug.h"
  28. #include "config.h"
  29. #include "requests.h"
  30. #include "uart.h"
  31. #include "sram.h"
  32. #include "debug.h"
  33. #include "info.h"
  34. #include "dump.h"
  35. #include "crc.h"
  36. #include "usb_bulk.h"
  37. #include "timer.h"
  38. #include "watchdog.h"
  39. #include "rle.h"
  40. #include "loader.h"
  41. #include "command.h"
  42. #include "shared_memory.h"
  43. #include "testing.h"
  44. extern const char _rom[] PROGMEM;
  45. extern FILE uart_stdout;
  46. uint8_t debug_level = (DEBUG | DEBUG_USB | DEBUG_CRC);
  47. uint8_t read_buffer[TRANSFER_BUFFER_SIZE];
  48. uint32_t req_addr = 0;
  49. uint32_t req_addr_end = 0;
  50. uint32_t req_size;
  51. uint8_t req_bank;
  52. uint32_t req_bank_size;
  53. uint16_t req_bank_cnt;
  54. uint8_t req_state = REQ_STATUS_IDLE;
  55. uint8_t rx_remaining = 0;
  56. uint8_t tx_remaining = 0;
  57. uint16_t sync_errors = 0;
  58. uint8_t tx_buffer[32];
  59. uint8_t data_buffer[4];
  60. uint32_t addr;
  61. uint16_t crc = 0;
  62. usbMsgLen_t usbFunctionSetup(uchar data[8])
  63. {
  64. usbRequest_t *rq = (void *) data;
  65. uint8_t ret_len = 0;
  66. if (rq->bRequest == USB_BULK_UPLOAD_INIT) {
  67. req_bank = 0;
  68. rx_remaining = 0;
  69. debug(DEBUG_USB, "USB_BULK_UPLOAD_INIT: %i %i\n", rq->wValue.word,
  70. rq->wIndex.word);
  71. req_bank_size = (uint32_t) (1L << rq->wValue.word);
  72. req_bank_cnt = rq->wIndex.word;
  73. req_addr_end = (uint32_t) req_bank_size *req_bank_cnt;
  74. sync_errors = 0;
  75. debug(DEBUG_USB,
  76. "USB_BULK_UPLOAD_INIT: bank_size=0x%08lx bank_cnt=0x%x end_addr=0x%08lx\n",
  77. req_bank_size, req_bank_cnt, req_addr_end);
  78. shared_memory_write(SHARED_MEM_TX_CMD_BANK_COUNT, req_bank_cnt);
  79. if (req_addr == 0x000000) {
  80. timer_start();
  81. }
  82. /*
  83. * -------------------------------------------------------------------------
  84. */
  85. } else if (rq->bRequest == USB_BULK_UPLOAD_ADDR) {
  86. req_state = REQ_STATUS_BULK_UPLOAD;
  87. req_addr = rq->wValue.word;
  88. req_addr = req_addr << 16;
  89. req_addr = req_addr | rq->wIndex.word;
  90. rx_remaining = rq->wLength.word;
  91. if (req_addr && req_addr % req_bank_size == 0) {
  92. #ifdef FLT_DEBUG
  93. debug(DEBUG_USB,
  94. "USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  95. req_bank, req_addr, timer_stop());
  96. #else
  97. debug(DEBUG_USB,
  98. "USB_BULK_UPLOAD_ADDR: req_bank=0x%02x addr=0x%08lx time=%i\n",
  99. req_bank, req_addr, timer_stop_int());
  100. #endif
  101. req_bank++;
  102. shared_memory_write(SHARED_MEM_TX_CMD_UPLOAD_PROGESS, req_bank);
  103. sram_bulk_write_start(req_addr);
  104. timer_start();
  105. } else {
  106. sram_bulk_write_start(req_addr);
  107. }
  108. ret_len = USB_MAX_TRANS;
  109. /*
  110. * -------------------------------------------------------------------------
  111. */
  112. } else if (rq->bRequest == USB_BULK_UPLOAD_NEXT) {
  113. req_state = REQ_STATUS_BULK_UPLOAD;
  114. req_addr = rq->wValue.word;
  115. req_addr = req_addr << 16;
  116. req_addr = req_addr | rq->wIndex.word;
  117. rx_remaining = rq->wLength.word;
  118. #if 0
  119. if (req_addr && (req_addr % 0x1000) == 0) {
  120. debug(DEBUG_USB,
  121. "USB_BULK_UPLOAD_NEXT: bank=0x%02x addr=0x%08lx crc=%04x\n",
  122. req_bank, req_addr, crc_check_bulk_memory(req_addr - 0x1000,
  123. req_addr,
  124. req_bank_size));
  125. }
  126. sram_bulk_write_start(req_addr);
  127. #endif
  128. if (req_addr && (req_addr % req_bank_size) == 0) {
  129. #ifdef FLT_DEBUG
  130. debug(DEBUG_USB,
  131. "USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%.4f\n",
  132. req_bank, req_addr, timer_stop());
  133. #else
  134. debug(DEBUG_USB,
  135. "USB_BULK_UPLOAD_NEXT: req_bank=0x%02x addr=0x%08lx time=%i\n",
  136. req_bank, req_addr, timer_stop_int());
  137. #endif
  138. req_bank++;
  139. timer_start();
  140. shared_memory_write(SHARED_MEM_TX_CMD_BANK_CURRENT, req_bank);
  141. sram_bulk_write_start(req_addr);
  142. }
  143. ret_len = USB_MAX_TRANS;
  144. /*
  145. * -------------------------------------------------------------------------
  146. */
  147. } else if (rq->bRequest == USB_BULK_UPLOAD_END) {
  148. if (req_state != REQ_STATUS_BULK_UPLOAD) {
  149. debug(DEBUG_USB,
  150. "USB_BULK_UPLOAD_END: ERROR state is not REQ_STATUS_BULK_UPLOAD\n");
  151. return 0;
  152. }
  153. debug(DEBUG_USB, "USB_BULK_UPLOAD_END:\n");
  154. req_state = REQ_STATUS_IDLE;
  155. sram_bulk_write_end();
  156. shared_memory_write(SHARED_MEM_TX_CMD_UPLOAD_END, 0);
  157. ret_len = 0;
  158. /*
  159. * -------------------------------------------------------------------------
  160. */
  161. } else if (rq->bRequest == USB_CRC) {
  162. req_addr = rq->wValue.word;
  163. req_addr = req_addr << 16;
  164. req_addr = req_addr | rq->wIndex.word;
  165. debug(DEBUG_USB, "USB_CRC: addr=0x%08lx \n", req_addr);
  166. crc_check_bulk_memory(0x000000, req_addr, req_bank_size);
  167. ret_len = 0;
  168. /*
  169. * -------------------------------------------------------------------------
  170. */
  171. } else if (rq->bRequest == USB_MODE_SNES) {
  172. req_state = REQ_STATUS_SNES;
  173. debug(DEBUG_USB, "USB_MODE_SNES:\n");
  174. ret_len = 0;
  175. /*
  176. * -------------------------------------------------------------------------
  177. */
  178. } else if (rq->bRequest == USB_MODE_AVR) {
  179. req_state = REQ_STATUS_AVR;
  180. debug(DEBUG_USB, "USB_MODE_AVR:\n");
  181. ret_len = 0;
  182. /*
  183. * -------------------------------------------------------------------------
  184. */
  185. } else if (rq->bRequest == USB_AVR_RESET) {
  186. debug(DEBUG_USB, "USB_AVR_RESET:\n");
  187. soft_reset();
  188. ret_len = 0;
  189. /*
  190. * -------------------------------------------------------------------------
  191. */
  192. } else if (rq->bRequest == USB_CRC_ADDR) {
  193. req_state = REQ_STATUS_CRC;
  194. req_addr = rq->wValue.word;
  195. req_addr = req_addr << 16;
  196. req_addr = req_addr | rq->wIndex.word;
  197. debug(DEBUG_USB, "USB_CRC_ADDR: addr=0x%lx size=%i\n", req_addr,
  198. rq->wLength.word);
  199. req_size = rq->wLength.word;
  200. req_size = req_size << 2;
  201. tx_remaining = 2;
  202. debug(DEBUG_USB, "USB_CRC_ADDR: addr=0x%lx size=%li\n", req_addr,
  203. req_size);
  204. crc = crc_check_memory_range(req_addr, req_size, read_buffer);
  205. tx_buffer[0] = crc & 0xff;
  206. tx_buffer[1] = (crc >> 8) & 0xff;
  207. ret_len = 2;
  208. req_state = REQ_STATUS_IDLE;
  209. }
  210. usbMsgPtr = data_buffer;
  211. return ret_len; /* default for not implemented requests: return no data back to host */
  212. }
  213. /*
  214. * -------------------------------------------------------------------------
  215. */
  216. void usb_connect()
  217. {
  218. uint8_t i = 0;
  219. info("USB init\n");
  220. usbDeviceDisconnect(); /* enforce re-enumeration, do this while */
  221. cli();
  222. info("USB disconnect\n");
  223. i = 10;
  224. while (--i) { /* fake USB disconnect for > 250 ms */
  225. led_on();
  226. _delay_ms(35);
  227. led_off();
  228. _delay_ms(65);
  229. }
  230. led_on();
  231. usbDeviceConnect();
  232. info("USB connect\n");
  233. }
  234. void boot_startup_rom()
  235. {
  236. info("Activate AVR bus\n");
  237. avr_bus_active();
  238. info("IRQ off\n");
  239. snes_irq_lo();
  240. snes_irq_off();
  241. snes_lorom();
  242. info("Set Snes lowrom \n");
  243. rle_decode(&_rom, ROM_BUFFER_SIZE, 0x000000);
  244. dump_memory(0x10000 - 0x100, 0x10000);
  245. snes_reset_hi();
  246. snes_reset_off();
  247. snes_irq_lo();
  248. snes_irq_off();
  249. info("IRQ off\n");
  250. snes_hirom();
  251. snes_wr_disable();
  252. info("Disable snes WR\n");
  253. snes_bus_active();
  254. info("Activate Snes bus\n");
  255. _delay_ms(100);
  256. info("Reset Snes\n");
  257. send_reset();
  258. _delay_ms(100);
  259. #if 0
  260. uint8_t i = 0;
  261. i = 20;
  262. info("Wait");
  263. while (--i) {
  264. _delay_ms(500);
  265. info(".");
  266. }
  267. info("\n");
  268. #endif
  269. }
  270. int main(void)
  271. {
  272. uart_init();
  273. stdout = &uart_stdout;
  274. info("Sytem start\n");
  275. system_init();
  276. #if 0
  277. test_read_write();
  278. test_bulk_read_write();
  279. test_crc();
  280. while (1);
  281. #endif
  282. info("Boot startup rom\n");
  283. boot_startup_rom();
  284. usbInit();
  285. usb_connect();
  286. while (1) {
  287. avr_bus_active();
  288. info("Activate AVR bus\n");
  289. info("IRQ off\n");
  290. snes_irq_lo();
  291. snes_irq_off();
  292. info("Set Snes lowrom\n");
  293. snes_lorom();
  294. info("Disable snes WR\n");
  295. snes_wr_disable();
  296. sei();
  297. info("USB poll\n");
  298. while (req_state != REQ_STATUS_SNES) {
  299. usbPoll();
  300. }
  301. shared_memory_write(SHARED_MEM_TX_CMD_TERMINATE, 0);
  302. info("USB poll done\n");
  303. snes_reset_hi();
  304. snes_reset_off();
  305. snes_irq_lo();
  306. snes_irq_off();
  307. info("IRQ off\n");
  308. set_rom_mode();
  309. snes_wr_disable();
  310. info("Disable snes WR\n");
  311. snes_bus_active();
  312. info("Activate Snes bus\n");
  313. _delay_ms(100);
  314. info("Reset Snes\n");
  315. send_reset();
  316. info("Poll\n");
  317. while (req_state != REQ_STATUS_AVR) {
  318. usbPoll();
  319. #ifdef DO_IRQ
  320. uint8_t i;
  321. uint16_t irq_count = 0;
  322. i = 10;
  323. while (--i) {
  324. _delay_ms(100);
  325. }
  326. info("Send IRQ %i\n", ++irq_count);
  327. send_irq();
  328. #endif
  329. #ifdef DO_BUS_STEALING
  330. avr_bus_active();
  331. sram_bulk_read_start(0x003000);
  332. c = sram_bulk_read();
  333. i = 5;
  334. while (--i) {
  335. _delay_ms(500);
  336. info("Wait to switch to snes mode %i\n", i);
  337. }
  338. if (req_bank_size == 0x8000) {
  339. snes_lorom();
  340. info("Set Snes lowrom \n");
  341. } else {
  342. snes_hirom();
  343. info("Set Snes hirom \n");
  344. }
  345. snes_wr_disable();
  346. info("Disable snes WR\n");
  347. snes_bus_active();
  348. info("Activate Snes bus\n");
  349. info("Read 0x3000=%c\n", c);
  350. #endif
  351. }
  352. }
  353. return 0;
  354. }