memory.cpp 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125
  1. #ifdef SCPU_CPP
  2. /*****
  3. * These 3 functions control bus timing for the CPU.
  4. * cpu_io is an I/O cycle, and always 6 clock cycles long.
  5. * mem_read / mem_write indicate memory access bus cycles.
  6. * they are either 6, 8, or 12 bus cycles long, depending
  7. * both on location and the $420d.d0 FastROM enable bit.
  8. *****/
  9. void sCPU::op_io() {
  10. status.clock_count = 6;
  11. precycle_edge();
  12. add_clocks(6);
  13. cycle_edge();
  14. }
  15. uint8 sCPU::op_read(uint32 addr) {
  16. status.clock_count = bus.speed(addr);
  17. precycle_edge();
  18. add_clocks(status.clock_count - 4);
  19. regs.mdr = bus.read(addr);
  20. add_clocks(4);
  21. cycle_edge();
  22. return regs.mdr;
  23. }
  24. void sCPU::op_write(uint32 addr, uint8 data) {
  25. status.clock_count = bus.speed(addr);
  26. precycle_edge();
  27. add_clocks(status.clock_count);
  28. regs.mdr = data;
  29. bus.write(addr, regs.mdr);
  30. cycle_edge();
  31. }
  32. //
  33. alwaysinline uint8 sCPU::op_readpc() {
  34. return op_read((regs.pc.b << 16) + regs.pc.w++);
  35. }
  36. alwaysinline uint8 sCPU::op_readstack() {
  37. if(regs.e) {
  38. regs.s.l++;
  39. } else {
  40. regs.s.w++;
  41. }
  42. return op_read(regs.s.w);
  43. }
  44. alwaysinline uint8 sCPU::op_readstackn() {
  45. return op_read(++regs.s.w);
  46. }
  47. alwaysinline uint8 sCPU::op_readaddr(uint32 addr) {
  48. return op_read(addr & 0xffff);
  49. }
  50. alwaysinline uint8 sCPU::op_readlong(uint32 addr) {
  51. return op_read(addr & 0xffffff);
  52. }
  53. alwaysinline uint8 sCPU::op_readdbr(uint32 addr) {
  54. return op_read(((regs.db << 16) + addr) & 0xffffff);
  55. }
  56. alwaysinline uint8 sCPU::op_readpbr(uint32 addr) {
  57. return op_read((regs.pc.b << 16) + (addr & 0xffff));
  58. }
  59. alwaysinline uint8 sCPU::op_readdp(uint32 addr) {
  60. if(regs.e && regs.d.l == 0x00) {
  61. return op_read((regs.d & 0xff00) + ((regs.d + (addr & 0xffff)) & 0xff));
  62. } else {
  63. return op_read((regs.d + (addr & 0xffff)) & 0xffff);
  64. }
  65. }
  66. alwaysinline uint8 sCPU::op_readsp(uint32 addr) {
  67. return op_read((regs.s + (addr & 0xffff)) & 0xffff);
  68. }
  69. alwaysinline void sCPU::op_writestack(uint8 data) {
  70. op_write(regs.s.w, data);
  71. if(regs.e) {
  72. regs.s.l--;
  73. } else {
  74. regs.s.w--;
  75. }
  76. }
  77. alwaysinline void sCPU::op_writestackn(uint8 data) {
  78. op_write(regs.s.w--, data);
  79. }
  80. alwaysinline void sCPU::op_writeaddr(uint32 addr, uint8 data) {
  81. op_write(addr & 0xffff, data);
  82. }
  83. alwaysinline void sCPU::op_writelong(uint32 addr, uint8 data) {
  84. op_write(addr & 0xffffff, data);
  85. }
  86. alwaysinline void sCPU::op_writedbr(uint32 addr, uint8 data) {
  87. op_write(((regs.db << 16) + addr) & 0xffffff, data);
  88. }
  89. alwaysinline void sCPU::op_writepbr(uint32 addr, uint8 data) {
  90. op_write((regs.pc.b << 16) + (addr & 0xffff), data);
  91. }
  92. alwaysinline void sCPU::op_writedp(uint32 addr, uint8 data) {
  93. if(regs.e && regs.d.l == 0x00) {
  94. op_write((regs.d & 0xff00) + ((regs.d + (addr & 0xffff)) & 0xff), data);
  95. } else {
  96. op_write((regs.d + (addr & 0xffff)) & 0xffff, data);
  97. }
  98. }
  99. alwaysinline void sCPU::op_writesp(uint32 addr, uint8 data) {
  100. op_write((regs.s + (addr & 0xffff)) & 0xffff, data);
  101. }
  102. #endif //ifdef SCPU_CPP