Interrupt Processing Sequence The interrupt processing sequence is initiated as the direct result of hard- vare Abort, Interrupt Request, Non-Maskable Interrupt, or Reset inputs. The interrupt sequence can also be initiated as a result of the Break or Co-Processor instructions within the software. The following listings describe the function of each cycle in the interrupt processing sequence: Hardware Interrupt /ABORT, /IRQ, /NMI, /RES Inputs Cycle No. E = 0 E = 1 Address Data R/W SYNC VDA VPA VP Description 1 1 PC X 1 1 1 1 1 Internal Operation 2 2 PC X 1 0 0 0 1 Internal Operation 3 [1] S PB 0 0 1 0 1 Write PB to Stack, S-1�S 4 3 S PCH [2] 0[3] 0 1 0 1 Write PCH to Stack, S-1�S 5 4 S PCL 12] 0[3] 0 1 0 1 Write PCL to Stack, S-1�S 6 5 S P [4] 0[3] 0 1 0 1 Write P to Stack, S-1�S 7 6 VL (VL) 1 0 1 0 0 Read Vector Low Byte, 0->PD, 1->P1, OO->PB 8 7 VH (VH) 1 0 1 0 0 Read Vector High 8yte Software Interrupt - BRK, COP Instructions Cycle No. E = 0 E = 1 Address Data R/W SYNC VDA VPA VP Description 1 1 PC-2 X 1 1 1 1 1 Opcode 2 2 PC-1 X 1 0 0 1 1 Signature 3 111 S PB 0 0 1 0 1 Write PB to Stack, S-1�S 4 3 S PCH 0 0 1 0 1 Write PCH to Stack, S-1 - S 5 4 S PCL 0 0 1 0 1 Write PCL to Stack, S-1�S 6 5 S P 0 0 1 0 1 Write P to Stack, S-1�S 7 6 VL (VL) 1 0 1 0 0 Read Vector Low Byte, 0�Po, 1�Pl, 00�PB 8 7 VH (VH) 1 0 1 0 0 Read Vector High Byte Notes: [1] Delete this cycle in Emulation mode. [2] Abort writes address of aborted opcode. [3] R/W remains in the high state during Reset. [4] In Emulation mode, bit 4 written to stack is changed to 0. Table 3. Vector Locations Emulation Native Priority Name Source (E = 1) (E = 0) Level ABORT Hardware 00FFF8,9 00FFE8,9 2 BRK Software 00FFFE,F 00FFE6,7 N/A COP Software 00FFF4,5 00FFE4,5 N/A IRQ Hardware 00FFFE,F 00FFEE,F 4 NMI Hardware 00FFFA,B 00FFEA,B 3 RES Hardware 00FFFC.D 00FFFC,D 1