top.v 48 KB

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  1. `define YES
  2. `include "revision.v"
  3. module lfsre(
  4. input clk,
  5. output reg [16:0] lfsr);
  6. wire d0;
  7. xnor(d0,lfsr[16],lfsr[13]);
  8. always @(posedge clk) begin
  9. lfsr <= {lfsr[15:0],d0};
  10. end
  11. endmodule
  12. module oldram256x1s(
  13. input d,
  14. input we,
  15. input wclk,
  16. input [7:0] a,
  17. output o);
  18. wire sel0 = (a[7:6] == 0);
  19. wire o0;
  20. RAM64X1S r0(.O(o0), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]), .A5(a[5]), .D(d), .WCLK(wclk), .WE(sel0 & we));
  21. wire sel1 = (a[7:6] == 1);
  22. wire o1;
  23. RAM64X1S r1(.O(o1), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]), .A5(a[5]), .D(d), .WCLK(wclk), .WE(sel1 & we));
  24. wire sel2 = (a[7:6] == 2);
  25. wire o2;
  26. RAM64X1S r2(.O(o2), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]), .A5(a[5]), .D(d), .WCLK(wclk), .WE(sel2 & we));
  27. wire sel3 = (a[7:6] == 3);
  28. wire o3;
  29. RAM64X1S r3(.O(o3), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]), .A5(a[5]), .D(d), .WCLK(wclk), .WE(sel3 & we));
  30. assign o = (a[7] == 0) ? ((a[6] == 0) ? o0 : o1) : ((a[6] == 0) ? o2 : o3);
  31. endmodule
  32. module ring64(
  33. input clk,
  34. input i,
  35. output o);
  36. wire o0, o1, o2;
  37. SRL16E ring0( .CLK(clk), .CE(1), .D(i), .A0(1), .A1(1), .A2(1), .A3(1), .Q(o0));
  38. SRL16E ring1( .CLK(clk), .CE(1), .D(o0), .A0(1), .A1(1), .A2(1), .A3(1), .Q(o1));
  39. SRL16E ring2( .CLK(clk), .CE(1), .D(o1), .A0(1), .A1(1), .A2(1), .A3(1), .Q(o2));
  40. SRL16E ring3( .CLK(clk), .CE(1), .D(o2), .A0(1), .A1(1), .A2(1), .A3(1), .Q(o));
  41. endmodule
  42. module ram256x1s(
  43. input d,
  44. input we,
  45. input wclk,
  46. input [7:0] a,
  47. output o);
  48. wire [1:0] rsel = a[7:6];
  49. wire [3:0] oo;
  50. genvar i;
  51. generate
  52. for (i = 0; i < 4; i=i+1) begin : ramx
  53. RAM64X1S r0(.O(oo[i]), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]), .A5(a[5]), .D(d), .WCLK(wclk), .WE((rsel == i) & we));
  54. end
  55. endgenerate
  56. assign o = oo[rsel];
  57. endmodule
  58. module ram448x1s(
  59. input d,
  60. input we,
  61. input wclk,
  62. input [8:0] a,
  63. output o);
  64. wire [2:0] rsel = a[8:6];
  65. wire [7:0] oo;
  66. genvar i;
  67. generate
  68. for (i = 0; i < 7; i=i+1) begin : ramx
  69. RAM64X1S r0(.O(oo[i]), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]), .A5(a[5]), .D(d), .WCLK(wclk), .WE((rsel == i) & we));
  70. end
  71. endgenerate
  72. assign o = oo[rsel];
  73. endmodule
  74. module ram400x1s(
  75. input d,
  76. input we,
  77. input wclk,
  78. input [8:0] a,
  79. output o);
  80. wire [2:0] rsel = a[8:6];
  81. wire [6:0] oo;
  82. genvar i;
  83. generate
  84. for (i = 0; i < 6; i=i+1) begin : ramx
  85. RAM64X1S r0(.O(oo[i]), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]), .A5(a[5]), .D(d), .WCLK(wclk), .WE((rsel == i) & we));
  86. end
  87. endgenerate
  88. RAM16X1S r6(.O(oo[6]), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .D(d), .WCLK(wclk), .WE((rsel == 6) & we));
  89. assign o = oo[rsel];
  90. endmodule
  91. module ram256x8s(
  92. input [7:0] d,
  93. input we,
  94. input wclk,
  95. input [7:0] a,
  96. output [7:0] o);
  97. genvar i;
  98. generate
  99. for (i = 0; i < 8; i=i+1) begin : ramx
  100. ram256x1s ramx(
  101. .d(d[i]),
  102. .we(we),
  103. .wclk(wclk),
  104. .a(a),
  105. .o(o[i]));
  106. end
  107. endgenerate
  108. endmodule
  109. module ram32x8s(
  110. input [7:0] d,
  111. input we,
  112. input wclk,
  113. input [4:0] a,
  114. output [7:0] o);
  115. genvar i;
  116. generate
  117. for (i = 0; i < 8; i=i+1) begin : ramx
  118. RAM32X1S r0(.O(o[i]), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]), .D(d[i]), .WCLK(wclk), .WE(we));
  119. end
  120. endgenerate
  121. endmodule
  122. module ram64x8s(
  123. input [7:0] d,
  124. input we,
  125. input wclk,
  126. input [5:0] a,
  127. output [7:0] o);
  128. genvar i;
  129. generate
  130. for (i = 0; i < 8; i=i+1) begin : ramx
  131. RAM64X1S r0(.O(o[i]), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]), .A4(a[4]), .A5(a[5]), .D(d[i]), .WCLK(wclk), .WE(we));
  132. end
  133. endgenerate
  134. endmodule
  135. module mRAM32X1D(
  136. input D,
  137. input WE,
  138. input WCLK,
  139. input A0, // port A
  140. input A1,
  141. input A2,
  142. input A3,
  143. input A4,
  144. input DPRA0, // port B
  145. input DPRA1,
  146. input DPRA2,
  147. input DPRA3,
  148. input DPRA4,
  149. output DPO, // port A out
  150. output SPO); // port B out
  151. parameter INIT = 32'b0;
  152. wire hDPO;
  153. wire lDPO;
  154. wire hSPO;
  155. wire lSPO;
  156. RAM16X1D
  157. #( .INIT(INIT[15:0]) )
  158. lo(
  159. .D(D),
  160. .WE(WE & !A4),
  161. .WCLK(WCLK),
  162. .A0(A0),
  163. .A1(A1),
  164. .A2(A2),
  165. .A3(A3),
  166. .DPRA0(DPRA0),
  167. .DPRA1(DPRA1),
  168. .DPRA2(DPRA2),
  169. .DPRA3(DPRA3),
  170. .DPO(lDPO),
  171. .SPO(lSPO));
  172. RAM16X1D
  173. #( .INIT(INIT[31:16]) )
  174. hi(
  175. .D(D),
  176. .WE(WE & A4),
  177. .WCLK(WCLK),
  178. .A0(A0),
  179. .A1(A1),
  180. .A2(A2),
  181. .A3(A3),
  182. .DPRA0(DPRA0),
  183. .DPRA1(DPRA1),
  184. .DPRA2(DPRA2),
  185. .DPRA3(DPRA3),
  186. .DPO(hDPO),
  187. .SPO(hSPO));
  188. assign DPO = DPRA4 ? hDPO : lDPO;
  189. assign SPO = A4 ? hSPO : lSPO;
  190. endmodule
  191. module mRAM64X1D(
  192. input D,
  193. input WE,
  194. input WCLK,
  195. input A0, // port A
  196. input A1,
  197. input A2,
  198. input A3,
  199. input A4,
  200. input A5,
  201. input DPRA0, // port B
  202. input DPRA1,
  203. input DPRA2,
  204. input DPRA3,
  205. input DPRA4,
  206. input DPRA5,
  207. output DPO, // port A out
  208. output SPO); // port B out
  209. parameter INIT = 64'b0;
  210. wire hDPO;
  211. wire lDPO;
  212. wire hSPO;
  213. wire lSPO;
  214. mRAM32X1D
  215. #( .INIT(INIT[31:0]) )
  216. lo(
  217. .D(D),
  218. .WE(WE & !A5),
  219. .WCLK(WCLK),
  220. .A0(A0),
  221. .A1(A1),
  222. .A2(A2),
  223. .A3(A3),
  224. .A4(A4),
  225. .DPRA0(DPRA0),
  226. .DPRA1(DPRA1),
  227. .DPRA2(DPRA2),
  228. .DPRA3(DPRA3),
  229. .DPRA4(DPRA4),
  230. .DPO(lDPO),
  231. .SPO(lSPO));
  232. mRAM32X1D
  233. #( .INIT(INIT[63:32]) )
  234. hi(
  235. .D(D),
  236. .WE(WE & A5),
  237. .WCLK(WCLK),
  238. .A0(A0),
  239. .A1(A1),
  240. .A2(A2),
  241. .A3(A3),
  242. .A4(A4),
  243. .DPRA0(DPRA0),
  244. .DPRA1(DPRA1),
  245. .DPRA2(DPRA2),
  246. .DPRA3(DPRA3),
  247. .DPRA4(DPRA4),
  248. .DPO(hDPO),
  249. .SPO(hSPO));
  250. assign DPO = DPRA5 ? hDPO : lDPO;
  251. assign SPO = A5 ? hSPO : lSPO;
  252. endmodule
  253. module mRAM128X1D(
  254. input D,
  255. input WE,
  256. input WCLK,
  257. input A0, // port A
  258. input A1,
  259. input A2,
  260. input A3,
  261. input A4,
  262. input A5,
  263. input A6,
  264. input DPRA0, // port B
  265. input DPRA1,
  266. input DPRA2,
  267. input DPRA3,
  268. input DPRA4,
  269. input DPRA5,
  270. input DPRA6,
  271. output DPO, // port A out
  272. output SPO); // port B out
  273. parameter INIT = 128'b0;
  274. wire hDPO;
  275. wire lDPO;
  276. wire hSPO;
  277. wire lSPO;
  278. mRAM64X1D
  279. #( .INIT(INIT[63:0]) )
  280. lo(
  281. .D(D),
  282. .WE(WE & !A6),
  283. .WCLK(WCLK),
  284. .A0(A0),
  285. .A1(A1),
  286. .A2(A2),
  287. .A3(A3),
  288. .A4(A4),
  289. .A5(A5),
  290. .DPRA0(DPRA0),
  291. .DPRA1(DPRA1),
  292. .DPRA2(DPRA2),
  293. .DPRA3(DPRA3),
  294. .DPRA4(DPRA4),
  295. .DPRA5(DPRA5),
  296. .DPO(lDPO),
  297. .SPO(lSPO));
  298. mRAM64X1D
  299. #( .INIT(INIT[127:64]) )
  300. hi(
  301. .D(D),
  302. .WE(WE & A6),
  303. .WCLK(WCLK),
  304. .A0(A0),
  305. .A1(A1),
  306. .A2(A2),
  307. .A3(A3),
  308. .A4(A4),
  309. .A5(A5),
  310. .DPRA0(DPRA0),
  311. .DPRA1(DPRA1),
  312. .DPRA2(DPRA2),
  313. .DPRA3(DPRA3),
  314. .DPRA4(DPRA4),
  315. .DPRA5(DPRA5),
  316. .DPO(hDPO),
  317. .SPO(hSPO));
  318. assign DPO = DPRA6 ? hDPO : lDPO;
  319. assign SPO = A6 ? hSPO : lSPO;
  320. endmodule
  321. module mRAM256X1D(
  322. input D,
  323. input WE,
  324. input WCLK,
  325. input A0, // port A
  326. input A1,
  327. input A2,
  328. input A3,
  329. input A4,
  330. input A5,
  331. input A6,
  332. input A7,
  333. input DPRA0, // port B
  334. input DPRA1,
  335. input DPRA2,
  336. input DPRA3,
  337. input DPRA4,
  338. input DPRA5,
  339. input DPRA6,
  340. input DPRA7,
  341. output DPO, // port A out
  342. output SPO); // port B out
  343. wire hDPO;
  344. wire lDPO;
  345. wire hSPO;
  346. wire lSPO;
  347. mRAM128X1D
  348. lo(
  349. .D(D),
  350. .WE(WE & !A7),
  351. .WCLK(WCLK),
  352. .A0(A0),
  353. .A1(A1),
  354. .A2(A2),
  355. .A3(A3),
  356. .A4(A4),
  357. .A5(A5),
  358. .A6(A6),
  359. .DPRA0(DPRA0),
  360. .DPRA1(DPRA1),
  361. .DPRA2(DPRA2),
  362. .DPRA3(DPRA3),
  363. .DPRA4(DPRA4),
  364. .DPRA5(DPRA5),
  365. .DPRA6(DPRA6),
  366. .DPO(lDPO),
  367. .SPO(lSPO));
  368. mRAM128X1D
  369. hi(
  370. .D(D),
  371. .WE(WE & A7),
  372. .WCLK(WCLK),
  373. .A0(A0),
  374. .A1(A1),
  375. .A2(A2),
  376. .A3(A3),
  377. .A4(A4),
  378. .A5(A5),
  379. .A6(A6),
  380. .DPRA0(DPRA0),
  381. .DPRA1(DPRA1),
  382. .DPRA2(DPRA2),
  383. .DPRA3(DPRA3),
  384. .DPRA4(DPRA4),
  385. .DPRA5(DPRA5),
  386. .DPRA6(DPRA6),
  387. .DPO(hDPO),
  388. .SPO(hSPO));
  389. assign DPO = DPRA7 ? hDPO : lDPO;
  390. assign SPO = A7 ? hSPO : lSPO;
  391. endmodule
  392. module ram32x8d(
  393. input [7:0] ad,
  394. input wea,
  395. input wclk,
  396. input [4:0] a,
  397. input [4:0] b,
  398. output [7:0] ao,
  399. output [7:0] bo
  400. );
  401. genvar i;
  402. generate
  403. for (i = 0; i < 8; i=i+1) begin : ramx
  404. mRAM32X1D ramx(
  405. .D(ad[i]),
  406. .WE(wea),
  407. .WCLK(wclk),
  408. .A0(a[0]),
  409. .A1(a[1]),
  410. .A2(a[2]),
  411. .A3(a[3]),
  412. .A4(a[4]),
  413. .DPRA0(b[0]),
  414. .DPRA1(b[1]),
  415. .DPRA2(b[2]),
  416. .DPRA3(b[3]),
  417. .DPRA4(b[4]),
  418. .SPO(ao[i]),
  419. .DPO(bo[i]));
  420. end
  421. endgenerate
  422. endmodule
  423. module ram64x8d(
  424. input [7:0] ad,
  425. input wea,
  426. input wclk,
  427. input [5:0] a,
  428. input [5:0] b,
  429. output [7:0] ao,
  430. output [7:0] bo
  431. );
  432. genvar i;
  433. generate
  434. for (i = 0; i < 8; i=i+1) begin : ramx
  435. mRAM64X1D ramx(
  436. .D(ad[i]),
  437. .WE(wea),
  438. .WCLK(wclk),
  439. .A0(a[0]),
  440. .A1(a[1]),
  441. .A2(a[2]),
  442. .A3(a[3]),
  443. .A4(a[4]),
  444. .A5(a[5]),
  445. .DPRA0(b[0]),
  446. .DPRA1(b[1]),
  447. .DPRA2(b[2]),
  448. .DPRA3(b[3]),
  449. .DPRA4(b[4]),
  450. .DPRA5(b[5]),
  451. .SPO(ao[i]),
  452. .DPO(bo[i]));
  453. end
  454. endgenerate
  455. endmodule
  456. // Same but latched read port, for CPU
  457. module ram32x8rd(
  458. input wclk,
  459. input [15:0] ad,
  460. input wea,
  461. input [4:0] a,
  462. input [4:0] b,
  463. output reg [15:0] ao,
  464. output reg [15:0] bo
  465. );
  466. wire [15:0] _ao;
  467. wire [15:0] _bo;
  468. always @(posedge wclk)
  469. begin
  470. ao <= _ao;
  471. bo <= _bo;
  472. end
  473. genvar i;
  474. generate
  475. for (i = 0; i < 16; i=i+1) begin : ramx
  476. mRAM32X1D ramx(
  477. .D(ad[i]),
  478. .WE(wea),
  479. .WCLK(wclk),
  480. .A0(a[0]),
  481. .A1(a[1]),
  482. .A2(a[2]),
  483. .A3(a[3]),
  484. .A4(a[4]),
  485. .DPRA0(b[0]),
  486. .DPRA1(b[1]),
  487. .DPRA2(b[2]),
  488. .DPRA3(b[3]),
  489. .DPRA4(b[4]),
  490. .SPO(_ao[i]),
  491. .DPO(_bo[i]));
  492. end
  493. endgenerate
  494. endmodule
  495. module ram128x8rd(
  496. input wclk,
  497. input [15:0] ad,
  498. input wea,
  499. input [6:0] a,
  500. input [6:0] b,
  501. output reg [15:0] ao,
  502. output reg [15:0] bo
  503. );
  504. wire [15:0] _ao;
  505. wire [15:0] _bo;
  506. always @(posedge wclk)
  507. begin
  508. ao <= _ao;
  509. bo <= _bo;
  510. end
  511. genvar i;
  512. generate
  513. for (i = 0; i < 8; i=i+1) begin : ramx
  514. mRAM128X1D ramx(
  515. .D(ad[i]),
  516. .WE(wea),
  517. .WCLK(wclk),
  518. .A0(a[0]),
  519. .A1(a[1]),
  520. .A2(a[2]),
  521. .A3(a[3]),
  522. .A4(a[4]),
  523. .A5(a[5]),
  524. .A6(a[6]),
  525. .DPRA0(b[0]),
  526. .DPRA1(b[1]),
  527. .DPRA2(b[2]),
  528. .DPRA3(b[3]),
  529. .DPRA4(b[4]),
  530. .DPRA5(b[5]),
  531. .DPRA6(b[6]),
  532. .SPO(_ao[i]),
  533. .DPO(_bo[i]));
  534. end
  535. endgenerate
  536. endmodule
  537. module ram256x8rd(
  538. input wclk,
  539. input [7:0] ad,
  540. input wea,
  541. input [7:0] a,
  542. input [7:0] b,
  543. output reg [7:0] ao,
  544. output reg [7:0] bo
  545. );
  546. wire [7:0] _ao;
  547. wire [7:0] _bo;
  548. always @(posedge wclk)
  549. begin
  550. ao <= _ao;
  551. bo <= _bo;
  552. end
  553. genvar i;
  554. generate
  555. for (i = 0; i < 8; i=i+1) begin : ramx
  556. mRAM256X1D ramx(
  557. .D(ad[i]),
  558. .WE(wea),
  559. .WCLK(wclk),
  560. .A0(a[0]),
  561. .A1(a[1]),
  562. .A2(a[2]),
  563. .A3(a[3]),
  564. .A4(a[4]),
  565. .A5(a[5]),
  566. .A6(a[6]),
  567. .A7(a[7]),
  568. .DPRA0(b[0]),
  569. .DPRA1(b[1]),
  570. .DPRA2(b[2]),
  571. .DPRA3(b[3]),
  572. .DPRA4(b[4]),
  573. .DPRA5(b[5]),
  574. .DPRA6(b[6]),
  575. .DPRA7(b[7]),
  576. .SPO(_ao[i]),
  577. .DPO(_bo[i]));
  578. end
  579. endgenerate
  580. endmodule
  581. module ram448x9s(
  582. input [8:0] d,
  583. input we,
  584. input wclk,
  585. input [8:0] a,
  586. output [8:0] o);
  587. genvar i;
  588. generate
  589. for (i = 0; i < 9; i=i+1) begin : ramx
  590. ram448x1s ramx(
  591. .d(d[i]),
  592. .we(we),
  593. .wclk(wclk),
  594. .a(a),
  595. .o(o[i]));
  596. end
  597. endgenerate
  598. endmodule
  599. module ram400x9s(
  600. input [8:0] d,
  601. input we,
  602. input wclk,
  603. input [8:0] a,
  604. output [8:0] o);
  605. genvar i;
  606. generate
  607. for (i = 0; i < 9; i=i+1) begin : ramx
  608. ram400x1s ramx(
  609. .d(d[i]),
  610. .we(we),
  611. .wclk(wclk),
  612. .a(a),
  613. .o(o[i]));
  614. end
  615. endgenerate
  616. endmodule
  617. module ram400x8s(
  618. input [7:0] d,
  619. input we,
  620. input wclk,
  621. input [8:0] a,
  622. output [7:0] o);
  623. genvar i;
  624. generate
  625. for (i = 0; i < 8; i=i+1) begin : ramx
  626. ram400x1s ramx(
  627. .d(d[i]),
  628. .we(we),
  629. .wclk(wclk),
  630. .a(a),
  631. .o(o[i]));
  632. end
  633. endgenerate
  634. endmodule
  635. module ram400x7s(
  636. input [6:0] d,
  637. input we,
  638. input wclk,
  639. input [8:0] a,
  640. output [6:0] o);
  641. genvar i;
  642. generate
  643. for (i = 0; i < 7; i=i+1) begin : ramx
  644. ram400x1s ramx(
  645. .d(d[i]),
  646. .we(we),
  647. .wclk(wclk),
  648. .a(a),
  649. .o(o[i]));
  650. end
  651. endgenerate
  652. endmodule
  653. // SPI can be many things, so to be clear, this implementation:
  654. // MSB first
  655. // CPOL 0, leading edge when SCK rises
  656. // CPHA 0, sample on leading, setup on trailing
  657. module SPI_memory(
  658. input clk,
  659. input SCK, input MOSI, output MISO, input SSEL,
  660. output wire [15:0] raddr, // read address
  661. output reg [15:0] waddr, // write address
  662. output reg [7:0] data_w,
  663. input [7:0] data_r,
  664. output reg we,
  665. output reg re,
  666. output mem_clk
  667. );
  668. reg [15:0] paddr;
  669. reg [4:0] count;
  670. wire [4:0] _count = (count == 23) ? 16 : (count + 1);
  671. assign mem_clk = clk;
  672. // sync SCK to the FPGA clock using a 3-bits shift register
  673. reg [2:0] SCKr; always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
  674. wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
  675. wire SCK_fallingedge = (SCKr[2:1]==2'b10); // and falling edges
  676. // same thing for SSEL
  677. reg [2:0] SSELr; always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
  678. wire SSEL_active = ~SSELr[1]; // SSEL is active low
  679. wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
  680. wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
  681. // and for MOSI
  682. reg [1:0] MOSIr; always @(posedge clk) MOSIr <= {MOSIr[0], MOSI};
  683. wire MOSI_data = MOSIr[1];
  684. assign raddr = (count[4] == 0) ? {paddr[14:0], MOSI} : paddr;
  685. always @(posedge clk)
  686. begin
  687. if (~SSEL_active) begin
  688. count <= 0;
  689. re <= 0;
  690. we <= 0;
  691. end else
  692. if (SCK_risingedge) begin
  693. if (count[4] == 0) begin
  694. we <= 0;
  695. paddr <= raddr;
  696. re <= (count == 15);
  697. end else begin
  698. data_w <= {data_w[6:0], MOSI_data};
  699. if (count == 23) begin
  700. we <= paddr[15];
  701. re <= !paddr[15];
  702. waddr <= paddr;
  703. paddr <= paddr + 1;
  704. end else begin
  705. we <= 0;
  706. re <= 0;
  707. end
  708. end
  709. count <= _count;
  710. end
  711. if (SCK_fallingedge) begin
  712. re <= 0;
  713. we <= 0;
  714. end
  715. end
  716. reg readbit;
  717. always @*
  718. begin
  719. case (count[2:0])
  720. 3'd0: readbit <= data_r[7];
  721. 3'd1: readbit <= data_r[6];
  722. 3'd2: readbit <= data_r[5];
  723. 3'd3: readbit <= data_r[4];
  724. 3'd4: readbit <= data_r[3];
  725. 3'd5: readbit <= data_r[2];
  726. 3'd6: readbit <= data_r[1];
  727. 3'd7: readbit <= data_r[0];
  728. endcase
  729. end
  730. assign MISO = readbit;
  731. endmodule
  732. // This is a Delta-Sigma Digital to Analog Converter
  733. `define MSBI 12 // Most significant Bit of DAC input, 12 means 13-bit
  734. module dac(DACout, DACin, Clk, Reset);
  735. output DACout; // This is the average output that feeds low pass filter
  736. reg DACout; // for optimum performance, ensure that this ff is in IOB
  737. input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
  738. input Clk;
  739. input Reset;
  740. reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
  741. reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
  742. reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
  743. reg [`MSBI+2:0] DeltaB; // B input of Delta adder
  744. always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
  745. always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
  746. always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
  747. always @(posedge Clk or posedge Reset)
  748. begin
  749. if (Reset) begin
  750. SigmaLatch <= #1 1'b1 << (`MSBI+1);
  751. DACout <= #1 1'b0;
  752. end else begin
  753. SigmaLatch <= #1 SigmaAdder;
  754. DACout <= #1 SigmaLatch[`MSBI+2];
  755. end
  756. end
  757. endmodule
  758. module top(
  759. input clka,
  760. output [2:0] vga_red,
  761. output [2:0] vga_green,
  762. output [2:0] vga_blue,
  763. output vga_hsync_n,
  764. output vga_vsync_n,
  765. input SCK, // arduino 13
  766. input MOSI, // arduino 11
  767. inout MISO, // arduino 12
  768. input SSEL, // arduino 9
  769. inout AUX, // arduino 2
  770. output AUDIOL,
  771. output AUDIOR,
  772. output flashMOSI,
  773. input flashMISO,
  774. output flashSCK,
  775. output flashSSEL
  776. );
  777. wire mem_clk;
  778. wire [7:0] host_mem_data_wr;
  779. reg [7:0] mem_data_rd;
  780. reg [7:0] latched_mem_data_rd;
  781. wire [14:0] mem_w_addr; // Combined write address
  782. wire [14:0] mem_r_addr; // Combined read address
  783. wire [14:0] host_mem_w_addr;
  784. wire [14:0] host_mem_r_addr;
  785. wire host_mem_wr;
  786. wire mem_rd;
  787. wire vga_clk;
  788. ck_div #(.DIV_BY(2), .MULT_BY(4)) vga_ck_gen(.ck_in(clka), .ck_out(vga_clk));
  789. wire [15:0] j1_insn;
  790. wire [12:0] j1_insn_addr;
  791. wire [15:0] j1_mem_addr;
  792. wire [15:0] j1_mem_dout;
  793. wire j1_mem_wr;
  794. wire [7:0] j1insnl_read;
  795. wire [7:0] j1insnh_read;
  796. wire [7:0] mem_data_rd0;
  797. wire [7:0] mem_data_rd1;
  798. wire [7:0] mem_data_rd2;
  799. wire [7:0] mem_data_rd3;
  800. wire [7:0] mem_data_rd4;
  801. wire [7:0] mem_data_rd5;
  802. wire gdMISO;
  803. always @(posedge vga_clk)
  804. if (mem_rd)
  805. latched_mem_data_rd <= mem_data_rd;
  806. SPI_memory spi1(
  807. .clk(vga_clk),
  808. .SCK(SCK), .MOSI(MOSI), .MISO(gdMISO), .SSEL(SSEL),
  809. .raddr(host_mem_r_addr),
  810. .waddr(host_mem_w_addr),
  811. .data_w(host_mem_data_wr),
  812. .data_r(latched_mem_data_rd),
  813. .we(host_mem_wr),
  814. .re(mem_rd),
  815. .mem_clk(mem_clk));
  816. wire host_busy = host_mem_wr | mem_rd;
  817. wire mem_wr = host_busy ? host_mem_wr : j1_mem_wr;
  818. wire [7:0] mem_data_wr = host_busy ? host_mem_data_wr : j1_mem_dout;
  819. wire [14:0] mem_addr = host_busy ? (host_mem_wr ? host_mem_w_addr : host_mem_r_addr) : j1_mem_addr;
  820. assign mem_w_addr = host_busy ? host_mem_w_addr : j1_mem_addr;
  821. assign mem_r_addr = host_busy ? host_mem_r_addr : j1_mem_addr;
  822. reg signed [15:0] sample_l;
  823. reg signed [15:0] sample_r;
  824. reg [6:0] modvoice = 64;
  825. reg [14:0] bg_color;
  826. reg [7:0] pin2mode = 0;
  827. wire pin2f = (pin2mode == 8'h46);
  828. wire pin2j = (pin2mode == 8'h4A);
  829. wire flashsel = (AUX == 0) & pin2f;
  830. assign MISO = SSEL ? (flashsel ? flashMISO : 1'bz) : gdMISO;
  831. // assign MISO = SSEL ? (1'bz ) : gdMISO;
  832. // PULLUP MISO_pullup(.O(MISO));
  833. // IOBUF MISO_iobuf(
  834. // .I(gdMISO),
  835. // .IO(MISO),
  836. // .T(SSEL));
  837. // user-visible registers
  838. reg [7:0] frames;
  839. reg [8:0] scrollx;
  840. reg [8:0] scrolly;
  841. reg jkmode;
  842. wire [7:0] palette16l_read;
  843. wire [7:0] palette16h_read;
  844. wire [4:0] palette16_addr;
  845. wire [15:0] palette16_data;
  846. // 11'b00001xxxxx0: low
  847. wire palette16_wr = (mem_wr & (mem_w_addr[14:11] == 5) & (mem_w_addr[10:6] == 1));
  848. ram32x8d palette16l(
  849. .a(mem_addr[5:1]),
  850. .wclk(mem_clk),
  851. .wea((mem_w_addr[0] == 0) & palette16_wr),
  852. .ad(mem_data_wr),
  853. .ao(palette16l_read),
  854. .b(palette16_addr),
  855. .bo(palette16_data[7:0]));
  856. ram32x8d palette16h(
  857. .a(mem_addr[5:1]),
  858. .wclk(mem_clk),
  859. .wea((mem_w_addr[0] == 1) & palette16_wr),
  860. .ad(mem_data_wr),
  861. .ao(palette16h_read),
  862. .b(palette16_addr),
  863. .bo(palette16_data[15:8]));
  864. wire [7:0] palette4l_read;
  865. wire [7:0] palette4h_read;
  866. wire [4:0] palette4_addr;
  867. wire [15:0] palette4_data;
  868. // 11'b00010xxxxx0: low
  869. wire palette4_wr = (mem_wr & (mem_w_addr[14:11] == 5) & (mem_w_addr[10:6] == 2));
  870. ram32x8d palette4l(
  871. .a(mem_addr[5:1]),
  872. .wclk(mem_clk),
  873. .wea((mem_w_addr[0] == 0) & palette4_wr),
  874. .ad(mem_data_wr),
  875. .ao(palette4l_read),
  876. .b(palette4_addr),
  877. .bo(palette4_data[7:0]));
  878. ram32x8d palette4h(
  879. .a(mem_addr[5:1]),
  880. .wclk(mem_clk),
  881. .wea((mem_w_addr[0] == 1) & palette4_wr),
  882. .ad(mem_data_wr),
  883. .ao(palette4h_read),
  884. .b(palette4_addr),
  885. .bo(palette4_data[15:8]));
  886. // Generate CounterX and CounterY
  887. // A single line is 1040 clocks. Line pair is 2080 clocks.
  888. reg [10:0] CounterX;
  889. reg [9:0] CounterY;
  890. wire CounterXmaxed = (CounterX==1040);
  891. always @(posedge vga_clk)
  892. if(CounterXmaxed)
  893. CounterX <= 0;
  894. else
  895. CounterX <= CounterX + 1;
  896. wire lastline = (CounterY == 665);
  897. wire [9:0] _CounterY = lastline ? 0 : (CounterY + 1);
  898. always @(posedge vga_clk)
  899. if (CounterXmaxed) begin
  900. CounterY <= _CounterY;
  901. if (lastline)
  902. frames <= frames + 1;
  903. end
  904. reg [12:0] comp_workcnt; // Compositor work address
  905. reg comp_workcnt_lt_400;
  906. always @(posedge vga_clk)
  907. begin
  908. if (CounterXmaxed & (CounterY[0] == 0)) begin
  909. comp_workcnt <= 0;
  910. comp_workcnt_lt_400 <= 1;
  911. end else begin
  912. comp_workcnt <= comp_workcnt + 1;
  913. if (comp_workcnt == 399)
  914. comp_workcnt_lt_400 <= 0;
  915. end
  916. end
  917. // horizontal
  918. // Front porch 56
  919. // Sync 120
  920. // Back porch 64
  921. // vertical
  922. // Front porch 37 lines
  923. // Sync 6
  924. // Back porch 23
  925. // `define HSTART (53 + 120 + 61)
  926. `define HSTART 0
  927. reg vga_HS, vga_VS, vga_active;
  928. always @(posedge vga_clk)
  929. begin
  930. vga_HS <= ((800 + 61) <= CounterX) & (CounterX < (800 + 61 + 120));
  931. vga_VS <= (35 <= CounterY) & (CounterY < (35 + 6));
  932. vga_active = ((`HSTART + 1) <= CounterX) & (CounterX < (`HSTART + 1 + 800)) & ((35 + 6 + 21) < CounterY) & (CounterY <= (35 + 6 + 21 + 600));
  933. end
  934. wire [10:0] xx = (CounterX - `HSTART);
  935. wire [10:0] xx_1 = (CounterX - `HSTART + 1);
  936. wire [10:0] yy = (CounterY + 2 - (35 + 6 + 21 + 1)); // yy range 0-665
  937. wire [10:0] column = comp_workcnt + scrollx;
  938. wire [10:0] row = yy[10:1] + scrolly;
  939. wire [7:0] glyph;
  940. wire [11:0] picaddr = {row[8:3], column[8:3]};
  941. wire en_pic = (mem_addr[14:12] == 0);
  942. RAM_PICTURE picture(
  943. .dia(0),
  944. .doa(glyph),
  945. .wea(0),
  946. .ena(1),
  947. .clka(vga_clk),
  948. .addra(picaddr),
  949. .dib(mem_data_wr),
  950. .dob(mem_data_rd0),
  951. .web(mem_wr),
  952. .enb(en_pic),
  953. .clkb(mem_clk),
  954. .addrb(mem_addr)
  955. );
  956. reg [2:0] _column;
  957. always @(posedge vga_clk)
  958. _column = column;
  959. wire en_chr = (mem_addr[14:12] == 1);
  960. wire [1:0] charout;
  961. RAM_CHR chars(
  962. .dia(0), .doa(charout), .wea(0), .ena(1), .clka(vga_clk), .addra({glyph, row[2:0], _column[2], ~_column[1:0]}),
  963. .dib(mem_data_wr), .dob(mem_data_rd1), .web(mem_wr), .enb(en_chr), .clkb(mem_clk), .addrb(mem_addr));
  964. reg [7:0] _glyph;
  965. always @(posedge vga_clk)
  966. _glyph <= glyph;
  967. wire [4:0] bg_r;
  968. wire [4:0] bg_g;
  969. wire [4:0] bg_b;
  970. wire en_pal = (mem_addr[14:11] == 4'b0100);
  971. wire [15:0] char_matte;
  972. RAM_PAL charpalette(
  973. .DIA(mem_data_wr),
  974. .WEA(mem_wr),
  975. .ENA(en_pal),
  976. .CLKA(mem_clk),
  977. .ADDRA(mem_addr),
  978. .DOA(mem_data_rd2),
  979. .SSRA(0),
  980. .DIB(0),
  981. .WEB(0),
  982. .ENB(1),
  983. .CLKB(vga_clk),
  984. .ADDRB({_glyph, charout}),
  985. .DOB(char_matte),
  986. .SSRB(0)
  987. );
  988. // wire [4:0] bg_mix_r = bg_color[14:10] + char_matte[14:10];
  989. // wire [4:0] bg_mix_g = bg_color[9:5] + char_matte[9:5];
  990. // wire [4:0] bg_mix_b = bg_color[4:0] + char_matte[4:0];
  991. // wire [14:0] char_final = char_matte[15] ? {bg_mix_r, bg_mix_g, bg_mix_b} : char_matte[14:0];
  992. wire [14:0] char_final = char_matte[15] ? bg_color : char_matte[14:0];
  993. reg [7:0] mem_data_rd_reg;
  994. // Collision detection RAM is readable during vblank
  995. // writes coll_d to coll_w_addr during render
  996. wire coll_rd = (yy >= 600); // 1 means reading
  997. wire [7:0] coll_d;
  998. wire [7:0] coll_w_addr;
  999. wire coll_we;
  1000. wire [7:0] coll_addr = coll_rd ? mem_r_addr[7:0] : coll_w_addr;
  1001. wire [7:0] coll_o;
  1002. ram256x8s coll(.o(coll_o), .a(coll_addr), .d(coll_d), .wclk(vga_clk), .we(~coll_rd & coll_we));
  1003. wire [7:0] screenshot_rd;
  1004. wire [7:0] voicefl_read;
  1005. wire [7:0] voicefh_read;
  1006. wire [7:0] voicela_read;
  1007. wire [7:0] voicera_read;
  1008. reg j1_reset = 0;
  1009. reg spr_disable = 0;
  1010. reg spr_page = 0;
  1011. // Screenshot notes
  1012. // three states, controlled by screenshot_primed, _done:
  1013. // primed done composer.A
  1014. // 0 0 screenshot disabled write(comp_write)
  1015. // 1 0 screenshot primed write(comp_write)
  1016. // 1 1 screenshot done read(mem_r_addr[9:1])
  1017. reg [8:0] screenshot_yy; // 9 bits, 0-400
  1018. reg screenshot_primed;
  1019. reg screenshot_done;
  1020. wire screenshot_reset;
  1021. wire [8:0] public_yy = coll_rd ? 300 : yy[10:1];
  1022. always @(posedge vga_clk)
  1023. begin
  1024. if (screenshot_reset)
  1025. screenshot_done <= 0;
  1026. else if (CounterXmaxed & screenshot_primed & !screenshot_done & (public_yy == screenshot_yy)) begin
  1027. screenshot_done <= 1;
  1028. end
  1029. end
  1030. always @(mem_data_rd_reg)
  1031. begin
  1032. casex (mem_r_addr[10:0])
  1033. 11'h000: mem_data_rd_reg <= 8'h6d; // Gameduino ident
  1034. 11'h001: mem_data_rd_reg <= `REVISION;
  1035. 11'h002: mem_data_rd_reg <= frames;
  1036. 11'h003: mem_data_rd_reg <= coll_rd; // called VBLANK, but really "is coll readable?"
  1037. 11'h004: mem_data_rd_reg <= scrollx[7:0];
  1038. 11'h005: mem_data_rd_reg <= scrollx[8];
  1039. 11'h006: mem_data_rd_reg <= scrolly[7:0];
  1040. 11'h007: mem_data_rd_reg <= scrolly[8];
  1041. 11'h008: mem_data_rd_reg <= jkmode;
  1042. 11'h009: mem_data_rd_reg <= j1_reset;
  1043. 11'h00a: mem_data_rd_reg <= spr_disable;
  1044. 11'h00b: mem_data_rd_reg <= spr_page;
  1045. 11'h00c: mem_data_rd_reg <= pin2mode;
  1046. 11'h00e: mem_data_rd_reg <= bg_color[7:0];
  1047. 11'h00f: mem_data_rd_reg <= bg_color[14:8];
  1048. 11'h010: mem_data_rd_reg <= sample_l[7:0];
  1049. 11'h011: mem_data_rd_reg <= sample_l[15:8];
  1050. 11'h012: mem_data_rd_reg <= sample_r[7:0];
  1051. 11'h013: mem_data_rd_reg <= sample_r[15:8];
  1052. 11'h014: mem_data_rd_reg <= modvoice;
  1053. 11'h01e: mem_data_rd_reg <= public_yy[7:0];
  1054. 11'h01f: mem_data_rd_reg <= {screenshot_done, 6'b000000, public_yy[8]};
  1055. 11'b00001xxxxx0: mem_data_rd_reg <= palette16l_read;
  1056. 11'b00001xxxxx1: mem_data_rd_reg <= palette16h_read;
  1057. 11'b00010xxxxx0: mem_data_rd_reg <= palette4l_read;
  1058. 11'b00010xxxxx1: mem_data_rd_reg <= palette4h_read;
  1059. 11'b001xxxxxxxx:
  1060. mem_data_rd_reg <= coll_rd ? coll_o : 8'hff;
  1061. 11'b010xxxxxx00: mem_data_rd_reg <= voicefl_read;
  1062. 11'b010xxxxxx01: mem_data_rd_reg <= voicefh_read;
  1063. 11'b010xxxxxx10: mem_data_rd_reg <= voicela_read;
  1064. 11'b010xxxxxx11: mem_data_rd_reg <= voicera_read;
  1065. 11'b011xxxxxxx0: mem_data_rd_reg <= j1insnl_read;
  1066. 11'b011xxxxxxx1: mem_data_rd_reg <= j1insnh_read;
  1067. 11'b1xxxxxxxxxx: mem_data_rd_reg <= screenshot_rd;
  1068. // default: mem_data_rd_reg <= 0;
  1069. endcase
  1070. end
  1071. reg [17:0] soundcounter;
  1072. always @(posedge vga_clk)
  1073. soundcounter <= soundcounter + 1;
  1074. wire [5:0] viN = soundcounter + 1;
  1075. wire [5:0] vi = soundcounter;
  1076. wire voice_wr = mem_wr & (mem_w_addr[14:11] == 5) & (mem_w_addr[10:8] == 3'b010);
  1077. wire voicefl_wr = voice_wr & (mem_w_addr[1:0] == 2'b00);
  1078. wire voicefh_wr = voice_wr & (mem_w_addr[1:0] == 2'b01);
  1079. wire voicela_wr = voice_wr & (mem_w_addr[1:0] == 2'b10);
  1080. wire voicera_wr = voice_wr & (mem_w_addr[1:0] == 2'b11);
  1081. wire [7:0] voicela_data;
  1082. wire [7:0] voicera_data;
  1083. wire [7:0] voicefl_data;
  1084. wire [7:0] voicefh_data;
  1085. wire [5:0] voice_addr = mem_addr[7:2];
  1086. ram64x8d voicefl(
  1087. .a(voice_addr),
  1088. .wclk(mem_clk),
  1089. .wea(voicefl_wr),
  1090. .ad(mem_data_wr),
  1091. .ao(voicefl_read),
  1092. .b(viN),
  1093. .bo(voicefl_data));
  1094. ram64x8d voicefh(
  1095. .a(voice_addr),
  1096. .wclk(mem_clk),
  1097. .wea(voicefh_wr),
  1098. .ad(mem_data_wr),
  1099. .ao(voicefh_read),
  1100. .b(viN),
  1101. .bo(voicefh_data));
  1102. ram64x8d voicela(
  1103. .a(voice_addr),
  1104. .wclk(mem_clk),
  1105. .wea(voicela_wr),
  1106. .ad(mem_data_wr),
  1107. .ao(voicela_read),
  1108. .b(viN),
  1109. .bo(voicela_data));
  1110. ram64x8d voicera(
  1111. .a(voice_addr),
  1112. .wclk(mem_clk),
  1113. .wea(voicera_wr),
  1114. .ad(mem_data_wr),
  1115. .ao(voicera_read),
  1116. .b(viN),
  1117. .bo(voicera_data));
  1118. assign screenshot_reset = mem_wr & (mem_w_addr[14:11] == 5) & (mem_w_addr[10:0] == 11'h01f);
  1119. always @(posedge mem_clk)
  1120. begin
  1121. if (mem_wr & mem_w_addr[14:11] == 5)
  1122. casex (mem_w_addr[10:0])
  1123. 11'h004: scrollx[7:0] <= mem_data_wr;
  1124. 11'h005: scrollx[8] <= mem_data_wr;
  1125. 11'h006: scrolly[7:0] <= mem_data_wr;
  1126. 11'h007: scrolly[8] <= mem_data_wr;
  1127. 11'h008: jkmode <= mem_data_wr;
  1128. 11'h009: j1_reset <= mem_data_wr;
  1129. 11'h00a: spr_disable <= mem_data_wr;
  1130. 11'h00b: spr_page <= mem_data_wr;
  1131. 11'h00c: pin2mode <= mem_data_wr;
  1132. 11'h00e: bg_color[7:0] <= mem_data_wr;
  1133. 11'h00f: bg_color[14:8] <= mem_data_wr;
  1134. 11'h010: sample_l[7:0] <= mem_data_wr;
  1135. 11'h011: sample_l[15:8] <= mem_data_wr;
  1136. 11'h012: sample_r[7:0] <= mem_data_wr;
  1137. 11'h013: sample_r[15:8] <= mem_data_wr;
  1138. 11'h014: modvoice <= mem_data_wr;
  1139. 11'h01e: screenshot_yy[7:0] <= mem_data_wr;
  1140. 11'h01f: begin screenshot_primed <= mem_data_wr[7];
  1141. screenshot_yy[8] <= mem_data_wr; end
  1142. endcase
  1143. end
  1144. /*
  1145. 0000-0fff Picture
  1146. 1000-1fff Character
  1147. 2000-27ff Character
  1148. 2800-2fff (Unused)
  1149. 3000-37ff Sprite values
  1150. 3800-3fff Sprite palette
  1151. 4000-7fff Sprite image
  1152. */
  1153. always @*
  1154. begin
  1155. case (mem_addr[14:11]) // 2K pages
  1156. 4'h0: mem_data_rd <= mem_data_rd0; // pic
  1157. 4'h1: mem_data_rd <= mem_data_rd0;
  1158. 4'h2: mem_data_rd <= mem_data_rd1; // chr
  1159. 4'h3: mem_data_rd <= mem_data_rd1;
  1160. 4'h4: mem_data_rd <= mem_data_rd2; // pal
  1161. 4'h5: mem_data_rd <= mem_data_rd_reg;
  1162. 4'h6: mem_data_rd <= mem_data_rd3; // sprval
  1163. 4'h7: mem_data_rd <= mem_data_rd4; // sprpal
  1164. 4'h8: mem_data_rd <= mem_data_rd5; // sprimg
  1165. 4'h9: mem_data_rd <= mem_data_rd5; // sprimg
  1166. 4'ha: mem_data_rd <= mem_data_rd5; // sprimg
  1167. 4'hb: mem_data_rd <= mem_data_rd5; // sprimg
  1168. 4'hc: mem_data_rd <= mem_data_rd5; // sprimg
  1169. 4'hd: mem_data_rd <= mem_data_rd5; // sprimg
  1170. 4'he: mem_data_rd <= mem_data_rd5; // sprimg
  1171. 4'hf: mem_data_rd <= mem_data_rd5; // sprimg
  1172. default: mem_data_rd <= 8'h97;
  1173. endcase
  1174. end
  1175. // Sprite memory
  1176. // Stage 1: scan for valid
  1177. reg [8:0] s1_count;
  1178. wire en_sprval = (mem_addr[14:11] == 4'b0110);
  1179. wire [31:0] sprval_data;
  1180. RAM_SPRVAL sprval(
  1181. .DIA(mem_data_wr),
  1182. .WEA(mem_wr),
  1183. .ENA(en_sprval),
  1184. .CLKA(mem_clk),
  1185. .ADDRA(mem_addr),
  1186. .DOA(mem_data_rd3),
  1187. .SSRA(0),
  1188. .DIB(0),
  1189. .WEB(0),
  1190. .ENB(1),
  1191. .CLKB(vga_clk),
  1192. .ADDRB({spr_page, s1_count[7:0]}),
  1193. .DOB(sprval_data),
  1194. .SSRB(0)
  1195. );
  1196. wire [9:0] sprpal_addr;
  1197. wire [15:0] sprpal_data;
  1198. wire en_sprpal = (mem_addr[14:11] == 4'b0111);
  1199. RAM_SPRPAL sprpal(
  1200. .DIA(mem_data_wr),
  1201. .WEA(mem_wr),
  1202. .ENA(en_sprpal),
  1203. .CLKA(mem_clk),
  1204. .ADDRA(mem_addr),
  1205. .DOA(mem_data_rd4),
  1206. .SSRA(0),
  1207. .DIB(0),
  1208. .WEB(0),
  1209. .ENB(1),
  1210. .CLKB(vga_clk),
  1211. .ADDRB(sprpal_addr),
  1212. .DOB(sprpal_data),
  1213. .SSRB(0)
  1214. );
  1215. wire [13:0] sprimg_readaddr;
  1216. wire [7:0] sprimg_data;
  1217. wire en_sprimg = (mem_addr[14] == 1'b1);
  1218. // ram16K_8_8 sprimg(
  1219. RAM_SPRIMG sprimg(
  1220. .dia(mem_data_wr),
  1221. .wea(mem_wr),
  1222. .ena(en_sprimg),
  1223. .clka(mem_clk),
  1224. .addra(mem_addr),
  1225. .doa(mem_data_rd5),
  1226. .ssra(0),
  1227. .dib(0),
  1228. .web(0),
  1229. .enb(1),
  1230. .clkb(vga_clk),
  1231. .addrb(sprimg_readaddr),
  1232. .dob(sprimg_data),
  1233. .ssrb(0)
  1234. );
  1235. // Stage 1: scan for valid
  1236. reg s1_consider; // Consider the sprval on the next cycle
  1237. wire s2_room; // Does s2 fifo have room for one entry?
  1238. always @(posedge vga_clk)
  1239. begin
  1240. if (comp_workcnt == 0) begin
  1241. s1_count <= 0;
  1242. s1_consider <= 0;
  1243. end else
  1244. if ((s1_count <= 255) & s2_room) begin
  1245. s1_count <= s1_count + 1;
  1246. s1_consider <= 1;
  1247. end else begin
  1248. s1_consider <= 0;
  1249. end
  1250. end
  1251. wire [31:0] s1_out = sprval_data;
  1252. wire [8:0] s1_y_offset = yy[9:1] - s1_out[24:16];
  1253. wire s1_visible = (spr_disable == 0) & (s1_y_offset[8:4] == 0);
  1254. wire s1_valid = s1_consider & s1_visible;
  1255. reg [8:0] s1_id;
  1256. always @(posedge vga_clk)
  1257. s1_id <= s1_count;
  1258. // Stage 2: fifo
  1259. wire [4:0] s2_fullness;
  1260. wire s3_read;
  1261. wire [40:0] s2_out;
  1262. fifo #(40) s2(.clk(vga_clk),
  1263. .wr(s1_valid), .datain({s1_id, s1_out}),
  1264. .rd(s3_read), .dataout(s2_out),
  1265. .fullness(s2_fullness));
  1266. assign s2_room = (s2_fullness < 14);
  1267. wire s2_valid = s2_fullness != 0;
  1268. // 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  1269. // [ image ] [ y ] [PAL] [ ROT ] [ x ]
  1270. /* Stage 3: read sprimg
  1271. consume s2_out on last cycle
  1272. out: s3_valid, s3_pal, s3_out, s3_compaddr
  1273. */
  1274. reg [4:0] s3_state;
  1275. reg [3:0] s3_pal;
  1276. reg [31:0] s3_in;
  1277. assign s3_read = (s3_state == 15);
  1278. always @(posedge vga_clk)
  1279. begin
  1280. if (comp_workcnt < 403)
  1281. s3_state <= 16;
  1282. else if (s3_state == 16) begin
  1283. if (s2_valid) begin
  1284. s3_state <= 0;
  1285. s3_in <= s2_out;
  1286. end
  1287. end else begin
  1288. s3_state <= s3_state + 1;
  1289. end
  1290. s3_pal <= s2_out[15:12];
  1291. end
  1292. wire [3:0] s3_yoffset = yy[4:1] - s2_out[19:16];
  1293. wire [3:0] s3_prev_state = (s3_state == 16) ? 0 : (s3_state + 1);
  1294. wire [3:0] readx = (s2_out[9] ? s3_yoffset : s3_prev_state) ^ {4{s2_out[10]}};
  1295. wire [3:0] ready = (s2_out[9] ? s3_prev_state : s3_yoffset) ^ {4{s2_out[11]}};
  1296. assign sprimg_readaddr = {s2_out[30:25], ready, readx};
  1297. wire [7:0] s3_out = sprimg_data;
  1298. wire [8:0] s3_compaddr = s2_out[8:0] + s3_state;
  1299. wire s3_valid = (s3_state != 16) & (s3_compaddr < 400);
  1300. reg [8:0] s3_id;
  1301. reg s3_jk;
  1302. always @(posedge vga_clk)
  1303. begin
  1304. s3_id <= s2_out[40:32];
  1305. s3_jk <= s2_out[31];
  1306. end
  1307. /* Stage 4: read sprpal
  1308. out: s4_valid, s4_out, s4_compaddr
  1309. */
  1310. reg [15:0] sprpal4;
  1311. reg [15:0] sprpal16;
  1312. assign sprpal_addr = {s3_pal[1:0], s3_out};
  1313. reg [8:0] s4_compaddr;
  1314. reg s4_valid;
  1315. reg [8:0] s4_id;
  1316. reg s4_jk;
  1317. wire [3:0] subfield4 = s3_pal[1] ? s3_out[7:4] : s3_out[3:0];
  1318. wire [1:0] subfield2 = s3_pal[2] ? (s3_pal[1] ? s3_out[7:6] : s3_out[5:4]) : (s3_pal[1] ? s3_out[3:2] : s3_out[1:0]);
  1319. assign palette4_addr = {s3_pal[0], subfield2};
  1320. assign palette16_addr = {s3_pal[0], subfield4};
  1321. always @(posedge vga_clk)
  1322. begin
  1323. s4_compaddr <= s3_compaddr;
  1324. s4_valid <= s3_valid;
  1325. s4_id <= s3_id;
  1326. s4_jk <= s3_jk;
  1327. sprpal4 <= palette4_data;
  1328. sprpal16 <= palette16_data;
  1329. end
  1330. wire [15:0] s4_out = s3_pal[3] ? sprpal4 : ((s3_pal[3:2] == 0) ? sprpal_data : sprpal16);
  1331. // Common signals for collision and composite
  1332. wire sprite_write = s4_valid & !s4_out[15]; // transparency
  1333. // Collision detect
  1334. // Have 400x9 occupancy buffer. If NEW overwrites a fragment OLD
  1335. // (and their groups differ) write OLD to coll[NEW].
  1336. // Reset coll to FF at start of frame.
  1337. // Reset occ to FF at start of line, since sprites drawn 0->ff,
  1338. // ff is impossible and means empty.
  1339. wire coll_scrub = (yy == 0) & (comp_workcnt < 256);
  1340. wire [8:0] occ_addr = comp_workcnt_lt_400 ? comp_workcnt : s4_compaddr;
  1341. wire [8:0] occ_d = comp_workcnt_lt_400 ? 9'hff : {s4_jk, s4_id[7:0]};
  1342. wire [8:0] oldocc;
  1343. wire occ_w = comp_workcnt_lt_400 | sprite_write;
  1344. ram400x9s occ(.o(oldocc), .a(occ_addr), .d(occ_d), .wclk(vga_clk), .we(occ_w));
  1345. assign coll_d = coll_scrub ? 8'hff : oldocc[7:0];
  1346. assign coll_w_addr = coll_scrub ? comp_workcnt : s4_id[7:0];
  1347. // old contents 0xff, never write
  1348. // jkmode=1 and JK's differ, allow write
  1349. wire overwriting = (oldocc[7:0] != 8'hff);
  1350. wire jkpass = (jkmode == 0) | (oldocc[8] ^ s4_jk);
  1351. assign coll_we = coll_scrub | ((403 <= comp_workcnt) & sprite_write & overwriting & jkpass);
  1352. // Composite
  1353. wire comp_read = yy[1]; // which block is reading
  1354. wire [8:0] comp_scanout = xx[9:1];
  1355. wire [8:0] comp_write = (comp_workcnt < 403) ? (comp_workcnt - 3) : s4_compaddr;
  1356. wire comp_part1 = (3 <= comp_workcnt) & (comp_workcnt < 403);
  1357. `ifdef NELLY
  1358. wire [14:0] comp_out0;
  1359. wire [14:0] comp_out1;
  1360. RAMB16_S18_S18 composer(
  1361. .DIPA(0),
  1362. .DIA(comp_part1 ? char_final : s4_out),
  1363. .WEA(comp_read == 1 & (comp_part1 | sprite_write)),
  1364. .ENA(1),
  1365. .CLKA(vga_clk),
  1366. .ADDRA({1'b0, (comp_read == 0) ? comp_scanout : comp_write[8:0]}),
  1367. .DOA(comp_out0),
  1368. .SSRA(0),
  1369. .DIPB(0),
  1370. .DIB(comp_part1 ? char_final : s4_out),
  1371. .WEB(comp_read == 0 & (comp_part1 | sprite_write)),
  1372. .ENB(1),
  1373. .CLKB(vga_clk),
  1374. .ADDRB({1'b1, (comp_read == 1) ? comp_scanout : comp_write[8:0]}),
  1375. .DOB(comp_out1),
  1376. .SSRB(0)
  1377. );
  1378. wire [14:0] comp_out = comp_read ? comp_out1 : comp_out0;
  1379. `else
  1380. wire ss = screenshot_primed & screenshot_done; // screenshot readout mode
  1381. wire [15:0] screenshot_rdHL;
  1382. wire [14:0] comp_out;
  1383. // Port A is the write, or read when screenshot is ready
  1384. // Port B is scanout
  1385. RAMB16_S18_S18
  1386. composer(
  1387. .DIPA(0),
  1388. .DIA(comp_part1 ? char_final : s4_out),
  1389. .WEA(!ss & (comp_part1 | sprite_write)),
  1390. .ENA(1),
  1391. .CLKA(vga_clk),
  1392. .ADDRA(ss ? {screenshot_yy[0], mem_r_addr[9:1]} : {comp_read, comp_write[8:0]}),
  1393. .DOA(screenshot_rdHL),
  1394. .SSRA(0),
  1395. .DIPB(0),
  1396. .DIB(0),
  1397. .WEB(0),
  1398. .ENB(1),
  1399. .CLKB(vga_clk),
  1400. .ADDRB({!comp_read, comp_scanout}),
  1401. .DOB(comp_out),
  1402. .SSRB(0)
  1403. );
  1404. assign screenshot_rd = mem_r_addr[0] ? screenshot_rdHL[15:8] : screenshot_rdHL[7:0];
  1405. `endif
  1406. assign {bg_r,bg_g,bg_b} = comp_out;
  1407. // Figure out from above signals when composite completes
  1408. // by detecting pipeline idle
  1409. wire composite_complete = (comp_workcnt > 403) & (s1_count == 256) & !s1_consider & !s2_valid & (s3_state == 16) & !s4_valid;
  1410. // Signal generation
  1411. wire [16:0] lfsr;
  1412. lfsre lfsr0(
  1413. .clk(vga_clk),
  1414. .lfsr(lfsr));
  1415. wire [1:0] dith;
  1416. // 0 2
  1417. // 3 1
  1418. assign dith = {(xx[0]^yy[0]), yy[0]};
  1419. wire [5:0] dith_r = (bg_r + dith);
  1420. wire [5:0] dith_g = (bg_g + dith);
  1421. wire [5:0] dith_b = (bg_b + dith);
  1422. wire [2:0] f_r = {3{dith_r[5]}} | dith_r[4:2];
  1423. wire [2:0] f_g = {3{dith_g[5]}} | dith_g[4:2];
  1424. wire [2:0] f_b = {3{dith_b[5]}} | dith_b[4:2];
  1425. wire [2:0] ccc = { charout[1], charout[0], charout[0] };
  1426. assign vga_red = vga_active ? f_r : 0;
  1427. assign vga_green = vga_active ? f_g : 0;
  1428. assign vga_blue = vga_active ? f_b : 0;
  1429. assign vga_hsync_n = ~vga_HS;
  1430. assign vga_vsync_n = ~vga_VS;
  1431. /*
  1432. An 18-bit counter, multiplied by the frequency gives a single bit
  1433. pulse that advances the voice's wave counter.
  1434. Frequency of 4 means 1Hz, 16385 means 4095.75Hz.
  1435. 18-bit counter increments every 1/(2**18), or 262144 Hz.
  1436. */
  1437. `define MASTERFREQ (1 << 22)
  1438. reg [27:0] d;
  1439. wire [27:0] dInc = d[27] ? (`MASTERFREQ) : (`MASTERFREQ - 50000000);
  1440. wire [27:0] dN = d + dInc;
  1441. reg [16:0] soundmaster; // This increments at MASTERFREQ Hz
  1442. always @(posedge vga_clk)
  1443. begin
  1444. d = dN;
  1445. // clock B tick whenever d[27] is zero
  1446. if (dN[27] == 0) begin
  1447. soundmaster <= soundmaster + 1;
  1448. end
  1449. end
  1450. wire [6:0] hsin;
  1451. wire [6:0] wavecounter;
  1452. wire [6:0] note = wavecounter[6:0];
  1453. `ifdef YES
  1454. RAM64X1S #(.INIT(64'b0000000000110101100010001111010010010111100010001101011000000000) /* 0 */
  1455. ) sin0(.O(hsin[0]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]), .D(0), .WCLK(vga_clk), .WE(0));
  1456. RAM64X1S #(.INIT(64'b0101010101101100011100010101001111100101010001110001101101010101) /* 1 */
  1457. ) sin1(.O(hsin[1]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]), .D(0), .WCLK(vga_clk), .WE(0));
  1458. RAM64X1S #(.INIT(64'b0110011001001001010101001100111111111001100101010100100100110011) /* 2 */
  1459. ) sin2(.O(hsin[2]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]), .D(0), .WCLK(vga_clk), .WE(0));
  1460. RAM64X1S #(.INIT(64'b0010110100100100110011000011111111111110000110011001001001011010) /* 3 */
  1461. ) sin3(.O(hsin[3]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]), .D(0), .WCLK(vga_clk), .WE(0));
  1462. RAM64X1S #(.INIT(64'b0001110011100011110000111111111111111111111000011110001110011100) /* 4 */
  1463. ) sin4(.O(hsin[4]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]), .D(0), .WCLK(vga_clk), .WE(0));
  1464. RAM64X1S #(.INIT(64'b0000001111100000001111111111111111111111111111100000001111100000) /* 5 */
  1465. ) sin5(.O(hsin[5]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]), .D(0), .WCLK(vga_clk), .WE(0));
  1466. RAM64X1S #(.INIT(64'b0000000000011111111111111111111111111111111111111111110000000000) /* 6 */
  1467. ) sin6(.O(hsin[6]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]), .D(0), .WCLK(vga_clk), .WE(0));
  1468. `else
  1469. ROM64X1 #(.INIT(64'b0000000000110101100010001111010010010111100010001101011000000000) /* 0 */) sin0(.O(hsin[0]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]));
  1470. ROM64X1 #(.INIT(64'b0101010101101100011100010101001111100101010001110001101101010101) /* 1 */) sin1(.O(hsin[1]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]));
  1471. ROM64X1 #(.INIT(64'b0110011001001001010101001100111111111001100101010100100100110011) /* 2 */) sin2(.O(hsin[2]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]));
  1472. ROM64X1 #(.INIT(64'b0010110100100100110011000011111111111110000110011001001001011010) /* 3 */) sin3(.O(hsin[3]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]));
  1473. ROM64X1 #(.INIT(64'b0001110011100011110000111111111111111111111000011110001110011100) /* 4 */) sin4(.O(hsin[4]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]));
  1474. ROM64X1 #(.INIT(64'b0000001111100000001111111111111111111111111111100000001111100000) /* 5 */) sin5(.O(hsin[5]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]));
  1475. ROM64X1 #(.INIT(64'b0000000000011111111111111111111111111111111111111111110000000000) /* 6 */) sin6(.O(hsin[6]), .A0(note[0]), .A1(note[1]), .A2(note[2]), .A3(note[3]), .A4(note[4]), .A5(note[5]));
  1476. `endif
  1477. wire signed [7:0] sin = note[6] ? (8'h00 - hsin) : hsin;
  1478. wire voiceshape = voicefh_data[7];
  1479. wire [14:0] voicefreq = {voicefh_data[6:0], voicefl_data};
  1480. wire [35:0] derived = {1'b0, soundmaster} * voicefreq;
  1481. wire highfreq = voicefreq[14];
  1482. wire newpulse = highfreq ? derived[18] : derived[17]; // pulse is a square wave frequency 64*f
  1483. wire oldpulse;
  1484. wire [6:0] nextwavecounter = voiceshape ? lfsr : (wavecounter + (highfreq ? 2 : 1));
  1485. wire [6:0] _wavecounter = (newpulse != oldpulse) ? nextwavecounter : wavecounter;
  1486. `ifdef NELLY
  1487. ram64x8s voicestate(
  1488. .a(viN),
  1489. .we(1),
  1490. .wclk(vga_clk),
  1491. .d({_wavecounter, newpulse}),
  1492. .o({wavecounter, oldpulse}));
  1493. `else
  1494. wire [8:0] vsi = {_wavecounter, newpulse};
  1495. wire [8:0] vso;
  1496. ring64 vs0(.clk(vga_clk), .i(vsi[0]), .o(vso[0]));
  1497. ring64 vs1(.clk(vga_clk), .i(vsi[1]), .o(vso[1]));
  1498. ring64 vs2(.clk(vga_clk), .i(vsi[2]), .o(vso[2]));
  1499. ring64 vs3(.clk(vga_clk), .i(vsi[3]), .o(vso[3]));
  1500. ring64 vs4(.clk(vga_clk), .i(vsi[4]), .o(vso[4]));
  1501. ring64 vs5(.clk(vga_clk), .i(vsi[5]), .o(vso[5]));
  1502. ring64 vs6(.clk(vga_clk), .i(vsi[6]), .o(vso[6]));
  1503. ring64 vs7(.clk(vga_clk), .i(vsi[7]), .o(vso[7]));
  1504. assign wavecounter = vso[7:1];
  1505. assign oldpulse = vso[0];
  1506. `endif
  1507. wire signed [8:0] lamp = voicela_data;
  1508. wire signed [8:0] ramp = voicera_data;
  1509. reg signed [35:0] lmodulated;
  1510. reg signed [35:0] rmodulated;
  1511. always @(posedge vga_clk)
  1512. begin
  1513. lmodulated = lamp * sin;
  1514. rmodulated = ramp * sin;
  1515. end
  1516. // Have lmodulated and rmodulated
  1517. reg signed [15:0] lacc;
  1518. reg signed [15:0] racc;
  1519. wire signed [15:0] lsum = lacc + lmodulated[15:0];
  1520. wire signed [15:0] rsum = racc + rmodulated[15:0];
  1521. wire signed [31:0] lprod = lacc * lmodulated;
  1522. wire signed [31:0] rprod = racc * rmodulated;
  1523. wire zeroacc = (vi == 63);
  1524. wire [15:0] _lacc = zeroacc ? sample_l : ((vi == modvoice) ? lprod[30:15] : lsum);
  1525. wire [15:0] _racc = zeroacc ? sample_r : ((vi == modvoice) ? rprod[30:15] : rsum);
  1526. reg signed [12:0] lvalue;
  1527. reg signed [12:0] rvalue;
  1528. always @(posedge vga_clk)
  1529. begin
  1530. if (vi == 63) begin
  1531. lvalue <= lsum[15:3] /* + sample_l + 32768 */;
  1532. rvalue <= rsum[15:3] /* + sample_r + 32768 */;
  1533. end
  1534. lacc <= _lacc;
  1535. racc <= _racc;
  1536. end
  1537. wire signed [7:0] dither = soundcounter;
  1538. // wire [15:0] dither = {soundcounter[0],
  1539. // soundcounter[1],
  1540. // soundcounter[2],
  1541. // soundcounter[3],
  1542. // soundcounter[4],
  1543. // soundcounter[5],
  1544. // soundcounter[6],
  1545. // soundcounter[7],
  1546. // soundcounter[8],
  1547. // soundcounter[9],
  1548. // soundcounter[10],
  1549. // soundcounter[11],
  1550. // soundcounter[12],
  1551. // soundcounter[13],
  1552. // soundcounter[14],
  1553. // soundcounter[15]
  1554. // };
  1555. `ifdef NELLY
  1556. wire lau_out = lvalue >= dither;
  1557. wire rau_out = rvalue >= dither;
  1558. assign AUDIOL = lau_out;
  1559. assign AUDIOR = rau_out;
  1560. `else
  1561. wire [12:0] ulvalue = lvalue ^ 4096;
  1562. wire [12:0] urvalue = rvalue ^ 4096;
  1563. dac ldac(AUDIOL, ulvalue, vga_clk, 0);
  1564. dac rdac(AUDIOR, urvalue, vga_clk, 0);
  1565. `endif
  1566. reg [2:0] busyhh;
  1567. always @(posedge vga_clk) busyhh = { busyhh[1:0], host_busy };
  1568. // J1 Peripherals
  1569. reg [7:0] icap_i; // ICAP in
  1570. reg icap_write;
  1571. reg icap_ce;
  1572. reg icap_clk;
  1573. wire [7:0] icap_o; // ICAP out
  1574. wire icap_busy;
  1575. reg j1_p2_dir = 1; // pin defaults to input
  1576. reg j1_p2_o = 1;
  1577. ICAP_SPARTAN3A ICAP_SPARTAN3A_inst (
  1578. .O(icap_o),
  1579. .BUSY(icap_busy),
  1580. .I(icap_i),
  1581. .WRITE(icap_write),
  1582. .CE(icap_ce),
  1583. .CLK(icap_clk));
  1584. reg dna_read;
  1585. reg dna_shift;
  1586. reg dna_clk;
  1587. wire dna_dout;
  1588. DNA_PORT dna(
  1589. .DOUT(dna_dout),
  1590. .DIN(0),
  1591. .READ(dna_read),
  1592. .SHIFT(dna_shift),
  1593. .CLK(dna_clk));
  1594. wire j1_wr;
  1595. reg [8:0] YYLINE;
  1596. wire [9:0] yyline = (CounterY + 4 - (35 + 6 + 21 + 1));
  1597. always @(posedge vga_clk)
  1598. begin
  1599. // if (xx == 400)
  1600. if (composite_complete)
  1601. YYLINE = yyline[9:1];
  1602. end
  1603. reg [15:0] freqhz = 8000;
  1604. reg [7:0] freqtick;
  1605. reg [26:0] freqd;
  1606. wire [26:0] freqdN = freqd + freqhz - (freqd[26] ? 0 : 50000000);
  1607. always @(posedge vga_clk)
  1608. begin
  1609. freqd = freqdN;
  1610. if (freqd[26] == 0)
  1611. freqtick = freqtick + 1;
  1612. end
  1613. reg [15:0] local_j1_read;
  1614. always @*
  1615. begin
  1616. case ({j1_mem_addr[4:1], 1'b0})
  1617. 5'h00: local_j1_read <= YYLINE;
  1618. 5'h02: local_j1_read <= icap_o;
  1619. 5'h0c: local_j1_read <= freqtick;
  1620. 5'h0e: local_j1_read <= AUX;
  1621. 5'h12: local_j1_read <= lfsr;
  1622. 5'h14: local_j1_read <= soundcounter;
  1623. 5'h16: local_j1_read <= flashMISO;
  1624. 5'h18: local_j1_read <= dna_dout;
  1625. // default: local_j1_read <= 16'hffff;
  1626. endcase
  1627. end
  1628. wire [0:7] j1_mem_dout_be = j1_mem_dout;
  1629. reg j1_flashMOSI;
  1630. reg j1_flashSCK;
  1631. reg j1_flashSSEL;
  1632. always @(posedge vga_clk)
  1633. begin
  1634. if (j1_wr & (j1_mem_addr[15] == 1))
  1635. case ({j1_mem_addr[4:1], 1'b0})
  1636. // 5'h06: icap_i <= j1_mem_dout;
  1637. // 5'h08: icap_write <= j1_mem_dout;
  1638. // 5'h0a: icap_ce <= j1_mem_dout;
  1639. // 5'h0c: icap_clk <= j1_mem_dout;
  1640. 5'h06: {icap_write,icap_ce,icap_clk,icap_i} <= j1_mem_dout;
  1641. 5'h08: {dna_read, dna_shift, dna_clk} <= j1_mem_dout;
  1642. 5'h0a: freqhz <= j1_mem_dout;
  1643. 5'h0e: j1_p2_o <= j1_mem_dout;
  1644. 5'h10: j1_p2_dir <= j1_mem_dout;
  1645. 5'h18: j1_flashMOSI <= j1_mem_dout;
  1646. 5'h1a: j1_flashSCK <= j1_mem_dout;
  1647. 5'h1c: j1_flashSSEL <= j1_mem_dout;
  1648. endcase
  1649. end
  1650. assign j1_mem_wr = j1_wr & (j1_mem_addr[15] == 0);
  1651. j0 j(.sys_clk_i(vga_clk),
  1652. .sys_rst_i(j1_reset),
  1653. .insn(j1_insn),
  1654. .insn_addr(j1_insn_addr),
  1655. .mem_wr(j1_wr),
  1656. .mem_addr(j1_mem_addr),
  1657. .mem_dout(j1_mem_dout),
  1658. .mem_din(j1_mem_addr[15] ? local_j1_read : mem_data_rd),
  1659. .pause(host_busy | (busyhh != 0))
  1660. );
  1661. // 0x2b00: j1 insn RAM
  1662. wire jinsn_wr = (mem_wr & (mem_w_addr[14:8] == 6'h2b));
  1663. RAM_CODEL jinsnl(.b(j1_insn_addr), .bo(j1_insn[7:0]),
  1664. .a(mem_addr[7:1]),
  1665. .wclk(vga_clk),
  1666. .wea((mem_w_addr[0] == 0) & jinsn_wr),
  1667. .ad(mem_data_wr),
  1668. .ao(j1insnl_read));
  1669. RAM_CODEH jinsnh(.b(j1_insn_addr), .bo(j1_insn[15:8]),
  1670. .a(mem_addr[7:1]),
  1671. .wclk(vga_clk),
  1672. .wea((mem_w_addr[0] == 1) & jinsn_wr),
  1673. .ad(mem_data_wr),
  1674. .ao(j1insnh_read));
  1675. assign flashMOSI = pin2j ? j1_flashMOSI : MOSI;
  1676. assign flashSCK = pin2j ? j1_flashSCK : SCK;
  1677. assign flashSSEL = pin2f ? AUX : (pin2j ? j1_flashSSEL : 1);
  1678. assign AUX = (pin2j & (j1_p2_dir == 0)) ? j1_p2_o : 1'bz;
  1679. endmodule // top