fifo.v 635 B

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  1. module fifo ( clk, datain, wr, dataout, rd, fullness);
  2. parameter WIDTH = 1;
  3. input clk;
  4. input [WIDTH-1:0] datain;
  5. input wr;
  6. output [WIDTH-1:0] dataout;
  7. input rd;
  8. output reg [4:0] fullness;
  9. always @(posedge clk)
  10. begin
  11. fullness <= (fullness + wr - rd);
  12. end
  13. wire [3:0] readaddr = (fullness - 1);
  14. genvar i;
  15. generate
  16. for (i = 0; i < WIDTH; i=i+1) begin : srl16
  17. SRL16E fifo16(
  18. .CLK(clk),
  19. .CE(wr),
  20. .D(datain[i]),
  21. .A0(readaddr[0]),
  22. .A1(readaddr[1]),
  23. .A2(readaddr[2]),
  24. .A3(readaddr[3]),
  25. .Q(dataout[i]));
  26. end
  27. endgenerate
  28. endmodule