ck_div.vhd 1.1 KB

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  1. module ck_div(
  2. input ck_in,
  3. output ck_out,
  4. input sys_rst_i
  5. //output locked;
  6. );
  7. parameter DIV_BY = 1;
  8. parameter MULT_BY = 1;
  9. wire ck_fb;
  10. //DCM #(
  11. // .CLKDV_DIVIDE(DIV_BY),
  12. // .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
  13. // .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
  14. // .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
  15. //) DCM_inst (
  16. // .CLK0(ck_fb),
  17. // .CLKDV(ck_out),
  18. // .CLKFB(ck_fb), // DCM clock feedback
  19. // .CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
  20. // .RST(0)
  21. //);
  22. DCM #(
  23. .CLKFX_MULTIPLY(MULT_BY),
  24. .CLKFX_DIVIDE(DIV_BY),
  25. .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
  26. .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
  27. .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
  28. ) DCM_inst (
  29. .CLK0(ck_fb),
  30. .CLKFX(ck_out),
  31. .CLKFB(ck_fb), // DCM clock feedback
  32. .CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
  33. .RST(0)
  34. );
  35. //BUFG BUFG_inst(.I(ck_int), .O(ck_out));
  36. endmodule