j1.ucf 16 KB

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  1. #####################################################
  2. #
  3. # XSA-3S1000 Board FPGA pin assignment constraints
  4. #
  5. #####################################################
  6. #
  7. # Clocks
  8. #
  9. net CLKA loc=T9 | IOSTANDARD = LVCMOS33 ; # 100MHz
  10. #net CLKB loc=P8 | IOSTANDARD = LVCMOS33 ; # 50MHz
  11. #net CLKC loc=R9 | IOSTANDARD = LVCMOS33 ; # ??Mhz
  12. #
  13. # Push button switches
  14. #
  15. #NET SW1_3_N loc=K2 | IOSTANDARD = LVCMOS33 ; # Flash Block select
  16. #NET SW1_4_N loc=J4 | IOSTANDARD = LVCMOS33 ; # Flash Block
  17. #NET SW2_N loc=E11 | IOSTANDARD = LVCMOS33 ; # active-low pushbutton
  18. #NET SW3_N loc=A13 | IOSTANDARD = LVCMOS33 ; # active-low pushbutton
  19. #
  20. # PS/2 Keyboard
  21. #
  22. net PS2_CLK loc=B16 | IOSTANDARD = LVCMOS33 ;
  23. net PS2_DAT loc=E13 | IOSTANDARD = LVCMOS33 ;
  24. #
  25. # VGA Outputs
  26. #
  27. NET VGA_BLUE<0> LOC=C9 | IOSTANDARD = LVCMOS33 ;
  28. NET VGA_BLUE<1> LOC=E7 | IOSTANDARD = LVCMOS33 ;
  29. NET VGA_BLUE<2> LOC=D5 | IOSTANDARD = LVCMOS33 ;
  30. NET VGA_GREEN<0> LOC=A8 | IOSTANDARD = LVCMOS33 ;
  31. NET VGA_GREEN<1> LOC=A5 | IOSTANDARD = LVCMOS33 ;
  32. NET VGA_GREEN<2> LOC=C3 | IOSTANDARD = LVCMOS33 ;
  33. NET VGA_RED<0> LOC=C8 | IOSTANDARD = LVCMOS33 ;
  34. NET VGA_RED<1> LOC=D6 | IOSTANDARD = LVCMOS33 ;
  35. NET VGA_RED<2> LOC=B1 | IOSTANDARD = LVCMOS33 ;
  36. NET VGA_HSYNC_N LOC=B7 | IOSTANDARD = LVCMOS33 ;
  37. NET VGA_VSYNC_N LOC=D8 | IOSTANDARD = LVCMOS33 ;
  38. #
  39. # Manually assign locations for the DCMs along the bottom of the FPGA
  40. # because PAR sometimes places them in opposing corners and that ruins the clocks.
  41. #
  42. #INST "u1/gen_dlls.dllint" LOC="DCM_X0Y0";
  43. #INST "u1/gen_dlls.dllext" LOC="DCM_X1Y0";
  44. # Manually assign locations for the DCMs along the bottom of the FPGA
  45. # because PAR sometimes places them in opposing corners and that ruins the clocks.
  46. #INST "u2_dllint" LOC="DCM_X0Y0";
  47. #INST "u2_dllext" LOC="DCM_X1Y0";
  48. #
  49. # SDRAM memory pin assignments
  50. #
  51. #net SDRAM_clkfb loc=N8 | IOSTANDARD = LVCMOS33 ; # feedback SDRAM clock after PCB delays
  52. #net SDRAM_clkout loc=E10 | IOSTANDARD = LVCMOS33 ; # clock to SDRAM
  53. #net SDRAM_CKE loc=D7 | IOSTANDARD = LVCMOS33 ; # SDRAM clock enable
  54. #net SDRAM_CS_N loc=B8 | IOSTANDARD = LVCMOS33 ; # SDRAM chip-select
  55. #net SDRAM_RAS_N loc=A9 | IOSTANDARD = LVCMOS33 ;
  56. #net SDRAM_CAS_N loc=A10 | IOSTANDARD = LVCMOS33 ;
  57. #net SDRAM_WE_N loc=B10 | IOSTANDARD = LVCMOS33 ;
  58. #net SDRAM_DQMH loc=D9 | IOSTANDARD = LVCMOS33 ;
  59. #net SDRAM_DQML loc=C10 | IOSTANDARD = LVCMOS33 ;
  60. #net SDRAM_A<0> loc=B5 | IOSTANDARD = LVCMOS33 ;
  61. #net SDRAM_A<1> loc=A4 | IOSTANDARD = LVCMOS33 ;
  62. #net SDRAM_A<2> loc=B4 | IOSTANDARD = LVCMOS33 ;
  63. #net SDRAM_A<3> loc=E6 | IOSTANDARD = LVCMOS33 ;
  64. #net SDRAM_A<4> loc=E3 | IOSTANDARD = LVCMOS33 ;
  65. #net SDRAM_A<5> loc=C1 | IOSTANDARD = LVCMOS33 ;
  66. #net SDRAM_A<6> loc=E4 | IOSTANDARD = LVCMOS33 ;
  67. #net SDRAM_A<7> loc=D3 | IOSTANDARD = LVCMOS33 ;
  68. #net SDRAM_A<8> loc=C2 | IOSTANDARD = LVCMOS33 ;
  69. #net SDRAM_A<9> loc=A3 | IOSTANDARD = LVCMOS33 ;
  70. #net SDRAM_A<10> loc=B6 | IOSTANDARD = LVCMOS33 ;
  71. #net SDRAM_A<11> loc=C5 | IOSTANDARD = LVCMOS33 ;
  72. #net SDRAM_A<12> loc=C6 | IOSTANDARD = LVCMOS33 ;
  73. #net SDRAM_D<0> loc=C15 | IOSTANDARD = LVCMOS33 ;
  74. #net SDRAM_D<1> loc=D12 | IOSTANDARD = LVCMOS33 ;
  75. #net SDRAM_D<2> loc=A14 | IOSTANDARD = LVCMOS33 ;
  76. #net SDRAM_D<3> loc=B13 | IOSTANDARD = LVCMOS33 ;
  77. #net SDRAM_D<4> loc=D11 | IOSTANDARD = LVCMOS33 ;
  78. #net SDRAM_D<5> loc=A12 | IOSTANDARD = LVCMOS33 ;
  79. #net SDRAM_D<6> loc=C11 | IOSTANDARD = LVCMOS33 ;
  80. #net SDRAM_D<7> loc=D10 | IOSTANDARD = LVCMOS33 ;
  81. #net SDRAM_D<8> loc=B11 | IOSTANDARD = LVCMOS33 ;
  82. #net SDRAM_D<9> loc=B12 | IOSTANDARD = LVCMOS33 ;
  83. #net SDRAM_D<10> loc=C12 | IOSTANDARD = LVCMOS33 ;
  84. #net SDRAM_D<11> loc=B14 | IOSTANDARD = LVCMOS33 ;
  85. #net SDRAM_D<12> loc=D14 | IOSTANDARD = LVCMOS33 ;
  86. #net SDRAM_D<13> loc=C16 | IOSTANDARD = LVCMOS33 ;
  87. #net SDRAM_D<14> loc=F12 | IOSTANDARD = LVCMOS33 ;
  88. #net SDRAM_D<15> loc=F13 | IOSTANDARD = LVCMOS33 ;
  89. #net SDRAM_BA<0> loc=A7 | IOSTANDARD = LVCMOS33 ;
  90. #net SDRAM_BA<1> loc=C7 | IOSTANDARD = LVCMOS33 ;
  91. #
  92. # Flash memory interface
  93. net FLASH_A<0> LOC=N5 | IOSTANDARD = LVCMOS33 ;
  94. net FLASH_A<1> LOC=K14 | IOSTANDARD = LVCMOS33 ;
  95. net FLASH_A<2> LOC=K13 | IOSTANDARD = LVCMOS33 ;
  96. net FLASH_A<3> LOC=K12 | IOSTANDARD = LVCMOS33 ;
  97. net FLASH_A<4> LOC=L14 | IOSTANDARD = LVCMOS33 ;
  98. net FLASH_A<5> LOC=M16 | IOSTANDARD = LVCMOS33 ;
  99. net FLASH_A<6> LOC=L13 | IOSTANDARD = LVCMOS33 ;
  100. net FLASH_A<7> LOC=N16 | IOSTANDARD = LVCMOS33 ;
  101. net FLASH_A<8> LOC=N14 | IOSTANDARD = LVCMOS33 ;
  102. net FLASH_A<9> LOC=P15 | IOSTANDARD = LVCMOS33 ;
  103. net FLASH_A<10> LOC=R16 | IOSTANDARD = LVCMOS33 ;
  104. net FLASH_A<11> LOC=P14 | IOSTANDARD = LVCMOS33 ;
  105. net FLASH_A<12> LOC=P13 | IOSTANDARD = LVCMOS33 ;
  106. net FLASH_A<13> LOC=N12 | IOSTANDARD = LVCMOS33 ;
  107. net FLASH_A<14> LOC=T14 | IOSTANDARD = LVCMOS33 ;
  108. net FLASH_A<15> LOC=R13 | IOSTANDARD = LVCMOS33 ;
  109. net FLASH_A<16> LOC=N10 | IOSTANDARD = LVCMOS33 ;
  110. net FLASH_A<17> LOC=M14 | IOSTANDARD = LVCMOS33 ;
  111. net FLASH_A<18> LOC=K3 | IOSTANDARD = LVCMOS33 ;
  112. net FLASH_A<19> LOC=K4 | IOSTANDARD = LVCMOS33 ;
  113. net FLASH_D<0> LOC=M11 | IOSTANDARD = LVCMOS33 ;
  114. net FLASH_D<1> LOC=N11 | IOSTANDARD = LVCMOS33 ;
  115. net FLASH_D<2> LOC=P10 | IOSTANDARD = LVCMOS33 ;
  116. net FLASH_D<3> LOC=R10 | IOSTANDARD = LVCMOS33 ;
  117. net FLASH_D<4> LOC=T7 | IOSTANDARD = LVCMOS33 ;
  118. net FLASH_D<5> LOC=R7 | IOSTANDARD = LVCMOS33 ;
  119. net FLASH_D<6> LOC=N6 | IOSTANDARD = LVCMOS33 ;
  120. net FLASH_D<7> LOC=M6 | IOSTANDARD = LVCMOS33 ;
  121. net FLASH_D<8> LOC=T4 | IOSTANDARD = LVCMOS33 ;
  122. net FLASH_D<9> LOC=R5 | IOSTANDARD = LVCMOS33 ;
  123. net FLASH_D<10> LOC=T5 | IOSTANDARD = LVCMOS33 ;
  124. net FLASH_D<11> LOC=P6 | IOSTANDARD = LVCMOS33 ;
  125. net FLASH_D<12> LOC=M7 | IOSTANDARD = LVCMOS33 ;
  126. net FLASH_D<13> LOC=R6 | IOSTANDARD = LVCMOS33 ;
  127. net FLASH_D<14> LOC=N7 | IOSTANDARD = LVCMOS33 ;
  128. net FLASH_D<15> LOC=P7 | IOSTANDARD = LVCMOS33 ;
  129. net FLASH_CE_N LOC=R4 | IOSTANDARD = LVCMOS33 ;
  130. net FLASH_OE_N LOC=P5 | IOSTANDARD = LVCMOS33 ;
  131. net FLASH_WE_N LOC=M13 | IOSTANDARD = LVCMOS33 ;
  132. net FLASH_BYTE_N LOC=T8 | IOSTANDARD = LVCMOS33 ;
  133. net FLASH_RDY LOC=L12 | IOSTANDARD = LVCMOS33 ;
  134. net FLASH_RST_N LOC=P16 | IOSTANDARD = LVCMOS33 ;
  135. # FPGA Programming interface
  136. #
  137. #net FPGA_D<0> LOC=M11 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D0, S1, LED_C
  138. #net FPGA_D<1> LOC=N11 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D1, S7, LED_DP
  139. #net FPGA_D<2> LOC=P10 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D2, S4, LED_B
  140. #net FPGA_D<3> LOC=R10 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D3, S6, LED_A
  141. #net FPGA_D<4> LOC=T7 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D4, S5, LED_F
  142. #net FPGA_D<5> LOC=R7 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D5, S3, LED_G
  143. #net FPGA_D<6> LOC=N6 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D6, S2, LED_E
  144. #net FPGA_D<7> LOC=M6 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D7, S0, LED_D
  145. #net FPGA_CCLK LOC=T15 | IOSTANDARD = LVCMOS33 ;
  146. #net FPGA_DONE LOC=R14 | IOSTANDARD = LVCMOS33 ;
  147. #net FPGA_INIT_N LOC=N9 | IOSTANDARD = LVCMOS33 ;
  148. #net FPGA_PROG_N LOC=B3 | IOSTANDARD = LVCMOS33 ;
  149. #net FPGA_TCK LOC=C14 | IOSTANDARD = LVCMOS33 ;
  150. #net FPGA_TDI LOC=A2 | IOSTANDARD = LVCMOS33 ;
  151. #net FPGA_TDI_CSN LOC=R3 | IOSTANDARD = LVCMOS33 ;
  152. #net FPGA_TDO LOC=A15 | IOSTANDARD = LVCMOS33 ;
  153. #net FPGA_TDO_WRN LOC=T3 | IOSTANDARD = LVCMOS33 ;
  154. #net FPGA_TMS LOC=C13 | IOSTANDARD = LVCMOS33 ;
  155. #net FPGA_TMS_BSY LOC=P9 | IOSTANDARD = LVCMOS33 ;
  156. #
  157. # Status LED
  158. #
  159. #net S<0> loc=M6 | IOSTANDARD = LVCMOS33 ; # FPGA_D7, LED_D
  160. #net S<1> loc=M11 | IOSTANDARD = LVCMOS33 ; # FPGA_D0, LED_C
  161. #net S<2> loc=N6 | IOSTANDARD = LVCMOS33 ; # FPGA_D6, LED_E
  162. #net S<3> loc=R7 | IOSTANDARD = LVCMOS33 ; # FPGA_D5, LED_G
  163. #net S<4> loc=P10 | IOSTANDARD = LVCMOS33 ; # FPGA_D2, LED_B
  164. #net S<5> loc=T7 | IOSTANDARD = LVCMOS33 ; # FPGA_D4, LED_F
  165. #net S<6> loc=R10 | IOSTANDARD = LVCMOS33 ; # FPGA_D3, LED_A
  166. #net S<7> loc=N11 | IOSTANDARD = LVCMOS33 ; # FPGA_D1, LED_DP
  167. #
  168. # Parallel Port
  169. #
  170. #net PPORT_load loc=N14 | IOSTANDARD = LVCMOS33 ;
  171. #net PPORT_clk loc=P15 | IOSTANDARD = LVCMOS33 ;
  172. #net PPORT_din<0> loc=R16 | IOSTANDARD = LVCMOS33 ;
  173. #net PPORT_din<1> loc=P14 | IOSTANDARD = LVCMOS33 ;
  174. #net PPORT_din<2> loc=P13 | IOSTANDARD = LVCMOS33 ;
  175. #net PPORT_din<3> loc=N12 | IOSTANDARD = LVCMOS33 ;
  176. #
  177. #net PPORT_dout<0> loc=N5 | IOSTANDARD = LVCMOS33 ;
  178. #net PPORT_dout<1> loc=K14 | IOSTANDARD = LVCMOS33 ;
  179. #net PPORT_dout<2> loc=K13 | IOSTANDARD = LVCMOS33 ;
  180. #net PPORT_dout<3> loc=T10 | IOSTANDARD = LVCMOS33 ;
  181. #
  182. #net PPORT_d<0> loc=N14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<8> / PPORT_LOAD
  183. #net PPORT_d<1> loc=P15 | IOSTANDARD = LVCMOS33 ; # FLASH_A<9> / PPORT_CLK
  184. #net PPORT_d<2> loc=R16 | IOSTANDARD = LVCMOS33 ; # FLASH_A<10> / PPORT_DIN<0>
  185. #net PPORT_d<3> loc=P14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<11> / PPORT_DIN<1>
  186. #net PPORT_d<4> loc=P13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<12> / PPORT_DIN<2>
  187. #net PPORT_d<5> loc=N12 | IOSTANDARD = LVCMOS33 ; # FLASH_A<13> / PPORT_DIN<3>
  188. ##net PPORT_d<6> loc=T14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<14>
  189. ##net PPORT_d<7> loc=R13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<15>
  190. #
  191. #net PPORT_s<3> loc=N5 | IOSTANDARD = LVCMOS33 ; # FLASH_A<0> / PPORT_DOUT<0>
  192. #net PPORT_s<4> loc=K14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<1> / PPORT_DOUT<1>
  193. #net PPORT_s<5> loc=K13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<2> / PPORT_DOUT<2>
  194. #net PPORT_s<6> loc=T10 | IOSTANDARD = LVCMOS33 ; # / PPORT_DOUT<3>
  195. #
  196. ########################################################
  197. #
  198. # XST3.0 pins
  199. #
  200. ########################################################
  201. #
  202. # BAR LED
  203. #
  204. #net BAR<1> loc=L5 | IOSTANDARD = LVCMOS33 ; # bar led 1, PB_A0
  205. #net BAR<2> loc=N2 | IOSTANDARD = LVCMOS33 ; # bar led 2, PB_A1
  206. #net BAR<3> loc=M3 | IOSTANDARD = LVCMOS33 ; # bar led 3, PB_A2
  207. #net BAR<4> loc=N1 | IOSTANDARD = LVCMOS33 ; # bar led 4, PB_A3
  208. #net BAR<5> loc=T13 | IOSTANDARD = LVCMOS33 ; # bar led 5, PB_A4
  209. #net BAR<6> loc=L15 | IOSTANDARD = LVCMOS33 ; # bar led 6, ETHER_IRQ
  210. #net BAR<7> loc=J13 | IOSTANDARD = LVCMOS33 ; # bar led 7, USB_IRQ_N
  211. #net BAR<8> loc=H15 | IOSTANDARD = LVCMOS33 ; # bar led 8, IDE_IRQ
  212. #net BAR<9> loc=J16 | IOSTANDARD = LVCMOS33 ; # bar led 9, SLOT1_IRQ
  213. #net BAR<10> loc=J14 | IOSTANDARD = LVCMOS33 ; # bar led 10, SLOT2_IRQ
  214. #
  215. # Push Buttons
  216. #
  217. #net PB1_N loc=H4 | IOSTANDARD = LVCMOS33 ; # Shared with PB_D15
  218. #net PB2_N loc=L5 | IOSTANDARD = LVCMOS33 ; # Shared with BAR1, PB_A0
  219. #net PB3_N loc=N2 | IOSTANDARD = LVCMOS33 ; # Shared with BAR2, PB_A1
  220. #net PB4_N loc=M3 | IOSTANDARD = LVCMOS33 ; # Shared with BAR3, PB_A2
  221. #
  222. # RS232 PORT
  223. #
  224. net RS232_TXD loc=J2 | IOSTANDARD = LVCMOS33 ; # RS232 TD pin 3
  225. #net RS232_RXD loc=G5 | IOSTANDARD = LVCMOS33 ; # RS232 RD pin 2
  226. #net RS232_CTS loc=D1 | IOSTANDARD = LVCMOS33 ; # RS232 CTS
  227. #net RS232_RTS loc=F4 | IOSTANDARD = LVCMOS33 ; # RS232 RTS
  228. #
  229. # 16 Bit Peripheral Bus
  230. #
  231. # 5-bit Peripheral address bus
  232. net PB_A<0> loc=L5 | IOSTANDARD = LVCMOS33 ; # Shared with BAR1, PB2
  233. net PB_A<1> loc=N2 | IOSTANDARD = LVCMOS33 ; # Shared with BAR2, PB3
  234. net PB_A<2> loc=M3 | IOSTANDARD = LVCMOS33 ; # Shared with BAR3, PB4
  235. net PB_A<3> loc=N1 | IOSTANDARD = LVCMOS33 ; # Shared with BAR4
  236. net PB_A<4> loc=T13 | IOSTANDARD = LVCMOS33 ; # Shared with BAR5
  237. # 16-bit peripheral data bus
  238. net PB_D<0> loc=P12 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW1
  239. net PB_D<1> loc=J1 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW2
  240. net PB_D<2> loc=H1 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW3
  241. net PB_D<3> loc=H3 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW4
  242. net PB_D<4> loc=G2 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW5
  243. net PB_D<5> loc=K15 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW6
  244. net PB_D<6> loc=K16 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW7
  245. net PB_D<7> loc=F15 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW8
  246. net PB_D<8> loc=E2 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_A
  247. net PB_D<9> loc=E1 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_B
  248. net PB_D<10> loc=F3 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_C
  249. net PB_D<11> loc=F2 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_D
  250. net PB_D<12> loc=G4 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_E
  251. net PB_D<13> loc=G3 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_F
  252. net PB_D<14> loc=G1 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_G
  253. net PB_D<15> loc=H4 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_DP, PB1
  254. net PB_RD_N loc=P2 | IOSTANDARD = LVCMOS33 ; # disk I/O read control
  255. net PB_WR_N loc=R1 | IOSTANDARD = LVCMOS33 ; # disk I/O write control
  256. net RESET_TRIGGER loc=D15 | IOSTANDARD = LVCMOS33 ; # Reset RESET_TRIGGER#
  257. #
  258. # IDE Interface
  259. #
  260. #net IDE_CS0_N loc=G15 | IOSTANDARD = LVCMOS33 ; # disk register-bank select
  261. #net IDE_CS1_N loc=G14 | IOSTANDARD = LVCMOS33 ; # disk register-bank select
  262. #net IDE_DMACK_N loc=K1 | IOSTANDARD = LVCMOS33 ; # (out) IDE DMA acknowledge
  263. #net IDE_DMARQ loc=L4 | IOSTANDARD = LVCMOS33 ; # (in) IDE DMA request
  264. #net IDE_IORDY loc=L2 | IOSTANDARD = LVCMOS33 ; # (in) IDE IO ready
  265. #net IDE_IRQ loc=H15 | IOSTANDARD = LVCMOS33 ; # (in) IDE interrupt # shared with BAR8
  266. #
  267. # Ethernet Controller
  268. # Disable if not used
  269. #
  270. net ether_cs_n loc=G13 | IOSTANDARD = LVCMOS33 ; # (out)Ethernet chip-enable
  271. net ether_aen loc=E14 | IOSTANDARD = LVCMOS33 ; # (out) Ethernet address enable not
  272. net ether_bhe_n loc=J3 | IOSTANDARD = LVCMOS33 ; # (out) Ethernet bus high enable
  273. net ether_clk loc=R9 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet clock
  274. net ether_irq loc=L15 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet irq - Shared with BAR6
  275. net ether_rdy loc=M2 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet ready
  276. #
  277. # Expansion slots
  278. #
  279. #net slot1_cs_n loc=E15 | IOSTANDARD = LVCMOS33 ; # (out)
  280. #net slot1_irq loc=J16 | IOSTANDARD = LVCMOS33 ; # (in) Shared with BAR9
  281. #net slot2_cs_n loc=D16 | IOSTANDARD = LVCMOS33 ; # (out)
  282. #net slot2_irq loc=J14 | IOSTANDARD = LVCMOS33 ; # (in) Shared with BAR10
  283. #
  284. # Audio codec
  285. #
  286. #net audio_lrck loc=R12 | IOSTANDARD = LVCMOS33 ; # (out)
  287. #net audio_mclk loc=P11 | IOSTANDARD = LVCMOS33 ; # (out)
  288. #net audio_sclk loc=T12 | IOSTANDARD = LVCMOS33 ; # (out)
  289. #net audio_sdti loc=M10 | IOSTANDARD = LVCMOS33 ; # (out)
  290. #net audio_sdto loc=K5 | IOSTANDARD = LVCMOS33 ; # (in)
  291. #
  292. # i2c
  293. #
  294. #net i2c_scl loc=F5 | IOSTANDARD = LVCMOS33 ; #(out)
  295. #net i2c_sda loc=D2 | IOSTANDARD = LVCMOS33 ; # (in/out)
  296. #
  297. # USB
  298. #
  299. #NET USB_CLK LOC=M1 | IOSTANDARD = LVCMOS33 ; # (IN)
  300. #NET USB_IRQ_N LOC=J13 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with BAR7
  301. #NET USB_SUSPEND LOC=l3 | IOSTANDARD = LVCMOS33 ; # (IN)
  302. #
  303. # VIDEO DIGITIZER
  304. #
  305. #NET VIDIN_AVID LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
  306. #NET VIDIN_CLK LOC=H16 | IOSTANDARD = LVCMOS33 ; # (IN)
  307. #NET VIDIN_FID LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
  308. #NET VIDIN_HSYNC LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
  309. #NET VIDIN_IRQ LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
  310. #NET VIDIN_VSYNC LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
  311. #NET VIDIN_Y<0> LOC=H14 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_A
  312. #NET VIDIN_Y<1> LOC=M4 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_B
  313. #NET VIDIN_Y<2> LOC=P1 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_C
  314. #NET VIDIN_Y<3> LOC=N3 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_D
  315. #NET VIDIN_Y<4> LOC=M15 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_E
  316. #NET VIDIN_Y<5> LOC=H13 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_F
  317. #NET VIDIN_Y<6> LOC=G16 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_G
  318. #NET VIDIN_Y<7> LOC=N15 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_DP
  319. #
  320. # Timing Constraints
  321. #
  322. NET "CLKA" TNM_NET="CLKA";
  323. TIMESPEC "TS_clk"=PERIOD "CLKA" 10 ns HIGH 50 %;