Makefile 188 B

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  1. project = j1
  2. vendor = xilinx
  3. family = spartan3s
  4. part = xc3s1000-4ft256
  5. top_module = top
  6. vfiles = ../verilog/top.v ../verilog/j1.v ../verilog/ck_div.v ../verilog/uart.v
  7. include xilinx.mk