from memory import Op
from operands import *
TABLE = {
    0x00: Op(mnemonic="BRK", src=M_NONE, dst=M_PC, cycles=7),
    0x01: Op(mnemonic="ORA", src=M_INDX, dst=M_AC, cycles=6),
    0x05: Op(mnemonic="ORA", src=M_ZERO, dst=M_AC, cycles=3),
    0x06: Op(mnemonic="ASL", src=M_ZERO, dst=M_ZERO, cycles=5),
    0x08: Op(mnemonic="PHP", src=M_SR, dst=M_NONE, cycles=3),
    0x09: Op(mnemonic="ORA", src=M_IMM, dst=M_AC, cycles=2),
    0x0a: Op(mnemonic="ASL", src=M_AC, dst=M_AC, cycles=2),
    0x0d: Op(mnemonic="ORA", src=M_ABS, dst=M_AC, cycles=4),
    0x0e: Op(mnemonic="ASL", src=M_ABS, dst=M_ABS, cycles=6),
    0x10: Op(mnemonic="BPL", src=M_REL, dst=M_NONE, cycles=2),
    0x11: Op(mnemonic="ORA", src=M_INDY, dst=M_AC, cycles=5),
    0x15: Op(mnemonic="ORA", src=M_ZERX, dst=M_AC, cycles=4),
    0x16: Op(mnemonic="ASL", src=M_ZERX, dst=M_ZERX, cycles=6),
    0x18: Op(mnemonic="CLC", src=M_NONE, dst=M_FC, cycles=2),
    0x19: Op(mnemonic="ORA", src=M_ABSY, dst=M_AC, cycles=4),
    0x1d: Op(mnemonic="ORA", src=M_ABSX, dst=M_AC, cycles=4),
    0x1e: Op(mnemonic="ASL", src=M_ABSX, dst=M_ABSX, cycles=7),
    0x20: Op(mnemonic="JSR", src=M_ADDR, dst=M_PC, cycles=6),
    0x21: Op(mnemonic="AND", src=M_INDX, dst=M_AC, cycles=6),
    0x24: Op(mnemonic="BIT", src=M_ZERO, dst=M_NONE, cycles=3),
    0x25: Op(mnemonic="AND", src=M_ZERO, dst=M_AC, cycles=3),
    0x26: Op(mnemonic="ROL", src=M_ZERO, dst=M_ZERO, cycles=5),
    0x28: Op(mnemonic="PLP", src=M_NONE, dst=M_SR, cycles=4),
    0x29: Op(mnemonic="AND", src=M_IMM, dst=M_AC, cycles=2),
    0x2a: Op(mnemonic="ROL", src=M_AC, dst=M_AC, cycles=2),
    0x2c: Op(mnemonic="BIT", src=M_ABS, dst=M_NONE, cycles=4),
    0x2d: Op(mnemonic="AND", src=M_ABS, dst=M_AC, cycles=4),
    0x2e: Op(mnemonic="ROL", src=M_ABS, dst=M_ABS, cycles=6),
    0x30: Op(mnemonic="BMI", src=M_REL, dst=M_NONE, cycles=2),
    0x31: Op(mnemonic="AND", src=M_INDY, dst=M_AC, cycles=5),
    0x35: Op(mnemonic="AND", src=M_ZERX, dst=M_AC, cycles=4),
    0x36: Op(mnemonic="ROL", src=M_ZERX, dst=M_ZERX, cycles=6),
    0x38: Op(mnemonic="SEC", src=M_NONE, dst=M_FC, cycles=2),
    0x39: Op(mnemonic="AND", src=M_ABSY, dst=M_AC, cycles=4),
    0x3d: Op(mnemonic="AND", src=M_ABSX, dst=M_AC, cycles=4),
    0x3e: Op(mnemonic="ROL", src=M_ABSX, dst=M_ABSX, cycles=7),
    0x40: Op(mnemonic="RTI", src=M_NONE, dst=M_PC, cycles=6),
    0x41: Op(mnemonic="EOR", src=M_INDX, dst=M_AC, cycles=6),
    0x45: Op(mnemonic="EOR", src=M_ZERO, dst=M_AC, cycles=3),
    0x46: Op(mnemonic="LSR", src=M_ZERO, dst=M_ZERO, cycles=5),
    0x48: Op(mnemonic="PHA", src=M_AC, dst=M_NONE, cycles=3),
    0x49: Op(mnemonic="EOR", src=M_IMM, dst=M_AC, cycles=2),
    0x4a: Op(mnemonic="LSR", src=M_AC, dst=M_AC, cycles=2),
    0x4c: Op(mnemonic="JMP", src=M_ADDR, dst=M_PC, cycles=3),
    0x4d: Op(mnemonic="EOR", src=M_ABS, dst=M_AC, cycles=4),
    0x4e: Op(mnemonic="LSR", src=M_ABS, dst=M_ABS, cycles=6),
    0x50: Op(mnemonic="BVC", src=M_REL, dst=M_NONE, cycles=2),
    0x51: Op(mnemonic="EOR", src=M_INDY, dst=M_AC, cycles=5),
    0x55: Op(mnemonic="EOR", src=M_ZERX, dst=M_AC, cycles=4),
    0x56: Op(mnemonic="LSR", src=M_ZERX, dst=M_ZERX, cycles=6),
    0x58: Op(mnemonic="CLI", src=M_NONE, dst=M_FI, cycles=2),
    0x59: Op(mnemonic="EOR", src=M_ABSY, dst=M_AC, cycles=4),
    0x5d: Op(mnemonic="EOR", src=M_ABSX, dst=M_AC, cycles=4),
    0x5e: Op(mnemonic="LSR", src=M_ABSX, dst=M_ABSX, cycles=7),
    0x60: Op(mnemonic="RTS", src=M_NONE, dst=M_PC, cycles=6),
    0x61: Op(mnemonic="ADC", src=M_INDX, dst=M_AC, cycles=6),
    0x65: Op(mnemonic="ADC", src=M_ZERO, dst=M_AC, cycles=3),
    0x66: Op(mnemonic="ROR", src=M_ZERO, dst=M_ZERO, cycles=5),
    0x68: Op(mnemonic="PLA", src=M_NONE, dst=M_AC, cycles=4),
    0x69: Op(mnemonic="ADC", src=M_IMM, dst=M_AC, cycles=2),
    0x6a: Op(mnemonic="ROR", src=M_AC, dst=M_AC, cycles=2),
    0x6c: Op(mnemonic="JMP", src=M_AIND, dst=M_PC, cycles=5),
    0x6d: Op(mnemonic="ADC", src=M_ABS, dst=M_AC, cycles=4),
    0x6e: Op(mnemonic="ROR", src=M_ABS, dst=M_ABS, cycles=6),
    0x70: Op(mnemonic="BVS", src=M_REL, dst=M_NONE, cycles=2),
    0x71: Op(mnemonic="ADC", src=M_INDY, dst=M_AC, cycles=5),
    0x75: Op(mnemonic="ADC", src=M_ZERX, dst=M_AC, cycles=4),
    0x76: Op(mnemonic="ROR", src=M_ZERX, dst=M_ZERX, cycles=6),
    0x78: Op(mnemonic="SEI", src=M_NONE, dst=M_FI, cycles=2),
    0x79: Op(mnemonic="ADC", src=M_ABSY, dst=M_AC, cycles=4),
    0x7d: Op(mnemonic="ADC", src=M_ABSX, dst=M_AC, cycles=4),
    0x7e: Op(mnemonic="ROR", src=M_ABSX, dst=M_ABSX, cycles=7),
    0x81: Op(mnemonic="STA", src=M_AC, dst=M_INDX, cycles=6),
    0x84: Op(mnemonic="STY", src=M_YR, dst=M_ZERO, cycles=3),
    0x85: Op(mnemonic="STA", src=M_AC, dst=M_ZERO, cycles=3),
    0x86: Op(mnemonic="STX", src=M_XR, dst=M_ZERO, cycles=3),
    0x88: Op(mnemonic="DEY", src=M_YR, dst=M_YR, cycles=2),
    0x8a: Op(mnemonic="TXA", src=M_XR, dst=M_AC, cycles=2),
    0x8c: Op(mnemonic="STY", src=M_YR, dst=M_ABS, cycles=4),
    0x8d: Op(mnemonic="STA", src=M_AC, dst=M_ABS, cycles=4),
    0x8e: Op(mnemonic="STX", src=M_XR, dst=M_ABS, cycles=4),
    0x90: Op(mnemonic="BCC", src=M_REL, dst=M_NONE, cycles=2),
    0x91: Op(mnemonic="STA", src=M_AC, dst=M_INDY, cycles=6),
    0x94: Op(mnemonic="STY", src=M_YR, dst=M_ZERX, cycles=4),
    0x95: Op(mnemonic="STA", src=M_AC, dst=M_ZERX, cycles=4),
    0x96: Op(mnemonic="STX", src=M_XR, dst=M_ZERY, cycles=4),
    0x98: Op(mnemonic="TYA", src=M_YR, dst=M_AC, cycles=2),
    0x99: Op(mnemonic="STA", src=M_AC, dst=M_ABSY, cycles=5),
    0x9a: Op(mnemonic="TXS", src=M_XR, dst=M_SP, cycles=2),
    0x9d: Op(mnemonic="STA", src=M_AC, dst=M_ABSX, cycles=5),
    0xa0: Op(mnemonic="LDY", src=M_IMM, dst=M_YR, cycles=2),
    0xa1: Op(mnemonic="LDA", src=M_INDX, dst=M_AC, cycles=6),
    0xa2: Op(mnemonic="LDX", src=M_IMM, dst=M_XR, cycles=2),
    0xa4: Op(mnemonic="LDY", src=M_ZERO, dst=M_YR, cycles=3),
    0xa5: Op(mnemonic="LDA", src=M_ZERO, dst=M_AC, cycles=3),
    0xa6: Op(mnemonic="LDX", src=M_ZERO, dst=M_XR, cycles=3),
    0xa8: Op(mnemonic="TAY", src=M_AC, dst=M_YR, cycles=2),
    0xa9: Op(mnemonic="LDA", src=M_IMM, dst=M_AC, cycles=2),
    0xaa: Op(mnemonic="TAX", src=M_AC, dst=M_XR, cycles=2),
    0xac: Op(mnemonic="LDY", src=M_ABS, dst=M_YR, cycles=4),
    0xad: Op(mnemonic="LDA", src=M_ABS, dst=M_AC, cycles=4),
    0xae: Op(mnemonic="LDX", src=M_ABS, dst=M_XR, cycles=4),
    0xb0: Op(mnemonic="BCS", src=M_REL, dst=M_NONE, cycles=2),
    0xb1: Op(mnemonic="LDA", src=M_INDY, dst=M_AC, cycles=5),
    0xb4: Op(mnemonic="LDY", src=M_ZERX, dst=M_YR, cycles=4),
    0xb5: Op(mnemonic="LDA", src=M_ZERX, dst=M_AC, cycles=4),
    0xb6: Op(mnemonic="LDX", src=M_ZERY, dst=M_XR, cycles=4),
    0xb8: Op(mnemonic="CLV", src=M_NONE, dst=M_FV, cycles=2),
    0xb9: Op(mnemonic="LDA", src=M_ABSY, dst=M_AC, cycles=4),
    0xba: Op(mnemonic="TSX", src=M_SP, dst=M_XR, cycles=2),
    0xbc: Op(mnemonic="LDY", src=M_ABSX, dst=M_YR, cycles=4),
    0xbd: Op(mnemonic="LDA", src=M_ABSX, dst=M_AC, cycles=4),
    0xbe: Op(mnemonic="LDX", src=M_ABSY, dst=M_XR, cycles=4),
    0xc0: Op(mnemonic="CPY", src=M_IMM, dst=M_NONE, cycles=2),
    0xc1: Op(mnemonic="CMP", src=M_INDX, dst=M_NONE, cycles=6),
    0xc4: Op(mnemonic="CPY", src=M_ZERO, dst=M_NONE, cycles=3),
    0xc5: Op(mnemonic="CMP", src=M_ZERO, dst=M_NONE, cycles=3),
    0xc6: Op(mnemonic="DEC", src=M_ZERO, dst=M_ZERO, cycles=5),
    0xc8: Op(mnemonic="INY", src=M_YR, dst=M_YR, cycles=2),
    0xc9: Op(mnemonic="CMP", src=M_IMM, dst=M_NONE, cycles=2),
    0xca: Op(mnemonic="DEX", src=M_XR, dst=M_XR, cycles=2),
    0xcc: Op(mnemonic="CPY", src=M_ABS, dst=M_NONE, cycles=4),
    0xcd: Op(mnemonic="CMP", src=M_ABS, dst=M_NONE, cycles=4),
    0xce: Op(mnemonic="DEC", src=M_ABS, dst=M_ABS, cycles=6),
    0xd0: Op(mnemonic="BNE", src=M_REL, dst=M_NONE, cycles=2),
    0xd1: Op(mnemonic="CMP", src=M_INDY, dst=M_NONE, cycles=5),
    0xd5: Op(mnemonic="CMP", src=M_ZERX, dst=M_NONE, cycles=4),
    0xd6: Op(mnemonic="DEC", src=M_ZERX, dst=M_ZERX, cycles=6),
    0xd8: Op(mnemonic="CLD", src=M_NONE, dst=M_FD, cycles=2),
    0xd9: Op(mnemonic="CMP", src=M_ABSY, dst=M_NONE, cycles=4),
    0xdd: Op(mnemonic="CMP", src=M_ABSX, dst=M_NONE, cycles=4),
    0xde: Op(mnemonic="DEC", src=M_ABSX, dst=M_ABSX, cycles=7),
    0xe0: Op(mnemonic="CPX", src=M_IMM, dst=M_NONE, cycles=2),
    0xe1: Op(mnemonic="SBC", src=M_INDX, dst=M_AC, cycles=6),
    0xe4: Op(mnemonic="CPX", src=M_ZERO, dst=M_NONE, cycles=3),
    0xe5: Op(mnemonic="SBC", src=M_ZERO, dst=M_AC, cycles=3),
    0xe6: Op(mnemonic="INC", src=M_ZERO, dst=M_ZERO, cycles=5),
    0xe8: Op(mnemonic="INX", src=M_XR, dst=M_XR, cycles=2),
    0xe9: Op(mnemonic="SBC", src=M_IMM, dst=M_AC, cycles=2),
    0xea: Op(mnemonic="NOP", src=M_NONE, dst=M_NONE, cycles=2),
    0xec: Op(mnemonic="CPX", src=M_ABS, dst=M_NONE, cycles=4),
    0xed: Op(mnemonic="SBC", src=M_ABS, dst=M_AC, cycles=4),
    0xee: Op(mnemonic="INC", src=M_ABS, dst=M_ABS, cycles=6),
    0xf0: Op(mnemonic="BEQ", src=M_REL, dst=M_NONE, cycles=2),
    0xf1: Op(mnemonic="SBC", src=M_INDY, dst=M_AC, cycles=5),
    0xf5: Op(mnemonic="SBC", src=M_ZERX, dst=M_AC, cycles=4),
    0xf6: Op(mnemonic="INC", src=M_ZERX, dst=M_ZERX, cycles=6),
    0xf8: Op(mnemonic="SED", src=M_NONE, dst=M_FD, cycles=2),
    0xf9: Op(mnemonic="SBC", src=M_ABSY, dst=M_AC, cycles=4),
    0xfd: Op(mnemonic="SBC", src=M_ABSX, dst=M_AC, cycles=4),
    0xfe: Op(mnemonic="INC", src=M_ABSX, dst=M_ABSX, cycles=7),
}
