ia32_operand.cpp 17 KB

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  1. #include <stdio.h>
  2. #include <stdlib.h>
  3. #include <string.h>
  4. #include "libdis.h"
  5. #include "ia32_insn.h"
  6. #include "ia32_operand.h"
  7. #include "ia32_modrm.h"
  8. #include "ia32_reg.h"
  9. #include "x86_imm.h"
  10. #include "x86_operand_list.h"
  11. /* apply segment override to memory operand in insn */
  12. static void apply_seg( x86_op_t *op, unsigned int prefixes ) {
  13. if (! prefixes ) return;
  14. /* apply overrides from prefix */
  15. switch ( prefixes & PREFIX_REG_MASK ) {
  16. /* NOTE: that op->flags for segment override are not a bitfield */
  17. case PREFIX_CS:
  18. op->flags.op_seg = x86_op_flags::op_cs_seg>>8; break;
  19. case PREFIX_SS:
  20. op->flags.op_seg = x86_op_flags::op_ss_seg>>8; break;
  21. case PREFIX_DS:
  22. op->flags.op_seg = x86_op_flags::op_ds_seg>>8; break;
  23. case PREFIX_ES:
  24. op->flags.op_seg = x86_op_flags::op_es_seg>>8; break;
  25. case PREFIX_FS:
  26. op->flags.op_seg = x86_op_flags::op_fs_seg>>8; break;
  27. case PREFIX_GS:
  28. op->flags.op_seg = x86_op_flags::op_gs_seg>>8; break;
  29. }
  30. return;
  31. }
  32. size_t Ia32_Decoder::decode_operand_value( unsigned char *buf, size_t buf_len,
  33. x86_op_t *op,
  34. unsigned int addr_meth, size_t op_size,
  35. unsigned int op_value, unsigned char modrm,
  36. size_t gen_regs ) {
  37. size_t size = 0;
  38. /* ++ Do Operand Addressing Method / Decode operand ++ */
  39. switch (addr_meth) {
  40. /* This sets the operand Size based on the Intel Opcode Map
  41. * (Vol 2, Appendix A). Letter encodings are from section
  42. * A.1.1, 'Codes for Addressing Method' */
  43. /* ---------------------- Addressing Method -------------- */
  44. /* Note that decoding mod ModR/M operand adjusts the size of
  45. * the instruction, but decoding the reg operand does not.
  46. * This should not cause any problems, as every 'reg' operand
  47. * has an associated 'mod' operand.
  48. * Goddamn-Intel-Note:
  49. * Some Intel addressing methods [M, R] specify that modR/M
  50. * byte may only refer to a memory address/may only refer to
  51. * a register -- however Intel provides no clues on what to do
  52. * if, say, the modR/M for an M opcode decodes to a register
  53. * rather than a memory address ... returning 0 is out of the
  54. * question, as this would be an Immediate or a RelOffset, so
  55. * instead these modR/Ms are decoded with total disregard to
  56. * the M, R constraints. */
  57. /* MODRM -- mod operand. sets size to at least 1! */
  58. case ADDRMETH_E: /* ModR/M present, Gen reg or memory */
  59. size = ia32_modrm_decode( buf, buf_len, op, gen_regs );
  60. break;
  61. case ADDRMETH_M: /* ModR/M only refers to memory */
  62. size = ia32_modrm_decode( buf, buf_len, op, gen_regs );
  63. break;
  64. case ADDRMETH_Q: /* ModR/M present, MMX or Memory */
  65. size = ia32_modrm_decode( buf, buf_len, op, REG_MMX_OFFSET );
  66. break;
  67. case ADDRMETH_R: /* ModR/M mod == gen reg */
  68. size = ia32_modrm_decode( buf, buf_len, op, gen_regs );
  69. break;
  70. case ADDRMETH_W: /* ModR/M present, mem or SIMD reg */
  71. size = ia32_modrm_decode( buf, buf_len, op, REG_SIMD_OFFSET );
  72. break;
  73. /* MODRM -- reg operand. does not effect size! */
  74. case ADDRMETH_C: /* ModR/M reg == control reg */
  75. ia32_reg_decode( modrm, op, REG_CTRL_OFFSET );
  76. break;
  77. case ADDRMETH_D: /* ModR/M reg == debug reg */
  78. ia32_reg_decode( modrm, op, REG_DEBUG_OFFSET );
  79. break;
  80. case ADDRMETH_G: /* ModR/M reg == gen-purpose reg */
  81. ia32_reg_decode( modrm, op, gen_regs );
  82. break;
  83. case ADDRMETH_P: /* ModR/M reg == qword MMX reg */
  84. ia32_reg_decode( modrm, op, REG_MMX_OFFSET );
  85. break;
  86. case ADDRMETH_S: /* ModR/M reg == segment reg */
  87. ia32_reg_decode( modrm, op, REG_SEG_OFFSET );
  88. break;
  89. case ADDRMETH_T: /* ModR/M reg == test reg */
  90. ia32_reg_decode( modrm, op, REG_TEST_OFFSET );
  91. break;
  92. case ADDRMETH_V: /* ModR/M reg == SIMD reg */
  93. ia32_reg_decode( modrm, op, REG_SIMD_OFFSET );
  94. break;
  95. /* No MODRM : note these set operand type explicitly */
  96. case ADDRMETH_A: /* No modR/M -- direct addr */
  97. op->type = op_absolute;
  98. /* segment:offset address used in far calls */
  99. if ( m_decoded->addr_size == 4 ) {
  100. x86_imm_sized( buf, buf_len, &op->data.absolute.offset.off32, 4 );
  101. size = 4;
  102. } else {
  103. x86_imm_sized( buf, buf_len,&op->data.absolute.offset.off16, 2 );
  104. size = 2;
  105. }
  106. x86_imm_sized( buf+size, buf_len-size, &op->data.absolute.segment, 2 );
  107. size+=2;
  108. break;
  109. case ADDRMETH_I: /* Immediate val */
  110. op->type = op_immediate;
  111. /* if it ever becomes legal to have imm as dest and
  112. * there is a src ModR/M operand, we are screwed! */
  113. if ( op->flags.op_signed ) {
  114. x86_imm_signsized(buf, buf_len, &op->data.byte,
  115. op_size);
  116. } else {
  117. x86_imm_sized(buf, buf_len, &op->data.byte,
  118. op_size);
  119. }
  120. size = op_size;
  121. break;
  122. case ADDRMETH_J: /* Rel offset to add to IP [jmp] */
  123. /* this fills op->data.near_offset or
  124. op->data.far_offset depending on the size of
  125. the operand */
  126. op->flags.op_signed = true;
  127. switch(op_size)
  128. {
  129. case 1:
  130. /* one-byte near offset */
  131. op->type = op_relative_near;
  132. size = x86_imm_signsized(buf, buf_len, &op->data.relative_near, 1);
  133. break;
  134. case 2:
  135. op->type = op_relative_far;
  136. int16_t offset_val;
  137. size = x86_imm_signsized(buf, buf_len,&offset_val, 2);
  138. op->data.relative_far=offset_val;
  139. break;
  140. default:
  141. assert(false);
  142. size=0;
  143. }
  144. break;
  145. case ADDRMETH_O: /* No ModR/M; op is word/dword offset */
  146. /* NOTE: these are actually RVAs not offsets to seg!! */
  147. /* note bene: 'O' ADDR_METH uses addr_size to
  148. determine operand size */
  149. op->type = op_offset;
  150. op->flags.op_pointer=true;
  151. x86_imm_sized( buf, buf_len, &op->data.offset, m_decoded->addr_size );
  152. size = m_decoded->addr_size;
  153. break;
  154. /* Hard-coded: these are specified in the insn definition */
  155. case ADDRMETH_F: /* EFLAGS register */
  156. op->type = op_register;
  157. op->flags.op_hardcode=true;
  158. ia32_handle_register( &op->data.reg, REG_FLAGS_INDEX );
  159. break;
  160. case ADDRMETH_X: /* Memory addressed by DS:SI [string] */
  161. op->type = op_expression;
  162. op->flags.op_hardcode = true;
  163. op->flags.op_seg = x86_op_flags::op_ds_seg>>8;
  164. op->flags.op_pointer = true;
  165. op->flags.op_string = true;
  166. ia32_handle_register( &op->data.expression.base,
  167. REG_DWORD_OFFSET + 6 );
  168. break;
  169. case ADDRMETH_Y: /* Memory addressed by ES:DI [string] */
  170. op->type = op_expression;
  171. op->flags.op_hardcode = true;
  172. op->flags.op_seg = x86_op_flags::op_es_seg>>8;
  173. op->flags.op_pointer = true;
  174. op->flags.op_string = true;
  175. ia32_handle_register( &op->data.expression.base,
  176. REG_DWORD_OFFSET + 7 );
  177. break;
  178. case ADDRMETH_RR: /* Gen Register hard-coded in opcode */
  179. op->type = op_register;
  180. op->flags.op_hardcode = true;
  181. ia32_handle_register( &op->data.reg,
  182. op_value + gen_regs );
  183. break;
  184. case ADDRMETH_RS: /* Seg Register hard-coded in opcode */
  185. op->type = op_register;
  186. op->flags.op_hardcode = true;
  187. ia32_handle_register( &op->data.reg, op_value + REG_SEG_OFFSET );
  188. break;
  189. case ADDRMETH_RF: /* FPU Register hard-coded in opcode */
  190. op->type = op_register;
  191. op->flags.op_hardcode = true;
  192. ia32_handle_register( &op->data.reg,
  193. op_value + REG_FPU_OFFSET );
  194. break;
  195. case ADDRMETH_RT: /* TST Register hard-coded in opcode */
  196. op->type = op_register;
  197. op->flags.op_hardcode = true;
  198. ia32_handle_register( &op->data.reg,
  199. op_value + REG_TEST_OFFSET );
  200. break;
  201. case ADDRMETH_II: /* Immediate hard-coded in opcode */
  202. op->type = op_immediate;
  203. op->data.dword = op_value;
  204. op->flags.op_hardcode = true;
  205. break;
  206. case 0: /* Operand is not used */
  207. default:
  208. /* ignore -- operand not used in this insn */
  209. op->type = op_unused; /* this shouldn't happen! */
  210. break;
  211. }
  212. return size;
  213. }
  214. size_t Ia32_Decoder::decode_operand_size( unsigned int op_type, x86_op_t *op ) {
  215. size_t size;
  216. /* ++ Do Operand Type ++ */
  217. switch (op_type) {
  218. /* This sets the operand Size based on the Intel Opcode Map
  219. * (Vol 2, Appendix A). Letter encodings are from section
  220. * A.1.2, 'Codes for Operand Type' */
  221. /* NOTE: in this routines, 'size' refers to the size
  222. * of the operand in the raw (encoded) instruction;
  223. * 'datatype' stores the actual size and datatype
  224. * of the operand */
  225. /* ------------------------ Operand Type ----------------- */
  226. case OPTYPE_c: /* byte or word [op size attr] */
  227. size = (m_decoded->op_size == 4) ? 2 : 1;
  228. op->datatype = (size == 4) ? op_word : op_byte;
  229. break;
  230. case OPTYPE_a: /* 2 word or 2 dword [op size attr] */
  231. /* pointer to a 16:16 or 32:32 BOUNDS operand */
  232. size = (m_decoded->op_size == 4) ? 8 : 4;
  233. op->datatype = (size == 4) ? op_bounds32 : op_bounds16;
  234. break;
  235. case OPTYPE_v: /* word or dword [op size attr] */
  236. size = (m_decoded->op_size == 4) ? 4 : 2;
  237. op->datatype = (size == 4) ? op_dword : op_word;
  238. break;
  239. case OPTYPE_p: /* 32/48-bit ptr [op size attr] */
  240. /* technically these flags are not accurate: the
  241. * value s a 16:16 pointer or a 16:32 pointer, where
  242. * the first '16' is a segment */
  243. size = (m_decoded->addr_size == 4) ? 6 : 4;
  244. op->datatype = (size == 6) ? op_descr32 : op_descr16;
  245. break;
  246. case OPTYPE_b: /* byte, ignore op-size */
  247. size = 1;
  248. op->datatype = op_byte;
  249. break;
  250. case OPTYPE_w: /* word, ignore op-size */
  251. size = 2;
  252. op->datatype = op_word;
  253. break;
  254. case OPTYPE_d: /* dword , ignore op-size */
  255. size = 4;
  256. op->datatype = op_dword;
  257. break;
  258. case OPTYPE_s: /* 6-byte psuedo-descriptor */
  259. /* ptr to 6-byte value which is 32:16 in 32-bit
  260. * mode, or 8:24:16 in 16-bit mode. The high byte
  261. * is ignored in 16-bit mode. */
  262. size = 6;
  263. op->datatype = (m_decoded->addr_size == 4) ?
  264. op_pdescr32 : op_pdescr16;
  265. break;
  266. case OPTYPE_q: /* qword, ignore op-size */
  267. size = 8;
  268. op->datatype = op_qword;
  269. break;
  270. case OPTYPE_dq: /* d-qword, ignore op-size */
  271. size = 16;
  272. op->datatype = op_dqword;
  273. break;
  274. case OPTYPE_ps: /* 128-bit FP data */
  275. size = 16;
  276. /* really this is 4 packed SP FP values */
  277. op->datatype = op_ssimd;
  278. break;
  279. case OPTYPE_pd: /* 128-bit FP data */
  280. size = 16;
  281. /* really this is 2 packed DP FP values */
  282. op->datatype = op_dsimd;
  283. break;
  284. case OPTYPE_ss: /* Scalar elem of 128-bit FP data */
  285. size = 16;
  286. /* this only looks at the low dword (4 bytes)
  287. * of the xmmm register passed as a param.
  288. * This is a 16-byte register where only 4 bytes
  289. * are used in the insn. Painful, ain't it? */
  290. op->datatype = op_sssimd;
  291. break;
  292. case OPTYPE_sd: /* Scalar elem of 128-bit FP data */
  293. size = 16;
  294. /* this only looks at the low qword (8 bytes)
  295. * of the xmmm register passed as a param.
  296. * This is a 16-byte register where only 8 bytes
  297. * are used in the insn. Painful, again... */
  298. op->datatype = op_sdsimd;
  299. break;
  300. case OPTYPE_pi: /* qword mmx register */
  301. size = 8;
  302. op->datatype = op_qword;
  303. break;
  304. case OPTYPE_si: /* dword integer register */
  305. size = 4;
  306. op->datatype = op_dword;
  307. break;
  308. case OPTYPE_fs: /* single-real */
  309. size = 4;
  310. op->datatype = op_sreal;
  311. break;
  312. case OPTYPE_fd: /* double real */
  313. size = 8;
  314. op->datatype = op_dreal;
  315. break;
  316. case OPTYPE_fe: /* extended real */
  317. size = 10;
  318. op->datatype = op_extreal;
  319. break;
  320. case OPTYPE_fb: /* packed BCD */
  321. size = 10;
  322. op->datatype = op_bcd;
  323. break;
  324. case OPTYPE_fv: /* pointer to FPU env: 14 or 28-bytes */
  325. size = (m_decoded->addr_size == 4)? 28 : 14;
  326. op->datatype = (size == 28)? op_fpuenv32: op_fpuenv16;
  327. break;
  328. case OPTYPE_ft: /* pointer to FPU env: 94 or 108 bytes */
  329. size = (m_decoded->addr_size == 4)? 108 : 94;
  330. op->datatype = (size == 108)?
  331. op_fpustate32: op_fpustate16;
  332. break;
  333. case OPTYPE_fx: /* 512-byte register stack */
  334. size = 512;
  335. op->datatype = op_fpregset;
  336. break;
  337. case OPTYPE_fp: /* floating point register */
  338. size = 10; /* double extended precision */
  339. op->datatype = op_fpreg;
  340. break;
  341. case OPTYPE_m: /* fake operand type used for "lea Gv, M" */
  342. size = m_decoded->addr_size;
  343. op->datatype = (size == 4) ? op_dword : op_word;
  344. break;
  345. case OPTYPE_none: /* handle weird instructions that have no encoding but use a dword datatype, like invlpg */
  346. size = 0;
  347. op->datatype = op_none;
  348. break;
  349. case 0:
  350. default:
  351. size = m_decoded->op_size;
  352. op->datatype = (size == 4) ? op_dword : op_word;
  353. break;
  354. }
  355. return size;
  356. }
  357. size_t Ia32_Decoder::ia32_decode_operand( unsigned char *buf, size_t buf_len,
  358. unsigned int raw_op,
  359. unsigned int raw_flags, unsigned int prefixes,
  360. unsigned char modrm ) {
  361. unsigned int addr_meth, op_type, op_size, gen_regs;
  362. x86_op_t *op;
  363. size_t size;
  364. /* ++ Yank optype and addr mode out of operand flags */
  365. addr_meth = raw_flags & ADDRMETH_MASK;
  366. op_type = raw_flags & OPTYPE_MASK;
  367. if ( raw_flags == ARG_NONE ) {
  368. /* operand is not used in this instruction */
  369. return 0;
  370. }
  371. /* allocate a new operand */
  372. op = m_decoded->x86_operand_new();
  373. /* ++ Copy flags from opcode table to x86_insn_t */
  374. op->access = (enum x86_op_access) OP_PERM(raw_flags);
  375. op->flags.whole = (OP_FLAGS(raw_flags) >> 12);
  376. /* Get size (for decoding) and datatype of operand */
  377. op_size = decode_operand_size(op_type, op);
  378. /* override default register set based on Operand Type */
  379. /* this allows mixing of 8, 16, and 32 bit regs in insn */
  380. if (op_size == 1) {
  381. gen_regs = REG_BYTE_OFFSET;
  382. } else if (op_size == 2) {
  383. gen_regs = REG_WORD_OFFSET;
  384. } else {
  385. gen_regs = REG_DWORD_OFFSET;
  386. }
  387. size = decode_operand_value( buf, buf_len, op, addr_meth,
  388. op_size, raw_op, modrm, gen_regs );
  389. /* if operand is an address, apply any segment override prefixes */
  390. if ( op->type == op_expression || op->type == op_offset ) {
  391. apply_seg(op, prefixes);
  392. }
  393. return size; /* return number of bytes in instruction */
  394. }