scanner.cpp 39 KB

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  1. /*****************************************************************************
  2. * dcc project scanner module
  3. * Implements a simple state driven scanner to convert 8086 machine code into
  4. * I-code
  5. * (C) Cristina Cifuentes, Jeff Ledermann
  6. ****************************************************************************/
  7. #include <cstring>
  8. #include "dcc.h"
  9. #include "scanner.h"
  10. #include "project.h"
  11. /* Parser flags */
  12. #define TO_REG 0x000100 /* rm is source */
  13. #define S_EXT 0x000200 /* sign extend */
  14. #define OP386 0x000400 /* 386 op-code */
  15. #define NSP 0x000800 /* NOT_HLL if SP is src or dst */
  16. // defined in Enums.h #define ICODEMASK 0xFF00FF /* Masks off parser flags */
  17. static void rm(int i);
  18. static void modrm(int i);
  19. static void segrm(int i);
  20. static void data1(int i);
  21. static void data2(int i);
  22. static void regop(int i);
  23. static void segop(int i);
  24. static void strop(int i);
  25. static void escop(int i);
  26. static void axImp(int i);
  27. static void alImp(int i);
  28. static void axSrcIm(int i);
  29. static void memImp(int i);
  30. static void memReg0(int i);
  31. static void memOnly(int i);
  32. static void dispM(int i);
  33. static void dispS(int i);
  34. static void dispN(int i);
  35. static void dispF(int i);
  36. static void prefix(int i);
  37. static void immed(int i);
  38. static void shift(int i);
  39. static void arith(int i);
  40. static void trans(int i);
  41. static void const1(int i);
  42. static void const3(int i);
  43. static void none1(int i);
  44. static void none2(int i);
  45. static void checkInt(int i);
  46. #define iZERO (llIcode)0 // For neatness
  47. #define IC llIcode
  48. static struct {
  49. void (*state1)(int);
  50. void (*state2)(int);
  51. uint32_t flg;
  52. llIcode opcode;
  53. } stateTable[] = {
  54. { modrm, none2, B , iADD }, /* 00 */
  55. { modrm, none2, 0 , iADD }, /* 01 */
  56. { modrm, none2, TO_REG | B , iADD }, /* 02 */
  57. { modrm, none2, TO_REG , iADD }, /* 03 */
  58. { data1, axImp, B , iADD }, /* 04 */
  59. { data2, axImp, 0 , iADD }, /* 05 */
  60. { segop, none2, NO_SRC , iPUSH }, /* 06 */
  61. { segop, none2, NO_SRC , iPOP }, /* 07 */
  62. { modrm, none2, B , iOR }, /* 08 */
  63. { modrm, none2, NSP , iOR }, /* 09 */
  64. { modrm, none2, TO_REG | B , iOR }, /* 0A */
  65. { modrm, none2, TO_REG | NSP , iOR }, /* 0B */
  66. { data1, axImp, B , iOR }, /* 0C */
  67. { data2, axImp, 0 , iOR }, /* 0D */
  68. { segop, none2, NO_SRC , iPUSH }, /* 0E */
  69. { none1, none2, OP386 , iZERO }, /* 0F */
  70. { modrm, none2, B , iADC }, /* 10 */
  71. { modrm, none2, NSP , iADC }, /* 11 */
  72. { modrm, none2, TO_REG | B , iADC }, /* 12 */
  73. { modrm, none2, TO_REG | NSP , iADC }, /* 13 */
  74. { data1, axImp, B , iADC }, /* 14 */
  75. { data2, axImp, 0 , iADC }, /* 15 */
  76. { segop, none2, NOT_HLL | NO_SRC , iPUSH }, /* 16 */
  77. { segop, none2, NOT_HLL | NO_SRC , iPOP }, /* 17 */
  78. { modrm, none2, B , iSBB }, /* 18 */
  79. { modrm, none2, NSP , iSBB }, /* 19 */
  80. { modrm, none2, TO_REG | B , iSBB }, /* 1A */
  81. { modrm, none2, TO_REG | NSP , iSBB }, /* 1B */
  82. { data1, axImp, B , iSBB }, /* 1C */
  83. { data2, axImp, 0 , iSBB }, /* 1D */
  84. { segop, none2, NO_SRC , iPUSH }, /* 1E */
  85. { segop, none2, NO_SRC , iPOP }, /* 1F */
  86. { modrm, none2, B , iAND }, /* 20 */
  87. { modrm, none2, NSP , iAND }, /* 21 */
  88. { modrm, none2, TO_REG | B , iAND }, /* 22 */
  89. { modrm, none2, TO_REG | NSP , iAND }, /* 23 */
  90. { data1, axImp, B , iAND }, /* 24 */
  91. { data2, axImp, 0 , iAND }, /* 25 */
  92. { prefix, none2, 0 , (IC)rES}, /* 26 */
  93. { none1, axImp, NOT_HLL | B|NO_SRC , iDAA }, /* 27 */
  94. { modrm, none2, B , iSUB }, /* 28 */
  95. { modrm, none2, 0 , iSUB }, /* 29 */
  96. { modrm, none2, TO_REG | B , iSUB }, /* 2A */
  97. { modrm, none2, TO_REG , iSUB }, /* 2B */
  98. { data1, axImp, B , iSUB }, /* 2C */
  99. { data2, axImp, 0 , iSUB }, /* 2D */
  100. { prefix, none2, 0 , (IC)rCS}, /* 2E */
  101. { none1, axImp, NOT_HLL | B|NO_SRC , iDAS }, /* 2F */
  102. { modrm, none2, B , iXOR }, /* 30 */
  103. { modrm, none2, NSP , iXOR }, /* 31 */
  104. { modrm, none2, TO_REG | B , iXOR }, /* 32 */
  105. { modrm, none2, TO_REG | NSP , iXOR }, /* 33 */
  106. { data1, axImp, B , iXOR }, /* 34 */
  107. { data2, axImp, 0 , iXOR }, /* 35 */
  108. { prefix, none2, 0 , (IC)rSS}, /* 36 */
  109. { none1, axImp, NOT_HLL | NO_SRC , iAAA }, /* 37 */
  110. { modrm, none2, B , iCMP }, /* 38 */
  111. { modrm, none2, NSP , iCMP }, /* 39 */
  112. { modrm, none2, TO_REG | B , iCMP }, /* 3A */
  113. { modrm, none2, TO_REG | NSP , iCMP }, /* 3B */
  114. { data1, axImp, B , iCMP }, /* 3C */
  115. { data2, axImp, 0 , iCMP }, /* 3D */
  116. { prefix, none2, 0 , (IC)rDS}, /* 3E */
  117. { none1, axImp, NOT_HLL | NO_SRC , iAAS }, /* 3F */
  118. { regop, none2, 0 , iINC }, /* 40 */
  119. { regop, none2, 0 , iINC }, /* 41 */
  120. { regop, none2, 0 , iINC }, /* 42 */
  121. { regop, none2, 0 , iINC }, /* 43 */
  122. { regop, none2, NOT_HLL , iINC }, /* 44 */
  123. { regop, none2, 0 , iINC }, /* 45 */
  124. { regop, none2, 0 , iINC }, /* 46 */
  125. { regop, none2, 0 , iINC }, /* 47 */
  126. { regop, none2, 0 , iDEC }, /* 48 */
  127. { regop, none2, 0 , iDEC }, /* 49 */
  128. { regop, none2, 0 , iDEC }, /* 4A */
  129. { regop, none2, 0 , iDEC }, /* 4B */
  130. { regop, none2, NOT_HLL , iDEC }, /* 4C */
  131. { regop, none2, 0 , iDEC }, /* 4D */
  132. { regop, none2, 0 , iDEC }, /* 4E */
  133. { regop, none2, 0 , iDEC }, /* 4F */
  134. { regop, none2, NO_SRC , iPUSH }, /* 50 */
  135. { regop, none2, NO_SRC , iPUSH }, /* 51 */
  136. { regop, none2, NO_SRC , iPUSH }, /* 52 */
  137. { regop, none2, NO_SRC , iPUSH }, /* 53 */
  138. { regop, none2, NOT_HLL | NO_SRC , iPUSH }, /* 54 */
  139. { regop, none2, NO_SRC , iPUSH }, /* 55 */
  140. { regop, none2, NO_SRC , iPUSH }, /* 56 */
  141. { regop, none2, NO_SRC , iPUSH }, /* 57 */
  142. { regop, none2, NO_SRC , iPOP }, /* 58 */
  143. { regop, none2, NO_SRC , iPOP }, /* 59 */
  144. { regop, none2, NO_SRC , iPOP }, /* 5A */
  145. { regop, none2, NO_SRC , iPOP }, /* 5B */
  146. { regop, none2, NOT_HLL | NO_SRC , iPOP }, /* 5C */
  147. { regop, none2, NO_SRC , iPOP }, /* 5D */
  148. { regop, none2, NO_SRC , iPOP }, /* 5E */
  149. { regop, none2, NO_SRC , iPOP }, /* 5F */
  150. { none1, none2, NOT_HLL | NO_OPS , iPUSHA}, /* 60 */
  151. { none1, none2, NOT_HLL | NO_OPS , iPOPA }, /* 61 */
  152. { memOnly, modrm, TO_REG | NSP , iBOUND}, /* 62 */
  153. { none1, none2, OP386 , iZERO }, /* 63 */
  154. { none1, none2, OP386 , iZERO }, /* 64 */
  155. { none1, none2, OP386 , iZERO }, /* 65 */
  156. { none1, none2, OP386 , iZERO }, /* 66 */
  157. { none1, none2, OP386 , iZERO }, /* 67 */
  158. { data2, none2, NO_SRC , iPUSH }, /* 68 */
  159. { modrm, data2, TO_REG | NSP , iIMUL }, /* 69 */
  160. { data1, none2, S_EXT | NO_SRC , iPUSH }, /* 6A */
  161. { modrm, data1, TO_REG | NSP | S_EXT , iIMUL }, /* 6B */
  162. { strop, memImp, NOT_HLL | B|IM_OPS , iINS }, /* 6C */
  163. { strop, memImp, NOT_HLL | IM_OPS , iINS }, /* 6D */
  164. { strop, memImp, NOT_HLL | B|IM_OPS , iOUTS }, /* 6E */
  165. { strop, memImp, NOT_HLL | IM_OPS , iOUTS }, /* 6F */
  166. { dispS, none2, NOT_HLL , iJO }, /* 70 */
  167. { dispS, none2, NOT_HLL , iJNO }, /* 71 */
  168. { dispS, none2, 0 , iJB }, /* 72 */
  169. { dispS, none2, 0 , iJAE }, /* 73 */
  170. { dispS, none2, 0 , iJE }, /* 74 */
  171. { dispS, none2, 0 , iJNE }, /* 75 */
  172. { dispS, none2, 0 , iJBE }, /* 76 */
  173. { dispS, none2, 0 , iJA }, /* 77 */
  174. { dispS, none2, 0 , iJS }, /* 78 */
  175. { dispS, none2, 0 , iJNS }, /* 79 */
  176. { dispS, none2, NOT_HLL , iJP }, /* 7A */
  177. { dispS, none2, NOT_HLL , iJNP }, /* 7B */
  178. { dispS, none2, 0 , iJL }, /* 7C */
  179. { dispS, none2, 0 , iJGE }, /* 7D */
  180. { dispS, none2, 0 , iJLE }, /* 7E */
  181. { dispS, none2, 0 , iJG }, /* 7F */
  182. { immed, data1, B , iZERO }, /* 80 */
  183. { immed, data2, NSP , iZERO }, /* 81 */
  184. { immed, data1, B , iZERO }, /* 82 */ /* ?? */
  185. { immed, data1, NSP | S_EXT , iZERO }, /* 83 */
  186. { modrm, none2, TO_REG | B , iTEST }, /* 84 */
  187. { modrm, none2, TO_REG | NSP , iTEST }, /* 85 */
  188. { modrm, none2, TO_REG | B , iXCHG }, /* 86 */
  189. { modrm, none2, TO_REG | NSP , iXCHG }, /* 87 */
  190. { modrm, none2, B , iMOV }, /* 88 */
  191. { modrm, none2, 0 , iMOV }, /* 89 */
  192. { modrm, none2, TO_REG | B , iMOV }, /* 8A */
  193. { modrm, none2, TO_REG , iMOV }, /* 8B */
  194. { segrm, none2, NSP , iMOV }, /* 8C */
  195. { memOnly, modrm, TO_REG | NSP , iLEA }, /* 8D */
  196. { segrm, none2, TO_REG | NSP , iMOV }, /* 8E */
  197. { memReg0, none2, NO_SRC , iPOP }, /* 8F */
  198. { none1, none2, NO_OPS , iNOP }, /* 90 */
  199. { regop, axImp, 0 , iXCHG }, /* 91 */
  200. { regop, axImp, 0 , iXCHG }, /* 92 */
  201. { regop, axImp, 0 , iXCHG }, /* 93 */
  202. { regop, axImp, NOT_HLL , iXCHG }, /* 94 */
  203. { regop, axImp, 0 , iXCHG }, /* 95 */
  204. { regop, axImp, 0 , iXCHG }, /* 96 */
  205. { regop, axImp, 0 , iXCHG }, /* 97 */
  206. { alImp, axImp, SRC_B | S_EXT , iSIGNEX}, /* 98 */
  207. {axSrcIm, axImp, IM_DST | S_EXT , iSIGNEX}, /* 99 */
  208. { dispF, none2, 0 , iCALLF }, /* 9A */
  209. { none1, none2, FLOAT_OP| NO_OPS , iWAIT }, /* 9B */
  210. { none1, none2, NOT_HLL | NO_OPS , iPUSHF}, /* 9C */
  211. { none1, none2, NOT_HLL | NO_OPS , iPOPF }, /* 9D */
  212. { none1, none2, NOT_HLL | NO_OPS , iSAHF }, /* 9E */
  213. { none1, none2, NOT_HLL | NO_OPS , iLAHF }, /* 9F */
  214. { dispM, axImp, B , iMOV }, /* A0 */
  215. { dispM, axImp, 0 , iMOV }, /* A1 */
  216. { dispM, axImp, TO_REG | B , iMOV }, /* A2 */
  217. { dispM, axImp, TO_REG , iMOV }, /* A3 */
  218. { strop, memImp, B | IM_OPS , iMOVS }, /* A4 */
  219. { strop, memImp, IM_OPS , iMOVS }, /* A5 */
  220. { strop, memImp, B | IM_OPS , iCMPS }, /* A6 */
  221. { strop, memImp, IM_OPS , iCMPS }, /* A7 */
  222. { data1, axImp, B , iTEST }, /* A8 */
  223. { data2, axImp, 0 , iTEST }, /* A9 */
  224. { strop, memImp, B | IM_OPS , iSTOS }, /* AA */
  225. { strop, memImp, IM_OPS , iSTOS }, /* AB */
  226. { strop, memImp, B | IM_OPS , iLODS }, /* AC */
  227. { strop, memImp, IM_OPS , iLODS }, /* AD */
  228. { strop, memImp, B | IM_OPS , iSCAS }, /* AE */
  229. { strop, memImp, IM_OPS , iSCAS }, /* AF */
  230. { regop, data1, B , iMOV }, /* B0 */
  231. { regop, data1, B , iMOV }, /* B1 */
  232. { regop, data1, B , iMOV }, /* B2 */
  233. { regop, data1, B , iMOV }, /* B3 */
  234. { regop, data1, B , iMOV }, /* B4 */
  235. { regop, data1, B , iMOV }, /* B5 */
  236. { regop, data1, B , iMOV }, /* B6 */
  237. { regop, data1, B , iMOV }, /* B7 */
  238. { regop, data2, 0 , iMOV }, /* B8 */
  239. { regop, data2, 0 , iMOV }, /* B9 */
  240. { regop, data2, 0 , iMOV }, /* BA */
  241. { regop, data2, 0 , iMOV }, /* BB */
  242. { regop, data2, NOT_HLL , iMOV }, /* BC */
  243. { regop, data2, 0 , iMOV }, /* BD */
  244. { regop, data2, 0 , iMOV }, /* BE */
  245. { regop, data2, 0 , iMOV }, /* BF */
  246. { shift, data1, B , iZERO }, /* C0 */
  247. { shift, data1, NSP | SRC_B , iZERO }, /* C1 */
  248. { data2, none2, 0 , iRET }, /* C2 */
  249. { none1, none2, NO_OPS , iRET }, /* C3 */
  250. { memOnly, modrm, TO_REG | NSP , iLES }, /* C4 */
  251. { memOnly, modrm, TO_REG | NSP , iLDS }, /* C5 */
  252. { memReg0, data1, B , iMOV }, /* C6 */
  253. { memReg0, data2, 0 , iMOV }, /* C7 */
  254. { data2, data1, 0 , iENTER}, /* C8 */
  255. { none1, none2, NO_OPS , iLEAVE}, /* C9 */
  256. { data2, none2, 0 , iRETF }, /* CA */
  257. { none1, none2, NO_OPS , iRETF }, /* CB */
  258. { const3, none2, NOT_HLL , iINT }, /* CC */
  259. { data1,checkInt, NOT_HLL , iINT }, /* CD */
  260. { none1, none2, NOT_HLL | NO_OPS , iINTO }, /* CE */
  261. { none1, none2, NOT_HLL | NO_OPS , iIRET }, /* Cf */
  262. { shift, const1, B , iZERO }, /* D0 */
  263. { shift, const1, SRC_B , iZERO }, /* D1 */
  264. { shift, none1, B , iZERO }, /* D2 */
  265. { shift, none1, SRC_B , iZERO }, /* D3 */
  266. { data1, axImp, NOT_HLL , iAAM }, /* D4 */
  267. { data1, axImp, NOT_HLL , iAAD }, /* D5 */
  268. { none1, none2, 0 , iZERO }, /* D6 */
  269. { memImp, axImp, NOT_HLL | B| IM_OPS , iXLAT }, /* D7 */
  270. { escop, none2, FLOAT_OP , iESC }, /* D8 */
  271. { escop, none2, FLOAT_OP , iESC }, /* D9 */
  272. { escop, none2, FLOAT_OP , iESC }, /* DA */
  273. { escop, none2, FLOAT_OP , iESC }, /* DB */
  274. { escop, none2, FLOAT_OP , iESC }, /* DC */
  275. { escop, none2, FLOAT_OP , iESC }, /* DD */
  276. { escop, none2, FLOAT_OP , iESC }, /* DE */
  277. { escop, none2, FLOAT_OP , iESC }, /* Df */
  278. { dispS, none2, 0 , iLOOPNE}, /* E0 */
  279. { dispS, none2, 0 , iLOOPE}, /* E1 */
  280. { dispS, none2, 0 , iLOOP }, /* E2 */
  281. { dispS, none2, 0 , iJCXZ }, /* E3 */
  282. { data1, axImp, NOT_HLL | B|NO_SRC , iIN }, /* E4 */
  283. { data1, axImp, NOT_HLL | NO_SRC , iIN }, /* E5 */
  284. { data1, axImp, NOT_HLL | B|NO_SRC , iOUT }, /* E6 */
  285. { data1, axImp, NOT_HLL | NO_SRC , iOUT }, /* E7 */
  286. { dispN, none2, 0 , iCALL }, /* E8 */
  287. { dispN, none2, 0 , iJMP }, /* E9 */
  288. { dispF, none2, 0 , iJMPF }, /* EA */
  289. { dispS, none2, 0 , iJMP }, /* EB */
  290. { none1, axImp, NOT_HLL | B|NO_SRC , iIN }, /* EC */
  291. { none1, axImp, NOT_HLL | NO_SRC , iIN }, /* ED */
  292. { none1, axImp, NOT_HLL | B|NO_SRC , iOUT }, /* EE */
  293. { none1, axImp, NOT_HLL | NO_SRC , iOUT }, /* EF */
  294. { none1, none2, NOT_HLL | NO_OPS , iLOCK }, /* F0 */
  295. { none1, none2, 0 , iZERO }, /* F1 */
  296. { prefix, none2, 0 , iREPNE}, /* F2 */
  297. { prefix, none2, 0 , iREPE }, /* F3 */
  298. { none1, none2, NOT_HLL | NO_OPS , iHLT }, /* F4 */
  299. { none1, none2, NO_OPS , iCMC }, /* F5 */
  300. { arith, none1, B , iZERO }, /* F6 */
  301. { arith, none1, NSP , iZERO }, /* F7 */
  302. { none1, none2, NO_OPS , iCLC }, /* F8 */
  303. { none1, none2, NO_OPS , iSTC }, /* F9 */
  304. { none1, none2, NOT_HLL | NO_OPS , iCLI }, /* FA */
  305. { none1, none2, NOT_HLL | NO_OPS , iSTI }, /* FB */
  306. { none1, none2, NO_OPS , iCLD }, /* FC */
  307. { none1, none2, NO_OPS , iSTD }, /* FD */
  308. { trans, none1, B , iZERO }, /* FE */
  309. { trans, none1, NSP , iZERO } /* FF */
  310. } ;
  311. static uint16_t SegPrefix, RepPrefix;
  312. static uint8_t *pInst; /* Ptr. to current uint8_t of instruction */
  313. static ICODE * pIcode; /* Ptr to Icode record filled in by scan() */
  314. /*****************************************************************************
  315. Scans one machine instruction at offset ip in prog.Image and returns error.
  316. At the same time, fill in low-level icode details for the scanned inst.
  317. ****************************************************************************/
  318. static void convertUsedFlags(x86_insn_t &from,ICODE &to)
  319. {
  320. to.ll()->flagDU.d=0;
  321. to.ll()->flagDU.u=0;
  322. if(from.containsFlag(insn_eflag_carry,from.flags_set))
  323. to.ll()->flagDU.d |= Cf;
  324. if(from.containsFlag(insn_eflag_sign,from.flags_set))
  325. to.ll()->flagDU.d |= Sf;
  326. if(from.containsFlag(insn_eflag_zero,from.flags_set))
  327. to.ll()->flagDU.d |= Zf;
  328. if(from.containsFlag(insn_eflag_direction,from.flags_set))
  329. to.ll()->flagDU.d |= Df;
  330. if(from.containsFlag(insn_eflag_carry,from.flags_tested))
  331. to.ll()->flagDU.u |= Cf;
  332. if(from.containsFlag(insn_eflag_sign,from.flags_tested))
  333. to.ll()->flagDU.u |= Sf;
  334. if(from.containsFlag(insn_eflag_zero,from.flags_tested))
  335. to.ll()->flagDU.u |= Zf;
  336. if(from.containsFlag(insn_eflag_direction,from.flags_tested))
  337. to.ll()->flagDU.u |= Df;
  338. }
  339. /****************************************************************************
  340. Checks for int 34 to int 3B - if so, converts to ESC nn instruction
  341. ****************************************************************************/
  342. static void fixFloatEmulation(x86_insn_t &insn)
  343. {
  344. if(insn.group!=x86_insn_t::insn_interrupt)
  345. return;
  346. PROG &prog(Project::get()->prog);
  347. uint16_t wOp=insn.x86_get_imm()->data.word;
  348. if ((wOp < 0x34) || (wOp > 0x3B))
  349. return;
  350. uint8_t buf[16];
  351. /* This is a Borland/Microsoft floating point emulation instruction.
  352. Treat as if it is an ESC opcode */
  353. int actual_valid_bytes=std::min(16U,prog.cbImage-insn.offset);
  354. memcpy(buf,prog.Image+insn.offset,actual_valid_bytes);
  355. X86_Disasm ds(opt_16_bit);
  356. x86_insn_t patched_insn;
  357. //patch actual instruction into buffer;
  358. buf[1] = wOp-0x34+0xD8;
  359. ds.x86_disasm(buf,actual_valid_bytes,0,1,&patched_insn);
  360. patched_insn.addr = insn.addr; // actual address
  361. patched_insn.offset = insn.offset; // actual offset
  362. insn = patched_insn;
  363. insn.size += 1; // to account for emulator call INT
  364. }
  365. int disassembleOneLibDisasm(uint32_t ip,x86_insn_t &l)
  366. {
  367. PROG &prog(Project::get()->prog);
  368. X86_Disasm ds(opt_16_bit);
  369. int cnt=ds.x86_disasm(prog.Image,prog.cbImage,0,ip,&l);
  370. if(cnt && l.is_valid())
  371. {
  372. fixFloatEmulation(l); //can change 'l'
  373. }
  374. if(l.is_valid())
  375. return l.size;
  376. return 0;
  377. }
  378. eReg convertRegister(const x86_reg_t &reg)
  379. {
  380. eReg regmap[]={ rUNDEF,
  381. rUNDEF,rUNDEF,rUNDEF,rUNDEF, //eax ecx ebx edx
  382. rUNDEF,rUNDEF,rUNDEF,rUNDEF, //esp ebp esi edi
  383. rAX,rCX,rDX,rBX,
  384. rSP,rBP,rSI,rDI,
  385. rAL,rCL,rDL,rBL,
  386. rAH,rCH,rDH,rBH
  387. };
  388. assert(reg.id<sizeof(regmap)/sizeof(eReg));
  389. return regmap[reg.id];
  390. }
  391. LLOperand convertOperand(const x86_op_t &from)
  392. {
  393. switch(from.type)
  394. {
  395. case op_unused:
  396. break;
  397. case op_register:
  398. return LLOperand::CreateReg2(convertRegister(from.data.reg));
  399. case op_immediate:
  400. return LLOperand::CreateImm2(from.data.sdword);
  401. default:
  402. fprintf(stderr,"convertOperand does not know how to convert %d\n",from.type);
  403. }
  404. return LLOperand::CreateImm2(0);
  405. }
  406. eErrorId scan(uint32_t ip, ICODE &p)
  407. {
  408. PROG &prog(Project::get()->prog);
  409. int op;
  410. p = ICODE();
  411. p.type = LOW_LEVEL;
  412. p.ll()->label = ip; /* ip is absolute offset into image*/
  413. if (ip >= (uint32_t)prog.cbImage)
  414. {
  415. return (IP_OUT_OF_RANGE);
  416. }
  417. int cnt=disassembleOneLibDisasm(ip,p.insn);
  418. if(cnt)
  419. {
  420. convertUsedFlags(p.insn,p);
  421. }
  422. SegPrefix = RepPrefix = 0;
  423. pInst = prog.Image + ip;
  424. pIcode = &p;
  425. do
  426. {
  427. op = *pInst++; /* First state - trivial */
  428. /* Convert to Icode.opcode */
  429. p.ll()->set(stateTable[op].opcode,stateTable[op].flg & ICODEMASK);
  430. (*stateTable[op].state1)(op); /* Second state */
  431. (*stateTable[op].state2)(op); /* Third state */
  432. } while (stateTable[op].state1 == prefix); /* Loop if prefix */
  433. if (p.ll()->getOpcode())
  434. {
  435. /* Save bytes of image used */
  436. p.ll()->numBytes = (uint8_t)((pInst - prog.Image) - ip);
  437. if(p.insn.is_valid())
  438. assert(p.ll()->numBytes == p.insn.size);
  439. return ((SegPrefix)? FUNNY_SEGOVR: /* Seg. Override invalid */
  440. (RepPrefix ? FUNNY_REP: NO_ERR));/* REP prefix invalid */
  441. }
  442. /* Else opcode error */
  443. return ((stateTable[op].flg & OP386)? INVALID_386OP: INVALID_OPCODE);
  444. }
  445. /***************************************************************************
  446. relocItem - returns true if uint16_t pointed at is in relocation table
  447. **************************************************************************/
  448. static bool relocItem(uint8_t *p)
  449. {
  450. PROG &prog(Project::get()->prog);
  451. int i;
  452. uint32_t off = p - prog.Image;
  453. for (i = 0; i < prog.cReloc; i++)
  454. if (prog.relocTable[i] == off)
  455. return true;
  456. return false;
  457. }
  458. /***************************************************************************
  459. getWord - returns next uint16_t from image
  460. **************************************************************************/
  461. static uint16_t getWord(void)
  462. {
  463. uint16_t w = LH(pInst);
  464. pInst += 2;
  465. return w;
  466. }
  467. /****************************************************************************
  468. signex - returns uint8_t sign extended to int
  469. ***************************************************************************/
  470. static int signex(uint8_t b)
  471. {
  472. long s = b;
  473. return ((b & 0x80)? (int)(0xFFFFFF00 | s): (int)s);
  474. }
  475. /****************************************************************************
  476. * setAddress - Updates the source or destination field for the current
  477. * icode, based on fdst and the TO_REG flag.
  478. * Note: fdst == true is for the r/m part of the field (dest, unless TO_REG)
  479. * fdst == false is for reg part of the field
  480. ***************************************************************************/
  481. static void setAddress(int i, boolT fdst, uint16_t seg, int16_t reg, uint16_t off)
  482. {
  483. LLOperand *pm;
  484. /* If not to register (i.e. to r/m), and talking about r/m, then this is dest */
  485. pm = (!(stateTable[i].flg & TO_REG) == fdst) ?
  486. &pIcode->ll()->dst : &pIcode->ll()->src();
  487. /* Set segment. A later procedure (lookupAddr in proclist.c) will
  488. * provide the value of this segment in the field segValue. */
  489. if (seg) /* segment override */
  490. {
  491. pm->seg = pm->segOver = (eReg)seg;
  492. }
  493. else
  494. { /* no override, check indexed register */
  495. if ((reg >= INDEX_BX_SI) && (reg == INDEX_BP_SI || reg == INDEX_BP_DI || reg == INDEX_BP))
  496. {
  497. pm->seg = rSS; /* indexed on bp */
  498. }
  499. else
  500. {
  501. pm->seg = rDS; /* any other indexed reg */
  502. }
  503. }
  504. pm->regi = (eReg)reg;
  505. pm->off = (int16_t)off;
  506. if (reg && reg < INDEX_BX_SI && (stateTable[i].flg & B))
  507. {
  508. pm->regi = Machine_X86::subRegL(pm->regi);
  509. }
  510. if (seg) /* So we can catch invalid use of segment overrides */
  511. {
  512. SegPrefix = 0;
  513. }
  514. }
  515. /****************************************************************************
  516. rm - Decodes r/m part of modrm uint8_t for dst (unless TO_REG) part of icode
  517. ***************************************************************************/
  518. static void rm(int i)
  519. {
  520. uint8_t mod = *pInst >> 6;
  521. uint8_t rm = *pInst++ & 7;
  522. switch (mod) {
  523. case 0: /* No disp unless rm == 6 */
  524. if (rm == 6) {
  525. setAddress(i, true, SegPrefix, 0, getWord());
  526. pIcode->ll()->setFlags(WORD_OFF);
  527. }
  528. else
  529. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, 0);
  530. break;
  531. case 1: /* 1 uint8_t disp */
  532. setAddress(i, true, SegPrefix, rm+INDEX_BX_SI, (uint16_t)signex(*pInst++));
  533. break;
  534. case 2: /* 2 uint8_t disp */
  535. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, getWord());
  536. pIcode->ll()->setFlags(WORD_OFF);
  537. break;
  538. case 3: /* reg */
  539. setAddress(i, true, 0, rm + rAX, 0);
  540. break;
  541. }
  542. if ((stateTable[i].flg & NSP) && (pIcode->ll()->src().getReg2()==rSP ||
  543. pIcode->ll()->dst.getReg2()==rSP))
  544. pIcode->ll()->setFlags(NOT_HLL);
  545. }
  546. /****************************************************************************
  547. modrm - Sets up src and dst from modrm uint8_t
  548. ***************************************************************************/
  549. static void modrm(int i)
  550. {
  551. setAddress(i, false, 0, REG(*pInst) + rAX, 0);
  552. rm(i);
  553. }
  554. /****************************************************************************
  555. segrm - seg encoded as reg of modrm
  556. ****************************************************************************/
  557. static void segrm(int i)
  558. {
  559. int reg = REG(*pInst) + rES;
  560. if (reg > rDS || (reg == rCS && (stateTable[i].flg & TO_REG)))
  561. pIcode->ll()->setOpcode((llIcode)0); // setCBW because it has that index
  562. else {
  563. setAddress(i, false, 0, (int16_t)reg, 0);
  564. rm(i);
  565. }
  566. }
  567. /****************************************************************************
  568. regop - src/dst reg encoded as low 3 bits of opcode
  569. ***************************************************************************/
  570. static void regop(int i)
  571. {
  572. setAddress(i, false, 0, ((int16_t)i & 7) + rAX, 0);
  573. pIcode->ll()->replaceDst(LLOperand::CreateReg2(pIcode->ll()->src().getReg2()));
  574. // pIcode->ll()->dst.regi = pIcode->ll()->src.regi;
  575. }
  576. /*****************************************************************************
  577. segop - seg encoded in middle of opcode
  578. *****************************************************************************/
  579. static void segop(int i)
  580. {
  581. setAddress(i, true, 0, (((int16_t)i & 0x18) >> 3) + rES, 0);
  582. }
  583. /****************************************************************************
  584. axImp - Plugs an implied AX dst
  585. ***************************************************************************/
  586. static void axImp(int i)
  587. {
  588. setAddress(i, true, 0, rAX, 0);
  589. }
  590. /* Implied AX source */
  591. static void axSrcIm (int )
  592. {
  593. pIcode->ll()->replaceSrc(rAX);//src.regi = rAX;
  594. }
  595. /* Implied AL source */
  596. static void alImp (int )
  597. {
  598. pIcode->ll()->replaceSrc(rAL);//src.regi = rAL;
  599. }
  600. /*****************************************************************************
  601. memImp - Plugs implied src memory operand with any segment override
  602. ****************************************************************************/
  603. static void memImp(int i)
  604. {
  605. setAddress(i, false, SegPrefix, 0, 0);
  606. }
  607. /****************************************************************************
  608. memOnly - Instruction is not valid if modrm refers to register (i.e. mod == 3)
  609. ***************************************************************************/
  610. static void memOnly(int )
  611. {
  612. if ((*pInst & 0xC0) == 0xC0)
  613. pIcode->ll()->setOpcode((llIcode)0);
  614. }
  615. /****************************************************************************
  616. memReg0 - modrm for 'memOnly' and Reg field must also be 0
  617. ****************************************************************************/
  618. static void memReg0(int i)
  619. {
  620. if (REG(*pInst) || (*pInst & 0xC0) == 0xC0)
  621. pIcode->ll()->setOpcode((llIcode)0);
  622. else
  623. rm(i);
  624. }
  625. /***************************************************************************
  626. immed - Sets up dst and opcode from modrm uint8_t
  627. **************************************************************************/
  628. static void immed(int i)
  629. {
  630. static llIcode immedTable[8] = {iADD, iOR, iADC, iSBB, iAND, iSUB, iXOR, iCMP};
  631. pIcode->ll()->setOpcode(immedTable[REG(*pInst)]) ;
  632. rm(i);
  633. if (pIcode->ll()->getOpcode() == iADD || pIcode->ll()->getOpcode() == iSUB)
  634. pIcode->ll()->clrFlags(NOT_HLL); /* Allow ADD/SUB SP, immed */
  635. }
  636. /****************************************************************************
  637. shift - Sets up dst and opcode from modrm uint8_t
  638. ***************************************************************************/
  639. static void shift(int i)
  640. {
  641. static llIcode shiftTable[8] =
  642. {
  643. (llIcode)iROL, (llIcode)iROR, (llIcode)iRCL, (llIcode)iRCR,
  644. (llIcode)iSHL, (llIcode)iSHR, (llIcode)0, (llIcode)iSAR};
  645. pIcode->ll()->setOpcode(shiftTable[REG(*pInst)]);
  646. rm(i);
  647. pIcode->ll()->replaceSrc(rCL); //src.regi =
  648. }
  649. /****************************************************************************
  650. trans - Sets up dst and opcode from modrm uint8_t
  651. ***************************************************************************/
  652. static void trans(int i)
  653. {
  654. static llIcode transTable[8] =
  655. {
  656. (llIcode)iINC, (llIcode)iDEC, (llIcode)iCALL, (llIcode)iCALLF,
  657. (llIcode)iJMP, (llIcode)iJMPF,(llIcode)iPUSH, (llIcode)0
  658. };
  659. LLInst *ll = pIcode->ll();
  660. if ((uint8_t)REG(*pInst) < 2 || !(stateTable[i].flg & B)) { /* INC & DEC */
  661. ll->setOpcode(transTable[REG(*pInst)]); /* valid on bytes */
  662. rm(i);
  663. ll->replaceSrc( pIcode->ll()->dst );
  664. if (ll->match(iJMP) || ll->match(iCALL) || ll->match(iCALLF))
  665. ll->setFlags(NO_OPS);
  666. else if (ll->match(iINC) || ll->match(iPUSH) || ll->match(iDEC))
  667. ll->setFlags(NO_SRC);
  668. }
  669. }
  670. /****************************************************************************
  671. arith - Sets up dst and opcode from modrm uint8_t
  672. ****************************************************************************/
  673. static void arith(int i)
  674. {
  675. uint8_t opcode;
  676. static llIcode arithTable[8] =
  677. {
  678. iTEST , (llIcode)0, iNOT, iNEG,
  679. iMUL , iIMUL, iDIV, iIDIV
  680. };
  681. opcode = arithTable[REG(*pInst)];
  682. pIcode->ll()->setOpcode((llIcode)opcode);
  683. rm(i);
  684. if (opcode == iTEST)
  685. {
  686. if (stateTable[i].flg & B)
  687. data1(i);
  688. else
  689. data2(i);
  690. }
  691. else if (!(opcode == iNOT || opcode == iNEG))
  692. {
  693. pIcode->ll()->replaceSrc( pIcode->ll()->dst );
  694. setAddress(i, true, 0, rAX, 0); /* dst = AX */
  695. }
  696. else if (opcode == iNEG || opcode == iNOT)
  697. pIcode->ll()->setFlags(NO_SRC);
  698. if ((opcode == iDIV) || (opcode == iIDIV))
  699. {
  700. if ( not pIcode->ll()->testFlags(B) )
  701. pIcode->ll()->setFlags(IM_TMP_DST);
  702. }
  703. }
  704. /*****************************************************************************
  705. data1 - Sets up immed from 1 uint8_t data
  706. *****************************************************************************/
  707. static void data1(int i)
  708. {
  709. pIcode->ll()->replaceSrc(LLOperand::CreateImm2((stateTable[i].flg & S_EXT)? signex(*pInst++): *pInst++));
  710. pIcode->ll()->setFlags(I);
  711. }
  712. /*****************************************************************************
  713. data2 - Sets up immed from 2 uint8_t data
  714. ****************************************************************************/
  715. static void data2(int )
  716. {
  717. if (relocItem(pInst))
  718. pIcode->ll()->setFlags(SEG_IMMED);
  719. /* ENTER is a special case, it does not take a destination operand,
  720. * but this field is being used as the number of bytes to allocate
  721. * on the stack. The procedure level is stored in the immediate
  722. * field. There is no source operand; therefore, the flag flg is
  723. * set to NO_OPS. */
  724. if (pIcode->ll()->getOpcode() == iENTER)
  725. {
  726. pIcode->ll()->dst.off = getWord();
  727. pIcode->ll()->setFlags(NO_OPS);
  728. }
  729. else
  730. pIcode->ll()->replaceSrc(getWord());
  731. pIcode->ll()->setFlags(I);
  732. }
  733. /****************************************************************************
  734. dispM - 2 uint8_t offset without modrm (== mod 0, rm 6) (Note:TO_REG bits are
  735. reversed)
  736. ****************************************************************************/
  737. static void dispM(int i)
  738. {
  739. setAddress(i, false, SegPrefix, 0, getWord());
  740. }
  741. /****************************************************************************
  742. dispN - 2 uint8_t disp as immed relative to ip
  743. ****************************************************************************/
  744. static void dispN(int )
  745. {
  746. PROG &prog(Project::get()->prog);
  747. long off = (short)getWord(); /* Signed displacement */
  748. /* Note: the result of the subtraction could be between 32k and 64k, and
  749. still be positive; it is an offset from prog.Image. So this must be
  750. treated as unsigned */
  751. pIcode->ll()->replaceSrc((uint32_t)(off + (unsigned)(pInst - prog.Image)));
  752. pIcode->ll()->setFlags(I);
  753. }
  754. /***************************************************************************
  755. dispS - 1 uint8_t disp as immed relative to ip
  756. ***************************************************************************/
  757. static void dispS(int )
  758. {
  759. PROG &prog(Project::get()->prog);
  760. long off = signex(*pInst++); /* Signed displacement */
  761. pIcode->ll()->replaceSrc((uint32_t)(off + (unsigned)(pInst - prog.Image)));
  762. pIcode->ll()->setFlags(I);
  763. }
  764. /****************************************************************************
  765. dispF - 4 uint8_t disp as immed 20-bit target address
  766. ***************************************************************************/
  767. static void dispF(int )
  768. {
  769. uint32_t off = (unsigned)getWord();
  770. uint32_t seg = (unsigned)getWord();
  771. pIcode->ll()->replaceSrc(off + ((uint32_t)(unsigned)seg << 4));
  772. pIcode->ll()->setFlags(I);
  773. }
  774. /****************************************************************************
  775. prefix - picks up prefix uint8_t for following instruction (LOCK is ignored
  776. on purpose)
  777. ****************************************************************************/
  778. static void prefix(int )
  779. {
  780. if (pIcode->ll()->getOpcode() == iREPE || pIcode->ll()->getOpcode() == iREPNE)
  781. RepPrefix = pIcode->ll()->getOpcode();
  782. else
  783. SegPrefix = pIcode->ll()->getOpcode();
  784. }
  785. inline void BumpOpcode(LLInst &ll)
  786. {
  787. llIcode ic((llIcode)ll.getOpcode());
  788. ic = (llIcode)(((int)ic)+1); // Bump this icode via the int type
  789. ll.setOpcode(ic);
  790. }
  791. /*****************************************************************************
  792. strop - checks RepPrefix and converts string instructions accordingly
  793. *****************************************************************************/
  794. static void strop(int )
  795. {
  796. if (RepPrefix)
  797. {
  798. // pIcode->ll()->getOpcode() += ((pIcode->ll()->getOpcode() == iCMPS ||
  799. // pIcode->ll()->getOpcode() == iSCAS)
  800. // && RepPrefix == iREPE)? 2: 1;
  801. if ((pIcode->ll()->match(iCMPS) || pIcode->ll()->match(iSCAS) ) && RepPrefix == iREPE)
  802. BumpOpcode(*pIcode->ll()); // += 2
  803. BumpOpcode(*pIcode->ll()); // else += 1
  804. if (pIcode->ll()->match(iREP_LODS) )
  805. pIcode->ll()->setFlags(NOT_HLL);
  806. RepPrefix = 0;
  807. }
  808. }
  809. /***************************************************************************
  810. escop - esc operands
  811. ***************************************************************************/
  812. static void escop(int i)
  813. {
  814. pIcode->ll()->replaceSrc(REG(*pInst) + (uint32_t)((i & 7) << 3));
  815. pIcode->ll()->setFlags(I);
  816. rm(i);
  817. }
  818. /****************************************************************************
  819. const1
  820. ****************************************************************************/
  821. static void const1(int )
  822. {
  823. pIcode->ll()->replaceSrc(1);
  824. pIcode->ll()->setFlags(I);
  825. }
  826. /*****************************************************************************
  827. const3
  828. ****************************************************************************/
  829. static void const3(int )
  830. {
  831. pIcode->ll()->replaceSrc(3);
  832. pIcode->ll()->setFlags(I);
  833. }
  834. /****************************************************************************
  835. none1
  836. ****************************************************************************/
  837. static void none1(int )
  838. {
  839. }
  840. /****************************************************************************
  841. none2 - Sets the NO_OPS flag if the operand is immediate
  842. ****************************************************************************/
  843. static void none2(int )
  844. {
  845. if ( pIcode->ll()->testFlags(I) )
  846. pIcode->ll()->setFlags(NO_OPS);
  847. }
  848. /****************************************************************************
  849. Checks for int 34 to int 3B - if so, converts to ESC nn instruction
  850. ****************************************************************************/
  851. static void checkInt(int )
  852. {
  853. uint16_t wOp = (uint16_t) pIcode->ll()->src().getImm2();
  854. if ((wOp >= 0x34) && (wOp <= 0x3B))
  855. {
  856. /* This is a Borland/Microsoft floating point emulation instruction.
  857. Treat as if it is an ESC opcode */
  858. pIcode->ll()->replaceSrc(wOp - 0x34);
  859. pIcode->ll()->set(iESC,FLOAT_OP);
  860. escop(wOp - 0x34 + 0xD8);
  861. }
  862. }