ia32_reg.cpp 8.9 KB

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  1. #include <stdlib.h>
  2. #include <string.h>
  3. #include "ia32_reg.h"
  4. #include "ia32_insn.h"
  5. #define NUM_X86_REGS 92
  6. /* register sizes */
  7. #define REG_DWORD_SIZE 4
  8. #define REG_WORD_SIZE 2
  9. #define REG_BYTE_SIZE 1
  10. #define REG_MMX_SIZE 8
  11. #define REG_SIMD_SIZE 16
  12. #define REG_DEBUG_SIZE 4
  13. #define REG_CTRL_SIZE 4
  14. #define REG_TEST_SIZE 4
  15. #define REG_SEG_SIZE 2
  16. #define REG_FPU_SIZE 10
  17. #define REG_FLAGS_SIZE 4
  18. #define REG_FPCTRL_SIZE 2
  19. #define REG_FPSTATUS_SIZE 2
  20. #define REG_FPTAG_SIZE 2
  21. #define REG_EIP_SIZE 4
  22. #define REG_IP_SIZE 2
  23. /* REGISTER ALIAS TABLE:
  24. *
  25. * NOTE: the MMX register mapping is fixed to the physical registers
  26. * used by the FPU. The floating FP stack does not effect the location
  27. * of the MMX registers, so this aliasing is not 100% accurate.
  28. * */
  29. static struct {
  30. unsigned char alias; /* id of register this is an alias for */
  31. unsigned char shift; /* # of bits register must be shifted */
  32. } ia32_reg_aliases[] = {
  33. { 0,0 },
  34. { REG_DWORD_OFFSET, 0 }, /* al : 1 */
  35. { REG_DWORD_OFFSET, 8 }, /* ah : 2 */
  36. { REG_DWORD_OFFSET, 0 }, /* ax : 3 */
  37. { REG_DWORD_OFFSET + 1, 0 }, /* cl : 4 */
  38. { REG_DWORD_OFFSET + 1, 8 }, /* ch : 5 */
  39. { REG_DWORD_OFFSET + 1, 0 }, /* cx : 6 */
  40. { REG_DWORD_OFFSET + 2, 0 }, /* dl : 7 */
  41. { REG_DWORD_OFFSET + 2, 8 }, /* dh : 8 */
  42. { REG_DWORD_OFFSET + 2, 0 }, /* dx : 9 */
  43. { REG_DWORD_OFFSET + 3, 0 }, /* bl : 10 */
  44. { REG_DWORD_OFFSET + 3, 8 }, /* bh : 11 */
  45. { REG_DWORD_OFFSET + 3, 0 }, /* bx : 12 */
  46. { REG_DWORD_OFFSET + 4, 0 }, /* sp : 13 */
  47. { REG_DWORD_OFFSET + 5, 0 }, /* bp : 14 */
  48. { REG_DWORD_OFFSET + 6, 0 }, /* si : 15 */
  49. { REG_DWORD_OFFSET + 7, 0 }, /* di : 16 */
  50. { REG_EIP_INDEX, 0 }, /* ip : 17 */
  51. { REG_FPU_OFFSET, 0 }, /* mm0 : 18 */
  52. { REG_FPU_OFFSET + 1, 0 }, /* mm1 : 19 */
  53. { REG_FPU_OFFSET + 2, 0 }, /* mm2 : 20 */
  54. { REG_FPU_OFFSET + 3, 0 }, /* mm3 : 21 */
  55. { REG_FPU_OFFSET + 4, 0 }, /* mm4 : 22 */
  56. { REG_FPU_OFFSET + 5, 0 }, /* mm5 : 23 */
  57. { REG_FPU_OFFSET + 6, 0 }, /* mm6 : 24 */
  58. { REG_FPU_OFFSET + 7, 0 } /* mm7 : 25 */
  59. };
  60. /* REGISTER TABLE: size, type, and name of every register in the
  61. * CPU. Does not include MSRs since the are, after all,
  62. * model specific. */
  63. static struct {
  64. unsigned int size;
  65. enum x86_reg_type type;
  66. unsigned int alias;
  67. char mnemonic[8];
  68. } ia32_reg_table[NUM_X86_REGS + 2] = {
  69. { 0, reg_undef, 0, "" },
  70. /* REG_DWORD_OFFSET */
  71. { REG_DWORD_SIZE, (x86_reg_type)(reg_gen | reg_ret), 0, "eax" },
  72. { REG_DWORD_SIZE, (x86_reg_type)(reg_gen | reg_count), 0, "ecx" },
  73. { REG_DWORD_SIZE, reg_gen, 0, "edx" },
  74. { REG_DWORD_SIZE, reg_gen, 0, "ebx" },
  75. /* REG_ESP_INDEX */
  76. { REG_DWORD_SIZE, (x86_reg_type)(reg_gen | reg_sp), 0, "esp" },
  77. { REG_DWORD_SIZE, (x86_reg_type)(reg_gen | reg_fp), 0, "ebp" },
  78. { REG_DWORD_SIZE, (x86_reg_type)(reg_gen | reg_src), 0, "esi" },
  79. { REG_DWORD_SIZE, (x86_reg_type)(reg_gen | reg_dest), 0, "edi" },
  80. /* REG_WORD_OFFSET */
  81. { REG_WORD_SIZE, (x86_reg_type)(reg_gen | reg_ret), 3, "ax" },
  82. { REG_WORD_SIZE, (x86_reg_type)(reg_gen | reg_count), 6, "cx" },
  83. { REG_WORD_SIZE, reg_gen, 9, "dx" },
  84. { REG_WORD_SIZE, reg_gen, 12, "bx" },
  85. { REG_WORD_SIZE, (x86_reg_type)(reg_gen | reg_sp), 13, "sp" },
  86. { REG_WORD_SIZE, (x86_reg_type)(reg_gen | reg_fp), 14, "bp" },
  87. { REG_WORD_SIZE, (x86_reg_type)(reg_gen | reg_src), 15, "si" },
  88. { REG_WORD_SIZE, (x86_reg_type)(reg_gen | reg_dest), 16, "di" },
  89. /* REG_BYTE_OFFSET */
  90. { REG_BYTE_SIZE, reg_gen, 1, "al" },
  91. { REG_BYTE_SIZE, reg_gen, 4, "cl" },
  92. { REG_BYTE_SIZE, reg_gen, 7, "dl" },
  93. { REG_BYTE_SIZE, reg_gen, 10, "bl" },
  94. { REG_BYTE_SIZE, reg_gen, 2, "ah" },
  95. { REG_BYTE_SIZE, reg_gen, 5, "ch" },
  96. { REG_BYTE_SIZE, reg_gen, 8, "dh" },
  97. { REG_BYTE_SIZE, reg_gen, 11, "bh" },
  98. /* REG_MMX_OFFSET */
  99. { REG_MMX_SIZE, reg_simd, 18, "mm0" },
  100. { REG_MMX_SIZE, reg_simd, 19, "mm1" },
  101. { REG_MMX_SIZE, reg_simd, 20, "mm2" },
  102. { REG_MMX_SIZE, reg_simd, 21, "mm3" },
  103. { REG_MMX_SIZE, reg_simd, 22, "mm4" },
  104. { REG_MMX_SIZE, reg_simd, 23, "mm5" },
  105. { REG_MMX_SIZE, reg_simd, 24, "mm6" },
  106. { REG_MMX_SIZE, reg_simd, 25, "mm7" },
  107. /* REG_SIMD_OFFSET */
  108. { REG_SIMD_SIZE, reg_simd, 0, "xmm0" },
  109. { REG_SIMD_SIZE, reg_simd, 0, "xmm1" },
  110. { REG_SIMD_SIZE, reg_simd, 0, "xmm2" },
  111. { REG_SIMD_SIZE, reg_simd, 0, "xmm3" },
  112. { REG_SIMD_SIZE, reg_simd, 0, "xmm4" },
  113. { REG_SIMD_SIZE, reg_simd, 0, "xmm5" },
  114. { REG_SIMD_SIZE, reg_simd, 0, "xmm6" },
  115. { REG_SIMD_SIZE, reg_simd, 0, "xmm7" },
  116. /* REG_DEBUG_OFFSET */
  117. { REG_DEBUG_SIZE, reg_sys, 0, "dr0" },
  118. { REG_DEBUG_SIZE, reg_sys, 0, "dr1" },
  119. { REG_DEBUG_SIZE, reg_sys, 0, "dr2" },
  120. { REG_DEBUG_SIZE, reg_sys, 0, "dr3" },
  121. { REG_DEBUG_SIZE, reg_sys, 0, "dr4" },
  122. { REG_DEBUG_SIZE, reg_sys, 0, "dr5" },
  123. { REG_DEBUG_SIZE, reg_sys, 0, "dr6" },
  124. { REG_DEBUG_SIZE, reg_sys, 0, "dr7" },
  125. /* REG_CTRL_OFFSET */
  126. { REG_CTRL_SIZE, reg_sys, 0, "cr0" },
  127. { REG_CTRL_SIZE, reg_sys, 0, "cr1" },
  128. { REG_CTRL_SIZE, reg_sys, 0, "cr2" },
  129. { REG_CTRL_SIZE, reg_sys, 0, "cr3" },
  130. { REG_CTRL_SIZE, reg_sys, 0, "cr4" },
  131. { REG_CTRL_SIZE, reg_sys, 0, "cr5" },
  132. { REG_CTRL_SIZE, reg_sys, 0, "cr6" },
  133. { REG_CTRL_SIZE, reg_sys, 0, "cr7" },
  134. /* REG_TEST_OFFSET */
  135. { REG_TEST_SIZE, reg_sys, 0, "tr0" },
  136. { REG_TEST_SIZE, reg_sys, 0, "tr1" },
  137. { REG_TEST_SIZE, reg_sys, 0, "tr2" },
  138. { REG_TEST_SIZE, reg_sys, 0, "tr3" },
  139. { REG_TEST_SIZE, reg_sys, 0, "tr4" },
  140. { REG_TEST_SIZE, reg_sys, 0, "tr5" },
  141. { REG_TEST_SIZE, reg_sys, 0, "tr6" },
  142. { REG_TEST_SIZE, reg_sys, 0, "tr7" },
  143. /* REG_SEG_OFFSET */
  144. { REG_SEG_SIZE, reg_seg, 0, "es" },
  145. { REG_SEG_SIZE, reg_seg, 0, "cs" },
  146. { REG_SEG_SIZE, reg_seg, 0, "ss" },
  147. { REG_SEG_SIZE, reg_seg, 0, "ds" },
  148. { REG_SEG_SIZE, reg_seg, 0, "fs" },
  149. { REG_SEG_SIZE, reg_seg, 0, "gs" },
  150. /* REG_LDTR_INDEX */
  151. { REG_DWORD_SIZE, reg_sys, 0, "ldtr" },
  152. /* REG_GDTR_INDEX */
  153. { REG_DWORD_SIZE, reg_sys, 0, "gdtr" },
  154. /* REG_FPU_OFFSET */
  155. { REG_FPU_SIZE, reg_fpu, 0, "st(0)" },
  156. { REG_FPU_SIZE, reg_fpu, 0, "st(1)" },
  157. { REG_FPU_SIZE, reg_fpu, 0, "st(2)" },
  158. { REG_FPU_SIZE, reg_fpu, 0, "st(3)" },
  159. { REG_FPU_SIZE, reg_fpu, 0, "st(4)" },
  160. { REG_FPU_SIZE, reg_fpu, 0, "st(5)" },
  161. { REG_FPU_SIZE, reg_fpu, 0, "st(6)" },
  162. { REG_FPU_SIZE, reg_fpu, 0, "st(7)" },
  163. /* REG_FLAGS_INDEX : 81 */
  164. { REG_FLAGS_SIZE, reg_cond, 0, "eflags" },
  165. /* REG_FPCTRL_INDEX : 82*/
  166. { REG_FPCTRL_SIZE, (x86_reg_type)(reg_fpu | reg_sys), 0, "fpctrl" },
  167. /* REG_FPSTATUS_INDEX : 83*/
  168. { REG_FPSTATUS_SIZE, (x86_reg_type)(reg_fpu | reg_sys), 0, "fpstat" },
  169. /* REG_FPTAG_INDEX : 84 */
  170. { REG_FPTAG_SIZE, (x86_reg_type)(reg_fpu | reg_sys), 0, "fptag" },
  171. /* REG_EIP_INDEX : 85 */
  172. { REG_EIP_SIZE, reg_pc, 0, "eip" },
  173. /* REG_IP_INDEX : 86 */
  174. { REG_IP_SIZE, reg_pc, 17, "ip" },
  175. /* REG_IDTR_INDEX : 87 */
  176. { REG_DWORD_SIZE, reg_sys, 0, "idtr" },
  177. /* REG_MXCSG_INDEX : SSE Control Reg : 88 */
  178. { REG_DWORD_SIZE, (x86_reg_type)(reg_sys | reg_simd), 0, "mxcsr" },
  179. /* REG_TR_INDEX : Task Register : 89 */
  180. { 16 + 64, reg_sys, 0, "tr" },
  181. /* REG_CSMSR_INDEX : SYSENTER_CS_MSR : 90 */
  182. { REG_DWORD_SIZE, reg_sys, 0, "cs_msr" },
  183. /* REG_ESPMSR_INDEX : SYSENTER_ESP_MSR : 91 */
  184. { REG_DWORD_SIZE, reg_sys, 0, "esp_msr" },
  185. /* REG_EIPMSR_INDEX : SYSENTER_EIP_MSR : 92 */
  186. { REG_DWORD_SIZE, reg_sys, 0, "eip_msr" },
  187. { 0,reg_undef,0,{0} }
  188. };
  189. static size_t sz_regtable = NUM_X86_REGS + 1;
  190. void ia32_handle_register( x86_reg_t *reg, size_t id ) {
  191. unsigned int alias;
  192. if (! id || id > sz_regtable ) {
  193. return;
  194. }
  195. memset( reg, 0, sizeof(x86_reg_t) );
  196. strncpy( reg->name, ia32_reg_table[id].mnemonic, MAX_REGNAME );
  197. reg->type = ia32_reg_table[id].type;
  198. reg->size = ia32_reg_table[id].size;
  199. alias = ia32_reg_table[id].alias;
  200. if ( alias ) {
  201. reg->alias = ia32_reg_aliases[alias].alias;
  202. reg->shift = ia32_reg_aliases[alias].shift;
  203. }
  204. reg->id = id;
  205. return;
  206. }
  207. size_t ia32_true_register_id( size_t id ) {
  208. size_t reg;
  209. if (! id || id > sz_regtable ) {
  210. return 0;
  211. }
  212. reg = id;
  213. if (ia32_reg_table[reg].alias) {
  214. reg = ia32_reg_aliases[ia32_reg_table[reg].alias].alias;
  215. }
  216. return reg;
  217. }