scanner.cpp 37 KB

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  1. /*****************************************************************************
  2. * dcc project scanner module
  3. * Implements a simple state driven scanner to convert 8086 machine code into
  4. * I-code
  5. * (C) Cristina Cifuentes, Jeff Ledermann
  6. ****************************************************************************/
  7. #include <cstring>
  8. #include "dcc.h"
  9. #include "scanner.h"
  10. static void rm(Int i);
  11. static void modrm(Int i);
  12. static void segrm(Int i);
  13. static void data1(Int i);
  14. static void data2(Int i);
  15. static void regop(Int i);
  16. static void segop(Int i);
  17. static void strop(Int i);
  18. static void escop(Int i);
  19. static void axImp(Int i);
  20. static void alImp(Int i);
  21. static void axSrcIm(Int i);
  22. static void memImp(Int i);
  23. static void memReg0(Int i);
  24. static void memOnly(Int i);
  25. static void dispM(Int i);
  26. static void dispS(Int i);
  27. static void dispN(Int i);
  28. static void dispF(Int i);
  29. static void prefix(Int i);
  30. static void immed(Int i);
  31. static void shift(Int i);
  32. static void arith(Int i);
  33. static void trans(Int i);
  34. static void const1(Int i);
  35. static void const3(Int i);
  36. static void none1(Int i);
  37. static void none2(Int i);
  38. static void checkInt(Int i);
  39. #define iZERO (llIcode)0 // For neatness
  40. #define IC llIcode
  41. static struct {
  42. void (*state1)(Int);
  43. void (*state2)(Int);
  44. flags32 flg;
  45. llIcode opcode;
  46. byte df;
  47. byte uf;
  48. } stateTable[] = {
  49. { modrm, none2, B , iADD , Sf | Zf | Cf , 0 }, /* 00 */
  50. { modrm, none2, 0 , iADD , Sf | Zf | Cf , 0 }, /* 01 */
  51. { modrm, none2, TO_REG | B , iADD , Sf | Zf | Cf , 0 }, /* 02 */
  52. { modrm, none2, TO_REG , iADD , Sf | Zf | Cf , 0 }, /* 03 */
  53. { data1, axImp, B , iADD , Sf | Zf | Cf , 0 }, /* 04 */
  54. { data2, axImp, 0 , iADD , Sf | Zf | Cf , 0 }, /* 05 */
  55. { segop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 06 */
  56. { segop, none2, NO_SRC , iPOP , 0 , 0 }, /* 07 */
  57. { modrm, none2, B , iOR , Sf | Zf | Cf , 0 }, /* 08 */
  58. { modrm, none2, NSP , iOR , Sf | Zf | Cf , 0 }, /* 09 */
  59. { modrm, none2, TO_REG | B , iOR , Sf | Zf | Cf , 0 }, /* 0A */
  60. { modrm, none2, TO_REG | NSP , iOR , Sf | Zf | Cf , 0 }, /* 0B */
  61. { data1, axImp, B , iOR , Sf | Zf | Cf , 0 }, /* 0C */
  62. { data2, axImp, 0 , iOR , Sf | Zf | Cf , 0 }, /* 0D */
  63. { segop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 0E */
  64. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 0F */
  65. { modrm, none2, B , iADC , Sf | Zf | Cf , Cf }, /* 10 */
  66. { modrm, none2, NSP , iADC , Sf | Zf | Cf , Cf }, /* 11 */
  67. { modrm, none2, TO_REG | B , iADC , Sf | Zf | Cf , Cf }, /* 12 */
  68. { modrm, none2, TO_REG | NSP , iADC , Sf | Zf | Cf , Cf }, /* 13 */
  69. { data1, axImp, B , iADC , Sf | Zf | Cf , Cf }, /* 14 */
  70. { data2, axImp, 0 , iADC , Sf | Zf | Cf , Cf }, /* 15 */
  71. { segop, none2, NOT_HLL | NO_SRC , iPUSH , 0 , 0 }, /* 16 */
  72. { segop, none2, NOT_HLL | NO_SRC , iPOP , 0 , 0 }, /* 17 */
  73. { modrm, none2, B , iSBB , Sf | Zf | Cf , Cf }, /* 18 */
  74. { modrm, none2, NSP , iSBB , Sf | Zf | Cf , Cf }, /* 19 */
  75. { modrm, none2, TO_REG | B , iSBB , Sf | Zf | Cf , Cf }, /* 1A */
  76. { modrm, none2, TO_REG | NSP , iSBB , Sf | Zf | Cf , Cf }, /* 1B */
  77. { data1, axImp, B , iSBB , Sf | Zf | Cf , Cf }, /* 1C */
  78. { data2, axImp, 0 , iSBB , Sf | Zf | Cf , Cf }, /* 1D */
  79. { segop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 1E */
  80. { segop, none2, NO_SRC , iPOP , 0 , 0 }, /* 1F */
  81. { modrm, none2, B , iAND , Sf | Zf | Cf , 0 }, /* 20 */
  82. { modrm, none2, NSP , iAND , Sf | Zf | Cf , 0 }, /* 21 */
  83. { modrm, none2, TO_REG | B , iAND , Sf | Zf | Cf , 0 }, /* 22 */
  84. { modrm, none2, TO_REG | NSP , iAND , Sf | Zf | Cf , 0 }, /* 23 */
  85. { data1, axImp, B , iAND , Sf | Zf | Cf , 0 }, /* 24 */
  86. { data2, axImp, 0 , iAND , Sf | Zf | Cf , 0 }, /* 25 */
  87. { prefix, none2, 0 , (IC)rES,0 , 0 }, /* 26 */
  88. { none1, axImp, NOT_HLL | B|NO_SRC , iDAA , Sf | Zf | Cf , 0 }, /* 27 */
  89. { modrm, none2, B , iSUB , Sf | Zf | Cf , 0 }, /* 28 */
  90. { modrm, none2, 0 , iSUB , Sf | Zf | Cf , 0 }, /* 29 */
  91. { modrm, none2, TO_REG | B , iSUB , Sf | Zf | Cf , 0 }, /* 2A */
  92. { modrm, none2, TO_REG , iSUB , Sf | Zf | Cf , 0 }, /* 2B */
  93. { data1, axImp, B , iSUB , Sf | Zf | Cf , 0 }, /* 2C */
  94. { data2, axImp, 0 , iSUB , Sf | Zf | Cf , 0 }, /* 2D */
  95. { prefix, none2, 0 , (IC)rCS,0 , 0 }, /* 2E */
  96. { none1, axImp, NOT_HLL | B|NO_SRC , iDAS , Sf | Zf | Cf , 0 }, /* 2F */
  97. { modrm, none2, B , iXOR , Sf | Zf | Cf , 0 }, /* 30 */
  98. { modrm, none2, NSP , iXOR , Sf | Zf | Cf , 0 }, /* 31 */
  99. { modrm, none2, TO_REG | B , iXOR , Sf | Zf | Cf , 0 }, /* 32 */
  100. { modrm, none2, TO_REG | NSP , iXOR , Sf | Zf | Cf , 0 }, /* 33 */
  101. { data1, axImp, B , iXOR , Sf | Zf | Cf , 0 }, /* 34 */
  102. { data2, axImp, 0 , iXOR , Sf | Zf | Cf , 0 }, /* 35 */
  103. { prefix, none2, 0 , (IC)rSS,0 , 0 }, /* 36 */
  104. { none1, axImp, NOT_HLL | NO_SRC , iAAA , Sf | Zf | Cf , 0 }, /* 37 */
  105. { modrm, none2, B , iCMP , Sf | Zf | Cf , 0 }, /* 38 */
  106. { modrm, none2, NSP , iCMP , Sf | Zf | Cf , 0 }, /* 39 */
  107. { modrm, none2, TO_REG | B , iCMP , Sf | Zf | Cf , 0 }, /* 3A */
  108. { modrm, none2, TO_REG | NSP , iCMP , Sf | Zf | Cf , 0 }, /* 3B */
  109. { data1, axImp, B , iCMP , Sf | Zf | Cf , 0 }, /* 3C */
  110. { data2, axImp, 0 , iCMP , Sf | Zf | Cf , 0 }, /* 3D */
  111. { prefix, none2, 0 , (IC)rDS,0 , 0 }, /* 3E */
  112. { none1, axImp, NOT_HLL | NO_SRC , iAAS , Sf | Zf | Cf , 0 }, /* 3F */
  113. { regop, none2, 0 , iINC , Sf | Zf, 0 }, /* 40 */
  114. { regop, none2, 0 , iINC , Sf | Zf, 0 }, /* 41 */
  115. { regop, none2, 0 , iINC , Sf | Zf, 0 }, /* 42 */
  116. { regop, none2, 0 , iINC , Sf | Zf, 0 }, /* 43 */
  117. { regop, none2, NOT_HLL , iINC , Sf | Zf, 0 }, /* 44 */
  118. { regop, none2, 0 , iINC , Sf | Zf, 0 }, /* 45 */
  119. { regop, none2, 0 , iINC , Sf | Zf, 0 }, /* 46 */
  120. { regop, none2, 0 , iINC , Sf | Zf, 0 }, /* 47 */
  121. { regop, none2, 0 , iDEC , Sf | Zf, 0 }, /* 48 */
  122. { regop, none2, 0 , iDEC , Sf | Zf, 0 }, /* 49 */
  123. { regop, none2, 0 , iDEC , Sf | Zf, 0 }, /* 4A */
  124. { regop, none2, 0 , iDEC , Sf | Zf, 0 }, /* 4B */
  125. { regop, none2, NOT_HLL , iDEC , Sf | Zf, 0 }, /* 4C */
  126. { regop, none2, 0 , iDEC , Sf | Zf, 0 }, /* 4D */
  127. { regop, none2, 0 , iDEC , Sf | Zf, 0 }, /* 4E */
  128. { regop, none2, 0 , iDEC , Sf | Zf, 0 }, /* 4F */
  129. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 50 */
  130. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 51 */
  131. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 52 */
  132. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 53 */
  133. { regop, none2, NOT_HLL | NO_SRC , iPUSH , 0 , 0 }, /* 54 */
  134. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 55 */
  135. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 56 */
  136. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 57 */
  137. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 58 */
  138. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 59 */
  139. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5A */
  140. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5B */
  141. { regop, none2, NOT_HLL | NO_SRC , iPOP , 0 , 0 }, /* 5C */
  142. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5D */
  143. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5E */
  144. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5F */
  145. { none1, none2, NOT_HLL | NO_OPS , iPUSHA, 0 , 0 }, /* 60 */
  146. { none1, none2, NOT_HLL | NO_OPS , iPOPA , 0 , 0 }, /* 61 */
  147. { memOnly, modrm, TO_REG | NSP , iBOUND, 0 , 0 }, /* 62 */
  148. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 63 */
  149. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 64 */
  150. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 65 */
  151. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 66 */
  152. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 67 */
  153. { data2, none2, NO_SRC , iPUSH , 0 , 0 }, /* 68 */
  154. { modrm, data2, TO_REG | NSP , iIMUL , Sf | Zf | Cf, 0 }, /* 69 */
  155. { data1, none2, S_EXT | NO_SRC , iPUSH , 0 , 0 }, /* 6A */
  156. { modrm, data1, TO_REG | NSP | S_EXT , iIMUL , Sf | Zf | Cf, 0 }, /* 6B */
  157. { strop, memImp, NOT_HLL | B|IM_OPS , iINS , 0 , Df }, /* 6C */
  158. { strop, memImp, NOT_HLL | IM_OPS , iINS , 0 , Df }, /* 6D */
  159. { strop, memImp, NOT_HLL | B|IM_OPS , iOUTS , 0 , Df }, /* 6E */
  160. { strop, memImp, NOT_HLL | IM_OPS , iOUTS , 0 , Df }, /* 6F */
  161. { dispS, none2, NOT_HLL , iJO , 0 , 0 }, /* 70 */
  162. { dispS, none2, NOT_HLL , iJNO , 0 , 0 }, /* 71 */
  163. { dispS, none2, 0 , iJB , 0 , Cf }, /* 72 */
  164. { dispS, none2, 0 , iJAE , 0 , Cf }, /* 73 */
  165. { dispS, none2, 0 , iJE , 0 , Zf }, /* 74 */
  166. { dispS, none2, 0 , iJNE , 0 , Zf }, /* 75 */
  167. { dispS, none2, 0 , iJBE , 0 , Zf | Cf }, /* 76 */
  168. { dispS, none2, 0 , iJA , 0 , Zf | Cf }, /* 77 */
  169. { dispS, none2, 0 , iJS , 0 , Sf }, /* 78 */
  170. { dispS, none2, 0 , iJNS , 0 , Sf }, /* 79 */
  171. { dispS, none2, NOT_HLL , iJP , 0 , 0 }, /* 7A */
  172. { dispS, none2, NOT_HLL , iJNP , 0 , 0 }, /* 7B */
  173. { dispS, none2, 0 , iJL , 0 , Sf }, /* 7C */
  174. { dispS, none2, 0 , iJGE , 0 , Sf }, /* 7D */
  175. { dispS, none2, 0 , iJLE , 0 , Sf | Zf }, /* 7E */
  176. { dispS, none2, 0 , iJG , 0 , Sf | Zf }, /* 7F */
  177. { immed, data1, B , iZERO , 0 , 0 }, /* 80 */
  178. { immed, data2, NSP , iZERO , 0 , 0 }, /* 81 */
  179. { immed, data1, B , iZERO , 0 , 0 }, /* 82 */ /* ?? */
  180. { immed, data1, NSP | S_EXT , iZERO , 0 , 0 }, /* 83 */
  181. { modrm, none2, TO_REG | B , iTEST , Sf | Zf | Cf, 0 }, /* 84 */
  182. { modrm, none2, TO_REG | NSP , iTEST , Sf | Zf | Cf, 0 }, /* 85 */
  183. { modrm, none2, TO_REG | B , iXCHG , 0 , 0 }, /* 86 */
  184. { modrm, none2, TO_REG | NSP , iXCHG , 0 , 0 }, /* 87 */
  185. { modrm, none2, B , iMOV , 0 , 0 }, /* 88 */
  186. { modrm, none2, 0 , iMOV , 0 , 0 }, /* 89 */
  187. { modrm, none2, TO_REG | B , iMOV , 0 , 0 }, /* 8A */
  188. { modrm, none2, TO_REG , iMOV , 0 , 0 }, /* 8B */
  189. { segrm, none2, NSP , iMOV , 0 , 0 }, /* 8C */
  190. { memOnly, modrm, TO_REG | NSP , iLEA , 0 , 0 }, /* 8D */
  191. { segrm, none2, TO_REG | NSP , iMOV , 0 , 0 }, /* 8E */
  192. { memReg0, none2, NO_SRC , iPOP , 0 , 0 }, /* 8F */
  193. { none1, none2, NO_OPS , iNOP , 0 , 0 }, /* 90 */
  194. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 91 */
  195. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 92 */
  196. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 93 */
  197. { regop, axImp, NOT_HLL , iXCHG , 0 , 0 }, /* 94 */
  198. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 95 */
  199. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 96 */
  200. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 97 */
  201. { alImp, axImp, SRC_B | S_EXT , iSIGNEX,0 , 0 }, /* 98 */
  202. {axSrcIm, axImp, IM_DST | S_EXT , iSIGNEX,0 , 0 }, /* 99 */
  203. { dispF, none2, 0 , iCALLF ,0 , 0 }, /* 9A */
  204. { none1, none2, FLOAT_OP| NO_OPS , iWAIT , 0 , 0 }, /* 9B */
  205. { none1, none2, NOT_HLL | NO_OPS , iPUSHF, 0 , 0 }, /* 9C */
  206. { none1, none2, NOT_HLL | NO_OPS , iPOPF , Sf | Zf | Cf | Df,}, /* 9D */
  207. { none1, none2, NOT_HLL | NO_OPS , iSAHF , Sf | Zf | Cf, 0 }, /* 9E */
  208. { none1, none2, NOT_HLL | NO_OPS , iLAHF , 0 , Sf | Zf | Cf }, /* 9F */
  209. { dispM, axImp, B , iMOV , 0 , 0 }, /* A0 */
  210. { dispM, axImp, 0 , iMOV , 0 , 0 }, /* A1 */
  211. { dispM, axImp, TO_REG | B , iMOV , 0 , 0 }, /* A2 */
  212. { dispM, axImp, TO_REG , iMOV , 0 , 0 }, /* A3 */
  213. { strop, memImp, B | IM_OPS , iMOVS , 0 , Df }, /* A4 */
  214. { strop, memImp, IM_OPS , iMOVS , 0 , Df }, /* A5 */
  215. { strop, memImp, B | IM_OPS , iCMPS , Sf | Zf | Cf, Df }, /* A6 */
  216. { strop, memImp, IM_OPS , iCMPS , Sf | Zf | Cf, Df }, /* A7 */
  217. { data1, axImp, B , iTEST , Sf | Zf | Cf, 0 }, /* A8 */
  218. { data2, axImp, 0 , iTEST , Sf | Zf | Cf, 0 }, /* A9 */
  219. { strop, memImp, B | IM_OPS , iSTOS , 0 , Df }, /* AA */
  220. { strop, memImp, IM_OPS , iSTOS , 0 , Df }, /* AB */
  221. { strop, memImp, B | IM_OPS , iLODS , 0 , Df }, /* AC */
  222. { strop, memImp, IM_OPS , iLODS , 0 , Df }, /* AD */
  223. { strop, memImp, B | IM_OPS , iSCAS , Sf | Zf | Cf, Df }, /* AE */
  224. { strop, memImp, IM_OPS , iSCAS , Sf | Zf | Cf, Df }, /* AF */
  225. { regop, data1, B , iMOV , 0 , 0 }, /* B0 */
  226. { regop, data1, B , iMOV , 0 , 0 }, /* B1 */
  227. { regop, data1, B , iMOV , 0 , 0 }, /* B2 */
  228. { regop, data1, B , iMOV , 0 , 0 }, /* B3 */
  229. { regop, data1, B , iMOV , 0 , 0 }, /* B4 */
  230. { regop, data1, B , iMOV , 0 , 0 }, /* B5 */
  231. { regop, data1, B , iMOV , 0 , 0 }, /* B6 */
  232. { regop, data1, B , iMOV , 0 , 0 }, /* B7 */
  233. { regop, data2, 0 , iMOV , 0 , 0 }, /* B8 */
  234. { regop, data2, 0 , iMOV , 0 , 0 }, /* B9 */
  235. { regop, data2, 0 , iMOV , 0 , 0 }, /* BA */
  236. { regop, data2, 0 , iMOV , 0 , 0 }, /* BB */
  237. { regop, data2, NOT_HLL , iMOV , 0 , 0 }, /* BC */
  238. { regop, data2, 0 , iMOV , 0 , 0 }, /* BD */
  239. { regop, data2, 0 , iMOV , 0 , 0 }, /* BE */
  240. { regop, data2, 0 , iMOV , 0 , 0 }, /* BF */
  241. { shift, data1, B , iZERO , 0 , 0 }, /* C0 */
  242. { shift, data1, NSP | SRC_B , iZERO , 0 , 0 }, /* C1 */
  243. { data2, none2, 0 , iRET , 0 , 0 }, /* C2 */
  244. { none1, none2, NO_OPS , iRET , 0 , 0 }, /* C3 */
  245. { memOnly, modrm, TO_REG | NSP , iLES , 0 , 0 }, /* C4 */
  246. { memOnly, modrm, TO_REG | NSP , iLDS , 0 , 0 }, /* C5 */
  247. { memReg0, data1, B , iMOV , 0 , 0 }, /* C6 */
  248. { memReg0, data2, 0 , iMOV , 0 , 0 }, /* C7 */
  249. { data2, data1, 0 , iENTER, 0 , 0 }, /* C8 */
  250. { none1, none2, NO_OPS , iLEAVE, 0 , 0 }, /* C9 */
  251. { data2, none2, 0 , iRETF , 0 , 0 }, /* CA */
  252. { none1, none2, NO_OPS , iRETF , 0 , 0 }, /* CB */
  253. { const3, none2, NOT_HLL , iINT , 0 , 0 }, /* CC */
  254. { data1,checkInt, NOT_HLL , iINT , 0 , 0 }, /* CD */
  255. { none1, none2, NOT_HLL | NO_OPS , iINTO , 0 , 0 }, /* CE */
  256. { none1, none2, NOT_HLL | NO_OPS , iIRET , 0 , 0 }, /* Cf */
  257. { shift, const1, B , iZERO , 0 , 0 }, /* D0 */
  258. { shift, const1, SRC_B , iZERO , 0 , 0 }, /* D1 */
  259. { shift, none1, B , iZERO , 0 , 0 }, /* D2 */
  260. { shift, none1, SRC_B , iZERO , 0 , 0 }, /* D3 */
  261. { data1, axImp, NOT_HLL , iAAM , Sf | Zf | Cf, 0 }, /* D4 */
  262. { data1, axImp, NOT_HLL , iAAD , Sf | Zf | Cf, 0 }, /* D5 */
  263. { none1, none2, 0 , iZERO , 0 , 0 }, /* D6 */
  264. { memImp, axImp, NOT_HLL | B| IM_OPS, iXLAT , 0 , 0 }, /* D7 */
  265. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* D8 */
  266. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* D9 */
  267. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DA */
  268. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DB */
  269. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DC */
  270. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DD */
  271. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DE */
  272. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* Df */
  273. { dispS, none2, 0 , iLOOPNE,0 , Zf }, /* E0 */
  274. { dispS, none2, 0 , iLOOPE, 0 , Zf }, /* E1 */
  275. { dispS, none2, 0 , iLOOP , 0 , 0 }, /* E2 */
  276. { dispS, none2, 0 , iJCXZ , 0 , 0 }, /* E3 */
  277. { data1, axImp, NOT_HLL | B|NO_SRC , iIN , 0 , 0 }, /* E4 */
  278. { data1, axImp, NOT_HLL | NO_SRC , iIN , 0 , 0 }, /* E5 */
  279. { data1, axImp, NOT_HLL | B|NO_SRC , iOUT , 0 , 0 }, /* E6 */
  280. { data1, axImp, NOT_HLL | NO_SRC , iOUT , 0 , 0 }, /* E7 */
  281. { dispN, none2, 0 , iCALL , 0 , 0 }, /* E8 */
  282. { dispN, none2, 0 , iJMP , 0 , 0 }, /* E9 */
  283. { dispF, none2, 0 , iJMPF , 0 , 0 }, /* EA */
  284. { dispS, none2, 0 , iJMP , 0 , 0 }, /* EB */
  285. { none1, axImp, NOT_HLL | B|NO_SRC , iIN , 0 , 0 }, /* EC */
  286. { none1, axImp, NOT_HLL | NO_SRC , iIN , 0 , 0 }, /* ED */
  287. { none1, axImp, NOT_HLL | B|NO_SRC , iOUT , 0 , 0 }, /* EE */
  288. { none1, axImp, NOT_HLL | NO_SRC , iOUT , 0 , 0 }, /* EF */
  289. { none1, none2, NOT_HLL | NO_OPS , iLOCK , 0 , 0 }, /* F0 */
  290. { none1, none2, 0 , iZERO , 0 , 0 }, /* F1 */
  291. { prefix, none2, 0 , iREPNE, 0 , 0 }, /* F2 */
  292. { prefix, none2, 0 , iREPE , 0 , 0 }, /* F3 */
  293. { none1, none2, NOT_HLL | NO_OPS , iHLT , 0 , 0 }, /* F4 */
  294. { none1, none2, NO_OPS , iCMC , Cf, Cf }, /* F5 */
  295. { arith, none1, B , iZERO , 0 , 0 }, /* F6 */
  296. { arith, none1, NSP , iZERO , 0 , 0 }, /* F7 */
  297. { none1, none2, NO_OPS , iCLC , Cf, 0 }, /* F8 */
  298. { none1, none2, NO_OPS , iSTC , Cf, 0 }, /* F9 */
  299. { none1, none2, NOT_HLL | NO_OPS , iCLI , 0 , 0 }, /* FA */
  300. { none1, none2, NOT_HLL | NO_OPS , iSTI , 0 , 0 }, /* FB */
  301. { none1, none2, NO_OPS , iCLD , Df, 0 }, /* FC */
  302. { none1, none2, NO_OPS , iSTD , Df, 0 }, /* FD */
  303. { trans, none1, B , iZERO , 0 , 0 }, /* FE */
  304. { trans, none1, NSP , iZERO , 0 , 0 } /* FF */
  305. } ;
  306. static word SegPrefix, RepPrefix;
  307. static byte *pInst; /* Ptr. to current byte of instruction */
  308. static ICODE * pIcode; /* Ptr to Icode record filled in by scan() */
  309. /*****************************************************************************
  310. Scans one machine instruction at offset ip in prog.Image and returns error.
  311. At the same time, fill in low-level icode details for the scanned inst.
  312. ****************************************************************************/
  313. eErrorId scan(dword ip, ICODE *p)
  314. {
  315. Int op;
  316. memset(p, 0, sizeof(ICODE));
  317. p->type = LOW_LEVEL;
  318. p->ic.ll.label = ip; /* ip is absolute offset into image*/
  319. if (ip >= (dword)prog.cbImage)
  320. {
  321. return (IP_OUT_OF_RANGE);
  322. }
  323. SegPrefix = RepPrefix = 0;
  324. pInst = prog.Image + ip;
  325. pIcode = p;
  326. do
  327. {
  328. op = *pInst++; /* First state - trivial */
  329. p->ic.ll.opcode = stateTable[op].opcode; /* Convert to Icode.opcode */
  330. p->ic.ll.flg = stateTable[op].flg & ICODEMASK;
  331. p->ic.ll.flagDU.d = stateTable[op].df;
  332. p->ic.ll.flagDU.u = stateTable[op].uf;
  333. (*stateTable[op].state1)(op); /* Second state */
  334. (*stateTable[op].state2)(op); /* Third state */
  335. } while (stateTable[op].state1 == prefix); /* Loop if prefix */
  336. if (p->ic.ll.opcode)
  337. {
  338. /* Save bytes of image used */
  339. p->ic.ll.numBytes = (byte)((pInst - prog.Image) - ip);
  340. return ((SegPrefix)? FUNNY_SEGOVR: /* Seg. Override invalid */
  341. (RepPrefix ? FUNNY_REP: NO_ERR));/* REP prefix invalid */
  342. }
  343. /* Else opcode error */
  344. return ((stateTable[op].flg & OP386)? INVALID_386OP: INVALID_OPCODE);
  345. }
  346. /***************************************************************************
  347. relocItem - returns TRUE if word pointed at is in relocation table
  348. **************************************************************************/
  349. static boolT relocItem(byte *p)
  350. {
  351. Int i;
  352. dword off = p - prog.Image;
  353. for (i = 0; i < prog.cReloc; i++)
  354. if (prog.relocTable[i] == off)
  355. return TRUE;
  356. return FALSE;
  357. }
  358. /***************************************************************************
  359. getWord - returns next word from image
  360. **************************************************************************/
  361. static word getWord(void)
  362. {
  363. word w = LH(pInst);
  364. pInst += 2;
  365. return w;
  366. }
  367. /****************************************************************************
  368. signex - returns byte sign extended to Int
  369. ***************************************************************************/
  370. static Int signex(byte b)
  371. {
  372. long s = b;
  373. return ((b & 0x80)? (Int)(0xFFFFFF00 | s): (Int)s);
  374. }
  375. /****************************************************************************
  376. * setAddress - Updates the source or destination field for the current
  377. * icode, based on fdst and the TO_REG flag.
  378. * Note: fdst == TRUE is for the r/m part of the field (dest, unless TO_REG)
  379. * fdst == FALSE is for reg part of the field
  380. ***************************************************************************/
  381. static void setAddress(Int i, boolT fdst, word seg, int16 reg, word off)
  382. {
  383. LLOpcode *pm;
  384. /* If not to register (i.e. to r/m), and talking about r/m,
  385. then this is dest */
  386. pm = (!(stateTable[i].flg & TO_REG) == fdst) ?
  387. &pIcode->ic.ll.dst : &pIcode->ic.ll.src;
  388. /* Set segment. A later procedure (lookupAddr in proclist.c) will
  389. * provide the value of this segment in the field segValue. */
  390. if (seg) /* segment override */
  391. {
  392. pm->seg = pm->segOver = (byte)seg;
  393. }
  394. else
  395. { /* no override, check indexed register */
  396. if ((reg >= INDEXBASE) && (reg == INDEXBASE + 2 ||
  397. reg == INDEXBASE + 3 || reg == INDEXBASE + 6))
  398. {
  399. pm->seg = rSS; /* indexed on bp */
  400. }
  401. else
  402. {
  403. pm->seg = rDS; /* any other indexed reg */
  404. }
  405. }
  406. pm->regi = (byte)reg;
  407. pm->off = (int16)off;
  408. if (reg && reg < INDEXBASE && (stateTable[i].flg & B))
  409. {
  410. pm->regi += rAL - rAX;
  411. }
  412. if (seg) /* So we can catch invalid use of segment overrides */
  413. {
  414. SegPrefix = 0;
  415. }
  416. }
  417. /****************************************************************************
  418. rm - Decodes r/m part of modrm byte for dst (unless TO_REG) part of icode
  419. ***************************************************************************/
  420. static void rm(Int i)
  421. {
  422. byte mod = *pInst >> 6;
  423. byte rm = *pInst++ & 7;
  424. switch (mod) {
  425. case 0: /* No disp unless rm == 6 */
  426. if (rm == 6) {
  427. setAddress(i, TRUE, SegPrefix, 0, getWord());
  428. pIcode->ic.ll.flg |= WORD_OFF;
  429. }
  430. else setAddress(i, TRUE, SegPrefix, rm + INDEXBASE, 0);
  431. break;
  432. case 1: /* 1 byte disp */
  433. setAddress(i, TRUE, SegPrefix, rm+INDEXBASE, (word)signex(*pInst++));
  434. break;
  435. case 2: /* 2 byte disp */
  436. setAddress(i, TRUE, SegPrefix, rm + INDEXBASE, getWord());
  437. pIcode->ic.ll.flg |= WORD_OFF;
  438. break;
  439. case 3: /* reg */
  440. setAddress(i, TRUE, 0, rm + rAX, 0);
  441. break;
  442. }
  443. if ((stateTable[i].flg & NSP) && (pIcode->ic.ll.src.regi==rSP ||
  444. pIcode->ic.ll.dst.regi==rSP))
  445. pIcode->ic.ll.flg |= NOT_HLL;
  446. }
  447. /****************************************************************************
  448. modrm - Sets up src and dst from modrm byte
  449. ***************************************************************************/
  450. static void modrm(Int i)
  451. {
  452. setAddress(i, FALSE, 0, REG(*pInst) + rAX, 0);
  453. rm(i);
  454. }
  455. /****************************************************************************
  456. segrm - seg encoded as reg of modrm
  457. ****************************************************************************/
  458. static void segrm(Int i)
  459. {
  460. Int reg = REG(*pInst) + rES;
  461. if (reg > rDS || (reg == rCS && (stateTable[i].flg & TO_REG)))
  462. pIcode->ic.ll.opcode = (llIcode)0;
  463. else {
  464. setAddress(i, FALSE, 0, (int16)reg, 0);
  465. rm(i);
  466. }
  467. }
  468. /****************************************************************************
  469. regop - src/dst reg encoded as low 3 bits of opcode
  470. ***************************************************************************/
  471. static void regop(Int i)
  472. {
  473. setAddress(i, FALSE, 0, ((int16)i & 7) + rAX, 0);
  474. pIcode->ic.ll.dst.regi = pIcode->ic.ll.src.regi;
  475. }
  476. /*****************************************************************************
  477. segop - seg encoded in middle of opcode
  478. *****************************************************************************/
  479. static void segop(Int i)
  480. {
  481. setAddress(i, TRUE, 0, (((int16)i & 0x18) >> 3) + rES, 0);
  482. }
  483. /****************************************************************************
  484. axImp - Plugs an implied AX dst
  485. ***************************************************************************/
  486. static void axImp(Int i)
  487. {
  488. setAddress(i, TRUE, 0, rAX, 0);
  489. }
  490. /* Implied AX source */
  491. static void axSrcIm (Int )
  492. {
  493. pIcode->ic.ll.src.regi = rAX;
  494. }
  495. /* Implied AL source */
  496. static void alImp (Int )
  497. {
  498. pIcode->ic.ll.src.regi = rAL;
  499. }
  500. /*****************************************************************************
  501. memImp - Plugs implied src memory operand with any segment override
  502. ****************************************************************************/
  503. static void memImp(Int i)
  504. {
  505. setAddress(i, FALSE, SegPrefix, 0, 0);
  506. }
  507. /****************************************************************************
  508. memOnly - Instruction is not valid if modrm refers to register (i.e. mod == 3)
  509. ***************************************************************************/
  510. static void memOnly(Int )
  511. {
  512. if ((*pInst & 0xC0) == 0xC0)
  513. pIcode->ic.ll.opcode = (llIcode)0;
  514. }
  515. /****************************************************************************
  516. memReg0 - modrm for 'memOnly' and Reg field must also be 0
  517. ****************************************************************************/
  518. static void memReg0(Int i)
  519. {
  520. if (REG(*pInst) || (*pInst & 0xC0) == 0xC0)
  521. pIcode->ic.ll.opcode = (llIcode)0;
  522. else
  523. rm(i);
  524. }
  525. /***************************************************************************
  526. immed - Sets up dst and opcode from modrm byte
  527. **************************************************************************/
  528. static void immed(Int i)
  529. {
  530. static llIcode immedTable[8] = {iADD, iOR, iADC, iSBB, iAND, iSUB, iXOR, iCMP};
  531. static byte uf[8] = { 0, 0, Cf, Cf, 0, 0, 0, 0 };
  532. pIcode->ic.ll.opcode = immedTable[REG(*pInst)];
  533. pIcode->ic.ll.flagDU.u = uf[REG(*pInst)];
  534. pIcode->ic.ll.flagDU.d = (Sf | Zf | Cf);
  535. rm(i);
  536. if (pIcode->ic.ll.opcode == iADD || pIcode->ic.ll.opcode == iSUB)
  537. pIcode->ic.ll.flg &= ~NOT_HLL; /* Allow ADD/SUB SP, immed */
  538. }
  539. /****************************************************************************
  540. shift - Sets up dst and opcode from modrm byte
  541. ***************************************************************************/
  542. static void shift(Int i)
  543. {
  544. static llIcode shiftTable[8] =
  545. {
  546. (llIcode)iROL, (llIcode)iROR, (llIcode)iRCL, (llIcode)iRCR,
  547. (llIcode)iSHL, (llIcode)iSHR, (llIcode)0, (llIcode)iSAR};
  548. static byte uf[8] = {0, 0, Cf, Cf, 0, 0, 0, 0 };
  549. static byte df[8] = {Cf, Cf, Cf, Cf, Sf | Zf | Cf,
  550. Sf | Zf | Cf, 0, Sf | Zf | Cf};
  551. pIcode->ic.ll.opcode = shiftTable[REG(*pInst)];
  552. pIcode->ic.ll.flagDU.u = uf[REG(*pInst)];
  553. pIcode->ic.ll.flagDU.d = df[REG(*pInst)];
  554. rm(i);
  555. pIcode->ic.ll.src.regi = rCL;
  556. }
  557. /****************************************************************************
  558. trans - Sets up dst and opcode from modrm byte
  559. ***************************************************************************/
  560. static void trans(Int i)
  561. {
  562. static llIcode transTable[8] =
  563. {
  564. (llIcode)iINC, (llIcode)iDEC, (llIcode)iCALL, (llIcode)iCALLF,
  565. (llIcode)iJMP, (llIcode)iJMPF,(llIcode)iPUSH, (llIcode)0
  566. };
  567. static byte df[8] = {Sf | Zf, Sf | Zf, 0, 0, 0, 0, 0, 0};
  568. if ((byte)REG(*pInst) < 2 || !(stateTable[i].flg & B)) { /* INC & DEC */
  569. pIcode->ic.ll.opcode = transTable[REG(*pInst)]; /* valid on bytes */
  570. pIcode->ic.ll.flagDU.d = df[REG(*pInst)];
  571. rm(i);
  572. pIcode->ic.ll.src = pIcode->ic.ll.dst;
  573. if (pIcode->ic.ll.opcode == iJMP || pIcode->ic.ll.opcode == iCALL || pIcode->ic.ll.opcode == iCALLF)
  574. pIcode->ic.ll.flg |= NO_OPS;
  575. else if (pIcode->ic.ll.opcode == iINC || pIcode->ic.ll.opcode == iPUSH || pIcode->ic.ll.opcode == iDEC)
  576. pIcode->ic.ll.flg |= NO_SRC;
  577. }
  578. }
  579. /****************************************************************************
  580. arith - Sets up dst and opcode from modrm byte
  581. ****************************************************************************/
  582. static void arith(Int i)
  583. { byte opcode;
  584. static llIcode arithTable[8] =
  585. {
  586. (llIcode)iTEST, (llIcode)0, (llIcode)iNOT, (llIcode)iNEG,
  587. (llIcode)iMUL, (llIcode)iIMUL, (llIcode)iDIV, (llIcode)iIDIV
  588. };
  589. static byte df[8] = {Sf | Zf | Cf, 0, 0, Sf | Zf | Cf,
  590. Sf | Zf | Cf, Sf | Zf | Cf, Sf | Zf | Cf,
  591. Sf | Zf | Cf};
  592. opcode = pIcode->ic.ll.opcode = arithTable[REG(*pInst)];
  593. pIcode->ic.ll.flagDU.d = df[REG(*pInst)];
  594. rm(i);
  595. if (opcode == iTEST)
  596. {
  597. if (stateTable[i].flg & B)
  598. data1(i);
  599. else
  600. data2(i);
  601. }
  602. else if (!(opcode == iNOT || opcode == iNEG))
  603. {
  604. pIcode->ic.ll.src = pIcode->ic.ll.dst;
  605. setAddress(i, TRUE, 0, rAX, 0); /* dst = AX */
  606. }
  607. else if (opcode == iNEG || opcode == iNOT)
  608. pIcode->ic.ll.flg |= NO_SRC;
  609. if ((opcode == iDIV) || (opcode == iIDIV))
  610. {
  611. if ((pIcode->ic.ll.flg & B) != B)
  612. pIcode->ic.ll.flg |= IM_TMP_DST;
  613. }
  614. }
  615. /*****************************************************************************
  616. data1 - Sets up immed from 1 byte data
  617. *****************************************************************************/
  618. static void data1(Int i)
  619. {
  620. pIcode->ic.ll.src.SetImmediateOp( (stateTable[i].flg & S_EXT)? signex(*pInst++): *pInst++ );
  621. pIcode->ic.ll.flg |= I;
  622. }
  623. /*****************************************************************************
  624. data2 - Sets up immed from 2 byte data
  625. ****************************************************************************/
  626. static void data2(Int )
  627. {
  628. if (relocItem(pInst))
  629. pIcode->ic.ll.flg |= SEG_IMMED;
  630. /* ENTER is a special case, it does not take a destination operand,
  631. * but this field is being used as the number of bytes to allocate
  632. * on the stack. The procedure level is stored in the immediate
  633. * field. There is no source operand; therefore, the flag flg is
  634. * set to NO_OPS. */
  635. if (pIcode->ic.ll.opcode == iENTER)
  636. {
  637. pIcode->ic.ll.dst.off = getWord();
  638. pIcode->ic.ll.flg |= NO_OPS;
  639. }
  640. else
  641. pIcode->ic.ll.src.SetImmediateOp(getWord());
  642. pIcode->ic.ll.flg |= I;
  643. }
  644. /****************************************************************************
  645. dispM - 2 byte offset without modrm (== mod 0, rm 6) (Note:TO_REG bits are
  646. reversed)
  647. ****************************************************************************/
  648. static void dispM(Int i)
  649. {
  650. setAddress(i, FALSE, SegPrefix, 0, getWord());
  651. }
  652. /****************************************************************************
  653. dispN - 2 byte disp as immed relative to ip
  654. ****************************************************************************/
  655. static void dispN(Int )
  656. {
  657. long off = (short)getWord(); /* Signed displacement */
  658. /* Note: the result of the subtraction could be between 32k and 64k, and
  659. still be positive; it is an offset from prog.Image. So this must be
  660. treated as unsigned */
  661. pIcode->ic.ll.src.SetImmediateOp((dword)(off + (unsigned)(pInst - prog.Image)));
  662. pIcode->ic.ll.flg |= I;
  663. }
  664. /***************************************************************************
  665. dispS - 1 byte disp as immed relative to ip
  666. ***************************************************************************/
  667. static void dispS(Int )
  668. {
  669. long off = signex(*pInst++); /* Signed displacement */
  670. pIcode->ic.ll.src.SetImmediateOp((dword)(off + (unsigned)(pInst - prog.Image)));
  671. pIcode->ic.ll.flg |= I;
  672. }
  673. /****************************************************************************
  674. dispF - 4 byte disp as immed 20-bit target address
  675. ***************************************************************************/
  676. static void dispF(Int )
  677. {
  678. dword off = (unsigned)getWord();
  679. dword seg = (unsigned)getWord();
  680. pIcode->ic.ll.src.SetImmediateOp(off + ((dword)(unsigned)seg << 4));
  681. pIcode->ic.ll.flg |= I;
  682. }
  683. /****************************************************************************
  684. prefix - picks up prefix byte for following instruction (LOCK is ignored
  685. on purpose)
  686. ****************************************************************************/
  687. static void prefix(Int )
  688. {
  689. if (pIcode->ic.ll.opcode == iREPE || pIcode->ic.ll.opcode == iREPNE)
  690. RepPrefix = pIcode->ic.ll.opcode;
  691. else
  692. SegPrefix = pIcode->ic.ll.opcode;
  693. }
  694. inline void BumpOpcode(llIcode& ic)
  695. {
  696. ic = (llIcode)(((int)ic)+1); // Bump this icode via the int type
  697. }
  698. /*****************************************************************************
  699. strop - checks RepPrefix and converts string instructions accordingly
  700. *****************************************************************************/
  701. static void strop(Int )
  702. {
  703. if (RepPrefix)
  704. {
  705. // pIcode->ic.ll.opcode += ((pIcode->ic.ll.opcode == iCMPS ||
  706. // pIcode->ic.ll.opcode == iSCAS)
  707. // && RepPrefix == iREPE)? 2: 1;
  708. if ((pIcode->ic.ll.opcode == iCMPS || pIcode->ic.ll.opcode == iSCAS)
  709. && RepPrefix == iREPE)
  710. BumpOpcode(pIcode->ic.ll.opcode); // += 2
  711. BumpOpcode(pIcode->ic.ll.opcode); // else += 1
  712. if (pIcode->ic.ll.opcode == iREP_LODS)
  713. pIcode->ic.ll.flg |= NOT_HLL;
  714. RepPrefix = 0;
  715. }
  716. }
  717. /***************************************************************************
  718. escop - esc operands
  719. ***************************************************************************/
  720. static void escop(Int i)
  721. {
  722. pIcode->ic.ll.src.SetImmediateOp(REG(*pInst) + (dword)((i & 7) << 3));
  723. pIcode->ic.ll.flg |= I;
  724. rm(i);
  725. }
  726. /****************************************************************************
  727. const1
  728. ****************************************************************************/
  729. static void const1(Int )
  730. {
  731. pIcode->ic.ll.src.SetImmediateOp(1);
  732. pIcode->ic.ll.flg |= I;
  733. }
  734. /*****************************************************************************
  735. const3
  736. ****************************************************************************/
  737. static void const3(Int )
  738. {
  739. pIcode->ic.ll.src.SetImmediateOp(3);
  740. pIcode->ic.ll.flg |= I;
  741. }
  742. /****************************************************************************
  743. none1
  744. ****************************************************************************/
  745. static void none1(Int )
  746. {
  747. }
  748. /****************************************************************************
  749. none2 - Sets the NO_OPS flag if the operand is immediate
  750. ****************************************************************************/
  751. static void none2(Int )
  752. {
  753. if (pIcode->ic.ll.flg & I)
  754. pIcode->ic.ll.flg |= NO_OPS;
  755. }
  756. /****************************************************************************
  757. Checks for int 34 to int 3B - if so, converts to ESC nn instruction
  758. ****************************************************************************/
  759. static void checkInt(Int )
  760. {
  761. word wOp = (word) pIcode->ic.ll.src.op();
  762. if ((wOp >= 0x34) && (wOp <= 0x3B))
  763. {
  764. /* This is a Borland/Microsoft floating point emulation instruction.
  765. Treat as if it is an ESC opcode */
  766. pIcode->ic.ll.src.SetImmediateOp(wOp - 0x34);
  767. pIcode->ic.ll.opcode = iESC;
  768. pIcode->ic.ll.flg |= FLOAT_OP;
  769. escop(wOp - 0x34 + 0xD8);
  770. }
  771. }