scanner.cpp 42 KB

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  1. /*****************************************************************************
  2. * dcc project scanner module
  3. * Implements a simple state driven scanner to convert 8086 machine code into
  4. * I-code
  5. * (C) Cristina Cifuentes, Jeff Ledermann
  6. ****************************************************************************/
  7. #include "scanner.h"
  8. #include "msvc_fixes.h"
  9. #include "dcc.h"
  10. #include "project.h"
  11. #include <cstring>
  12. #include <map>
  13. #include <string>
  14. /* Parser flags */
  15. #define TO_REG 0x000100 /* rm is source */
  16. #define S_EXT 0x000200 /* sign extend */
  17. #define OP386 0x000400 /* 386 op-code */
  18. #define NSP 0x000800 /* NOT_HLL if SP is src or dst */
  19. // defined in Enums.h #define ICODEMASK 0xFF00FF /* Masks off parser flags */
  20. static void rm(int i);
  21. static void modrm(int i);
  22. static void segrm(int i);
  23. static void data1(int i);
  24. static void data2(int i);
  25. static void regop(int i);
  26. static void segop(int i);
  27. static void strop(int i);
  28. static void escop(int i);
  29. static void axImp(int i);
  30. static void alImp(int i);
  31. static void axSrcIm(int i);
  32. static void memImp(int i);
  33. static void memReg0(int i);
  34. static void memOnly(int i);
  35. static void dispM(int i);
  36. static void dispS(int i);
  37. static void dispN(int i);
  38. static void dispF(int i);
  39. static void prefix(int i);
  40. static void immed(int i);
  41. static void shift(int i);
  42. static void arith(int i);
  43. static void trans(int i);
  44. static void const1(int i);
  45. static void const3(int i);
  46. static void none1(int i);
  47. static void none2(int i);
  48. static void checkInt(int i);
  49. #define iZERO (llIcode)0 // For neatness
  50. #define IC llIcode
  51. static struct {
  52. void (*state1)(int);
  53. void (*state2)(int);
  54. uint32_t flg;
  55. llIcode opcode;
  56. } stateTable[] = {
  57. { modrm, none2, B , iADD }, /* 00 */
  58. { modrm, none2, 0 , iADD }, /* 01 */
  59. { modrm, none2, TO_REG | B , iADD }, /* 02 */
  60. { modrm, none2, TO_REG , iADD }, /* 03 */
  61. { data1, axImp, B , iADD }, /* 04 */
  62. { data2, axImp, 0 , iADD }, /* 05 */
  63. { segop, none2, NO_SRC , iPUSH }, /* 06 */
  64. { segop, none2, NO_SRC , iPOP }, /* 07 */
  65. { modrm, none2, B , iOR }, /* 08 */
  66. { modrm, none2, NSP , iOR }, /* 09 */
  67. { modrm, none2, TO_REG | B , iOR }, /* 0A */
  68. { modrm, none2, TO_REG | NSP , iOR }, /* 0B */
  69. { data1, axImp, B , iOR }, /* 0C */
  70. { data2, axImp, 0 , iOR }, /* 0D */
  71. { segop, none2, NO_SRC , iPUSH }, /* 0E */
  72. { none1, none2, OP386 , iZERO }, /* 0F */
  73. { modrm, none2, B , iADC }, /* 10 */
  74. { modrm, none2, NSP , iADC }, /* 11 */
  75. { modrm, none2, TO_REG | B , iADC }, /* 12 */
  76. { modrm, none2, TO_REG | NSP , iADC }, /* 13 */
  77. { data1, axImp, B , iADC }, /* 14 */
  78. { data2, axImp, 0 , iADC }, /* 15 */
  79. { segop, none2, NOT_HLL | NO_SRC , iPUSH }, /* 16 */
  80. { segop, none2, NOT_HLL | NO_SRC , iPOP }, /* 17 */
  81. { modrm, none2, B , iSBB }, /* 18 */
  82. { modrm, none2, NSP , iSBB }, /* 19 */
  83. { modrm, none2, TO_REG | B , iSBB }, /* 1A */
  84. { modrm, none2, TO_REG | NSP , iSBB }, /* 1B */
  85. { data1, axImp, B , iSBB }, /* 1C */
  86. { data2, axImp, 0 , iSBB }, /* 1D */
  87. { segop, none2, NO_SRC , iPUSH }, /* 1E */
  88. { segop, none2, NO_SRC , iPOP }, /* 1F */
  89. { modrm, none2, B , iAND }, /* 20 */
  90. { modrm, none2, NSP , iAND }, /* 21 */
  91. { modrm, none2, TO_REG | B , iAND }, /* 22 */
  92. { modrm, none2, TO_REG | NSP , iAND }, /* 23 */
  93. { data1, axImp, B , iAND }, /* 24 */
  94. { data2, axImp, 0 , iAND }, /* 25 */
  95. { prefix, none2, 0 , (IC)rES}, /* 26 */
  96. { none1, axImp, NOT_HLL | B|NO_SRC , iDAA }, /* 27 */
  97. { modrm, none2, B , iSUB }, /* 28 */
  98. { modrm, none2, 0 , iSUB }, /* 29 */
  99. { modrm, none2, TO_REG | B , iSUB }, /* 2A */
  100. { modrm, none2, TO_REG , iSUB }, /* 2B */
  101. { data1, axImp, B , iSUB }, /* 2C */
  102. { data2, axImp, 0 , iSUB }, /* 2D */
  103. { prefix, none2, 0 , (IC)rCS}, /* 2E */
  104. { none1, axImp, NOT_HLL | B|NO_SRC , iDAS }, /* 2F */
  105. { modrm, none2, B , iXOR }, /* 30 */
  106. { modrm, none2, NSP , iXOR }, /* 31 */
  107. { modrm, none2, TO_REG | B , iXOR }, /* 32 */
  108. { modrm, none2, TO_REG | NSP , iXOR }, /* 33 */
  109. { data1, axImp, B , iXOR }, /* 34 */
  110. { data2, axImp, 0 , iXOR }, /* 35 */
  111. { prefix, none2, 0 , (IC)rSS}, /* 36 */
  112. { none1, axImp, NOT_HLL | NO_SRC , iAAA }, /* 37 */
  113. { modrm, none2, B , iCMP }, /* 38 */
  114. { modrm, none2, NSP , iCMP }, /* 39 */
  115. { modrm, none2, TO_REG | B , iCMP }, /* 3A */
  116. { modrm, none2, TO_REG | NSP , iCMP }, /* 3B */
  117. { data1, axImp, B , iCMP }, /* 3C */
  118. { data2, axImp, 0 , iCMP }, /* 3D */
  119. { prefix, none2, 0 , (IC)rDS}, /* 3E */
  120. { none1, axImp, NOT_HLL | NO_SRC , iAAS }, /* 3F */
  121. { regop, none2, 0 , iINC }, /* 40 */
  122. { regop, none2, 0 , iINC }, /* 41 */
  123. { regop, none2, 0 , iINC }, /* 42 */
  124. { regop, none2, 0 , iINC }, /* 43 */
  125. { regop, none2, NOT_HLL , iINC }, /* 44 */
  126. { regop, none2, 0 , iINC }, /* 45 */
  127. { regop, none2, 0 , iINC }, /* 46 */
  128. { regop, none2, 0 , iINC }, /* 47 */
  129. { regop, none2, 0 , iDEC }, /* 48 */
  130. { regop, none2, 0 , iDEC }, /* 49 */
  131. { regop, none2, 0 , iDEC }, /* 4A */
  132. { regop, none2, 0 , iDEC }, /* 4B */
  133. { regop, none2, NOT_HLL , iDEC }, /* 4C */
  134. { regop, none2, 0 , iDEC }, /* 4D */
  135. { regop, none2, 0 , iDEC }, /* 4E */
  136. { regop, none2, 0 , iDEC }, /* 4F */
  137. { regop, none2, NO_SRC , iPUSH }, /* 50 */
  138. { regop, none2, NO_SRC , iPUSH }, /* 51 */
  139. { regop, none2, NO_SRC , iPUSH }, /* 52 */
  140. { regop, none2, NO_SRC , iPUSH }, /* 53 */
  141. { regop, none2, NOT_HLL | NO_SRC , iPUSH }, /* 54 */
  142. { regop, none2, NO_SRC , iPUSH }, /* 55 */
  143. { regop, none2, NO_SRC , iPUSH }, /* 56 */
  144. { regop, none2, NO_SRC , iPUSH }, /* 57 */
  145. { regop, none2, NO_SRC , iPOP }, /* 58 */
  146. { regop, none2, NO_SRC , iPOP }, /* 59 */
  147. { regop, none2, NO_SRC , iPOP }, /* 5A */
  148. { regop, none2, NO_SRC , iPOP }, /* 5B */
  149. { regop, none2, NOT_HLL | NO_SRC , iPOP }, /* 5C */
  150. { regop, none2, NO_SRC , iPOP }, /* 5D */
  151. { regop, none2, NO_SRC , iPOP }, /* 5E */
  152. { regop, none2, NO_SRC , iPOP }, /* 5F */
  153. { none1, none2, NOT_HLL | NO_OPS , iPUSHA}, /* 60 */
  154. { none1, none2, NOT_HLL | NO_OPS , iPOPA }, /* 61 */
  155. { memOnly, modrm, TO_REG | NSP , iBOUND}, /* 62 */
  156. { none1, none2, OP386 , iZERO }, /* 63 */
  157. { none1, none2, OP386 , iZERO }, /* 64 */
  158. { none1, none2, OP386 , iZERO }, /* 65 */
  159. { none1, none2, OP386 , iZERO }, /* 66 */
  160. { none1, none2, OP386 , iZERO }, /* 67 */
  161. { data2, none2, NO_SRC , iPUSH }, /* 68 */
  162. { modrm, data2, TO_REG | NSP , iIMUL }, /* 69 */
  163. { data1, none2, S_EXT | NO_SRC , iPUSH }, /* 6A */
  164. { modrm, data1, TO_REG | NSP | S_EXT , iIMUL }, /* 6B */
  165. { strop, memImp, NOT_HLL | B|IM_OPS , iINS }, /* 6C */
  166. { strop, memImp, NOT_HLL | IM_OPS , iINS }, /* 6D */
  167. { strop, memImp, NOT_HLL | B|IM_OPS , iOUTS }, /* 6E */
  168. { strop, memImp, NOT_HLL | IM_OPS , iOUTS }, /* 6F */
  169. { dispS, none2, NOT_HLL , iJO }, /* 70 */
  170. { dispS, none2, NOT_HLL , iJNO }, /* 71 */
  171. { dispS, none2, 0 , iJB }, /* 72 */
  172. { dispS, none2, 0 , iJAE }, /* 73 */
  173. { dispS, none2, 0 , iJE }, /* 74 */
  174. { dispS, none2, 0 , iJNE }, /* 75 */
  175. { dispS, none2, 0 , iJBE }, /* 76 */
  176. { dispS, none2, 0 , iJA }, /* 77 */
  177. { dispS, none2, 0 , iJS }, /* 78 */
  178. { dispS, none2, 0 , iJNS }, /* 79 */
  179. { dispS, none2, NOT_HLL , iJP }, /* 7A */
  180. { dispS, none2, NOT_HLL , iJNP }, /* 7B */
  181. { dispS, none2, 0 , iJL }, /* 7C */
  182. { dispS, none2, 0 , iJGE }, /* 7D */
  183. { dispS, none2, 0 , iJLE }, /* 7E */
  184. { dispS, none2, 0 , iJG }, /* 7F */
  185. { immed, data1, B , iZERO }, /* 80 */
  186. { immed, data2, NSP , iZERO }, /* 81 */
  187. { immed, data1, B , iZERO }, /* 82 */ /* ?? */
  188. { immed, data1, NSP | S_EXT , iZERO }, /* 83 */
  189. { modrm, none2, TO_REG | B , iTEST }, /* 84 */
  190. { modrm, none2, TO_REG | NSP , iTEST }, /* 85 */
  191. { modrm, none2, TO_REG | B , iXCHG }, /* 86 */
  192. { modrm, none2, TO_REG | NSP , iXCHG }, /* 87 */
  193. { modrm, none2, B , iMOV }, /* 88 */
  194. { modrm, none2, 0 , iMOV }, /* 89 */
  195. { modrm, none2, TO_REG | B , iMOV }, /* 8A */
  196. { modrm, none2, TO_REG , iMOV }, /* 8B */
  197. { segrm, none2, NSP , iMOV }, /* 8C */
  198. { memOnly, modrm, TO_REG | NSP , iLEA }, /* 8D */
  199. { segrm, none2, TO_REG | NSP , iMOV }, /* 8E */
  200. { memReg0, none2, NO_SRC , iPOP }, /* 8F */
  201. { none1, none2, NO_OPS , iNOP }, /* 90 */
  202. { regop, axImp, 0 , iXCHG }, /* 91 */
  203. { regop, axImp, 0 , iXCHG }, /* 92 */
  204. { regop, axImp, 0 , iXCHG }, /* 93 */
  205. { regop, axImp, NOT_HLL , iXCHG }, /* 94 */
  206. { regop, axImp, 0 , iXCHG }, /* 95 */
  207. { regop, axImp, 0 , iXCHG }, /* 96 */
  208. { regop, axImp, 0 , iXCHG }, /* 97 */
  209. { alImp, axImp, SRC_B | S_EXT , iSIGNEX}, /* 98 */
  210. {axSrcIm, axImp, IM_DST | S_EXT , iSIGNEX}, /* 99 */
  211. { dispF, none2, 0 , iCALLF }, /* 9A */
  212. { none1, none2, FLOAT_OP| NO_OPS , iWAIT }, /* 9B */
  213. { none1, none2, NOT_HLL | NO_OPS , iPUSHF}, /* 9C */
  214. { none1, none2, NOT_HLL | NO_OPS , iPOPF }, /* 9D */
  215. { none1, none2, NOT_HLL | NO_OPS , iSAHF }, /* 9E */
  216. { none1, none2, NOT_HLL | NO_OPS , iLAHF }, /* 9F */
  217. { dispM, axImp, B , iMOV }, /* A0 */
  218. { dispM, axImp, 0 , iMOV }, /* A1 */
  219. { dispM, axImp, TO_REG | B , iMOV }, /* A2 */
  220. { dispM, axImp, TO_REG , iMOV }, /* A3 */
  221. { strop, memImp, B | IM_OPS , iMOVS }, /* A4 */
  222. { strop, memImp, IM_OPS , iMOVS }, /* A5 */
  223. { strop, memImp, B | IM_OPS , iCMPS }, /* A6 */
  224. { strop, memImp, IM_OPS , iCMPS }, /* A7 */
  225. { data1, axImp, B , iTEST }, /* A8 */
  226. { data2, axImp, 0 , iTEST }, /* A9 */
  227. { strop, memImp, B | IM_OPS , iSTOS }, /* AA */
  228. { strop, memImp, IM_OPS , iSTOS }, /* AB */
  229. { strop, memImp, B | IM_OPS , iLODS }, /* AC */
  230. { strop, memImp, IM_OPS , iLODS }, /* AD */
  231. { strop, memImp, B | IM_OPS , iSCAS }, /* AE */
  232. { strop, memImp, IM_OPS , iSCAS }, /* AF */
  233. { regop, data1, B , iMOV }, /* B0 */
  234. { regop, data1, B , iMOV }, /* B1 */
  235. { regop, data1, B , iMOV }, /* B2 */
  236. { regop, data1, B , iMOV }, /* B3 */
  237. { regop, data1, B , iMOV }, /* B4 */
  238. { regop, data1, B , iMOV }, /* B5 */
  239. { regop, data1, B , iMOV }, /* B6 */
  240. { regop, data1, B , iMOV }, /* B7 */
  241. { regop, data2, 0 , iMOV }, /* B8 */
  242. { regop, data2, 0 , iMOV }, /* B9 */
  243. { regop, data2, 0 , iMOV }, /* BA */
  244. { regop, data2, 0 , iMOV }, /* BB */
  245. { regop, data2, NOT_HLL , iMOV }, /* BC */
  246. { regop, data2, 0 , iMOV }, /* BD */
  247. { regop, data2, 0 , iMOV }, /* BE */
  248. { regop, data2, 0 , iMOV }, /* BF */
  249. { shift, data1, B , iZERO }, /* C0 */
  250. { shift, data1, NSP | SRC_B , iZERO }, /* C1 */
  251. { data2, none2, 0 , iRET }, /* C2 */
  252. { none1, none2, NO_OPS , iRET }, /* C3 */
  253. { memOnly, modrm, TO_REG | NSP , iLES }, /* C4 */
  254. { memOnly, modrm, TO_REG | NSP , iLDS }, /* C5 */
  255. { memReg0, data1, B , iMOV }, /* C6 */
  256. { memReg0, data2, 0 , iMOV }, /* C7 */
  257. { data2, data1, 0 , iENTER}, /* C8 */
  258. { none1, none2, NO_OPS , iLEAVE}, /* C9 */
  259. { data2, none2, 0 , iRETF }, /* CA */
  260. { none1, none2, NO_OPS , iRETF }, /* CB */
  261. { const3, none2, NOT_HLL , iINT }, /* CC */
  262. { data1,checkInt, NOT_HLL , iINT }, /* CD */
  263. { none1, none2, NOT_HLL | NO_OPS , iINTO }, /* CE */
  264. { none1, none2, NOT_HLL | NO_OPS , iIRET }, /* Cf */
  265. { shift, const1, B , iZERO }, /* D0 */
  266. { shift, const1, SRC_B , iZERO }, /* D1 */
  267. { shift, none1, B , iZERO }, /* D2 */
  268. { shift, none1, SRC_B , iZERO }, /* D3 */
  269. { data1, axImp, NOT_HLL , iAAM }, /* D4 */
  270. { data1, axImp, NOT_HLL , iAAD }, /* D5 */
  271. { none1, none2, 0 , iZERO }, /* D6 */
  272. { memImp, axImp, NOT_HLL | B| IM_OPS , iXLAT }, /* D7 */
  273. { escop, none2, FLOAT_OP , iESC }, /* D8 */
  274. { escop, none2, FLOAT_OP , iESC }, /* D9 */
  275. { escop, none2, FLOAT_OP , iESC }, /* DA */
  276. { escop, none2, FLOAT_OP , iESC }, /* DB */
  277. { escop, none2, FLOAT_OP , iESC }, /* DC */
  278. { escop, none2, FLOAT_OP , iESC }, /* DD */
  279. { escop, none2, FLOAT_OP , iESC }, /* DE */
  280. { escop, none2, FLOAT_OP , iESC }, /* Df */
  281. { dispS, none2, 0 , iLOOPNE}, /* E0 */
  282. { dispS, none2, 0 , iLOOPE}, /* E1 */
  283. { dispS, none2, 0 , iLOOP }, /* E2 */
  284. { dispS, none2, 0 , iJCXZ }, /* E3 */
  285. { data1, axImp, NOT_HLL | B|NO_SRC , iIN }, /* E4 */
  286. { data1, axImp, NOT_HLL | NO_SRC , iIN }, /* E5 */
  287. { data1, axImp, NOT_HLL | B|NO_SRC , iOUT }, /* E6 */
  288. { data1, axImp, NOT_HLL | NO_SRC , iOUT }, /* E7 */
  289. { dispN, none2, 0 , iCALL }, /* E8 */
  290. { dispN, none2, 0 , iJMP }, /* E9 */
  291. { dispF, none2, 0 , iJMPF }, /* EA */
  292. { dispS, none2, 0 , iJMP }, /* EB */
  293. { none1, axImp, NOT_HLL | B|NO_SRC , iIN }, /* EC */
  294. { none1, axImp, NOT_HLL | NO_SRC , iIN }, /* ED */
  295. { none1, axImp, NOT_HLL | B|NO_SRC , iOUT }, /* EE */
  296. { none1, axImp, NOT_HLL | NO_SRC , iOUT }, /* EF */
  297. { none1, none2, NOT_HLL | NO_OPS , iLOCK }, /* F0 */
  298. { none1, none2, 0 , iZERO }, /* F1 */
  299. { prefix, none2, 0 , iREPNE}, /* F2 */
  300. { prefix, none2, 0 , iREPE }, /* F3 */
  301. { none1, none2, NOT_HLL | NO_OPS , iHLT }, /* F4 */
  302. { none1, none2, NO_OPS , iCMC }, /* F5 */
  303. { arith, none1, B , iZERO }, /* F6 */
  304. { arith, none1, NSP , iZERO }, /* F7 */
  305. { none1, none2, NO_OPS , iCLC }, /* F8 */
  306. { none1, none2, NO_OPS , iSTC }, /* F9 */
  307. { none1, none2, NOT_HLL | NO_OPS , iCLI }, /* FA */
  308. { none1, none2, NOT_HLL | NO_OPS , iSTI }, /* FB */
  309. { none1, none2, NO_OPS , iCLD }, /* FC */
  310. { none1, none2, NO_OPS , iSTD }, /* FD */
  311. { trans, none1, B , iZERO }, /* FE */
  312. { trans, none1, NSP , iZERO } /* FF */
  313. } ;
  314. static uint16_t SegPrefix, RepPrefix;
  315. static const uint8_t *pInst; /* Ptr. to current uint8_t of instruction */
  316. static ICODE * pIcode; /* Ptr to Icode record filled in by scan() */
  317. static void decodeBranchTgt(x86_insn_t &insn)
  318. {
  319. x86_op_t *tgt_op = insn.x86_get_branch_target();
  320. if(tgt_op->type==op_expression)
  321. return; // unhandled for now
  322. if(tgt_op->type==op_register)
  323. return; // unhandled for now
  324. int32_t addr = tgt_op->getAddress();
  325. if(tgt_op->is_relative())
  326. {
  327. addr = (uint16_t)(addr + insn.addr + insn.size);
  328. }
  329. pIcode->ll()->replaceSrc((uint32_t)addr);
  330. pIcode->ll()->setFlags(I);
  331. // PROG &prog(Project::get()->prog);
  332. // long off = (short)getWord(); /* Signed displacement */
  333. // assert(addr==(uint32_t)(off + (unsigned)(pInst - prog.image())));
  334. }
  335. static void convertUsedFlags(x86_insn_t &from,ICODE &to)
  336. {
  337. to.ll()->flagDU.d=0;
  338. to.ll()->flagDU.u=0;
  339. if(from.containsFlag(insn_eflag_carry,from.flags_set))
  340. to.ll()->flagDU.d |= Cf;
  341. if(from.containsFlag(insn_eflag_sign,from.flags_set))
  342. to.ll()->flagDU.d |= Sf;
  343. if(from.containsFlag(insn_eflag_zero,from.flags_set))
  344. to.ll()->flagDU.d |= Zf;
  345. if(from.containsFlag(insn_eflag_direction,from.flags_set))
  346. to.ll()->flagDU.d |= Df;
  347. if(from.containsFlag(insn_eflag_carry,from.flags_tested))
  348. to.ll()->flagDU.u |= Cf;
  349. if(from.containsFlag(insn_eflag_sign,from.flags_tested))
  350. to.ll()->flagDU.u |= Sf;
  351. if(from.containsFlag(insn_eflag_zero,from.flags_tested))
  352. to.ll()->flagDU.u |= Zf;
  353. if(from.containsFlag(insn_eflag_direction,from.flags_tested))
  354. to.ll()->flagDU.u |= Df;
  355. }
  356. static void convertPrefix(x86_insn_prefix prefix,ICODE &to)
  357. {
  358. if(prefix ==insn_no_prefix)
  359. return;
  360. // insn_lock - no need to handle
  361. RepPrefix = (uint16_t)prefix & ~insn_lock;
  362. }
  363. /****************************************************************************
  364. Checks for int 34 to int 3B - if so, converts to ESC nn instruction
  365. ****************************************************************************/
  366. static void fixFloatEmulation(x86_insn_t &insn)
  367. {
  368. if(insn.operand_count==0)
  369. return;
  370. if(insn.group!=x86_insn_t::insn_interrupt)
  371. return;
  372. PROG &prog(Project::get()->prog);
  373. uint16_t wOp=insn.x86_get_imm()->data.word;
  374. if ((wOp < 0x34) or (wOp > 0x3B))
  375. return;
  376. uint8_t buf[16];
  377. /* This is a Borland/Microsoft floating point emulation instruction. Treat as if it is an ESC opcode */
  378. int actual_valid_bytes=std::min(16U,prog.cbImage-insn.offset);
  379. memcpy(buf,prog.image()+insn.offset,actual_valid_bytes);
  380. X86_Disasm ds(opt_16_bit);
  381. x86_insn_t patched_insn;
  382. //patch actual instruction into buffer;
  383. buf[1] = wOp-0x34+0xD8;
  384. ds.x86_disasm(buf,actual_valid_bytes,0,1,&patched_insn);
  385. patched_insn.addr = insn.addr; // actual address
  386. patched_insn.offset = insn.offset; // actual offset
  387. insn = patched_insn;
  388. insn.size += 1; // to account for emulator call INT
  389. }
  390. int disassembleOneLibDisasm(uint32_t ip,x86_insn_t &l)
  391. {
  392. PROG &prog(Project::get()->prog);
  393. X86_Disasm ds(opt_16_bit);
  394. int cnt=ds.x86_disasm(prog.image(),prog.cbImage,0,ip,&l);
  395. if(cnt and l.is_valid())
  396. {
  397. fixFloatEmulation(l); //can change 'l'
  398. }
  399. if(l.is_valid())
  400. return l.size;
  401. return 0;
  402. }
  403. eReg convertRegister(const x86_reg_t &reg)
  404. {
  405. if( (reg_pc==reg.type) or (0==reg.id))
  406. return rUNDEF;
  407. eReg regmap[]={ rUNDEF,
  408. rUNDEF,rUNDEF,rUNDEF,rUNDEF, //eax ecx ebx edx
  409. rSP,rUNDEF,rUNDEF,rDI, //esp ebp esi edi
  410. rAX,rCX,rDX,rBX,
  411. rSP,rBP,rSI,rDI,
  412. rAL,rCL,rDL,rBL,
  413. rAH,rCH,rDH,rBH
  414. };
  415. std::map<std::string,eReg> nameToEnum = {{"es",rES},{"ds",rDS},{"cs",rCS},{"ss",rSS}};
  416. if(nameToEnum.find(reg.name)!=nameToEnum.end())
  417. return nameToEnum[reg.name];
  418. assert(reg.id<sizeof(regmap)/sizeof(eReg));
  419. assert(regmap[reg.id]!=rUNDEF);
  420. return regmap[reg.id];
  421. }
  422. LLOperand convertExpression(const x86_ea_t &from)
  423. {
  424. // BASE + Scale*Index + Disp
  425. LLOperand res;
  426. res.seg = rDS;
  427. /*
  428. INDEX_BX_SI = 22, // "bx+si"
  429. INDEX_BX_DI, // "bx+di"
  430. INDEX_BP_SI, // "bp+si"
  431. INDEX_BP_DI, // "bp+di"
  432. INDEX_SI, // "si"
  433. INDEX_DI, // "di"
  434. INDEX_BP, // "bp"
  435. INDEX_BX, // "bx"
  436. */
  437. if(from.base.id)
  438. {
  439. eReg base_reg = convertRegister(from.base);
  440. eReg index_reg = convertRegister(from.index);
  441. // if(base_reg==rBX)
  442. switch(base_reg)
  443. {
  444. case rDI:
  445. res.regi = INDEX_DI; break;
  446. case rBP:
  447. res.seg=rSS;
  448. switch(index_reg)
  449. {
  450. case rDI:
  451. res.regi = INDEX_BP_DI; break;
  452. case rSI:
  453. res.regi = INDEX_BP_SI; break;
  454. case rUNDEF:
  455. res.regi = INDEX_BP; break;
  456. default:
  457. assert(false);
  458. }
  459. break;
  460. case rBX:
  461. switch(index_reg)
  462. {
  463. case rDI:
  464. res.regi = INDEX_BX_DI; break;
  465. case rSI:
  466. res.regi = INDEX_BX_SI; break;
  467. case rUNDEF:
  468. res.regi = INDEX_BX; break;
  469. default:
  470. assert(false);
  471. }
  472. break;
  473. default:
  474. assert(false);
  475. }
  476. assert(index_reg==rUNDEF);
  477. }
  478. assert(from.scale==0);
  479. if(from.index.id)
  480. {
  481. assert(false);
  482. }
  483. res.off = from.disp;
  484. return res;
  485. }
  486. LLOperand convertOperand(const x86_op_t &from)
  487. {
  488. LLOperand res;
  489. switch(from.type)
  490. {
  491. case op_unused:
  492. break;
  493. case op_register:
  494. res.regi = convertRegister(from.data.reg); break;
  495. case op_immediate:
  496. res.opz = from.data.sdword;
  497. case op_expression:
  498. res = convertExpression(from.data.expression); break;
  499. case op_offset:
  500. {
  501. LLOperand res;
  502. res.seg = rDS;
  503. res.off = from.data.offset;
  504. break;
  505. }
  506. default:
  507. fprintf(stderr,"convertOperand does not know how to convert %d\n",from.type);
  508. }
  509. if(res.isSet() and (res.seg == rUNDEF))
  510. {
  511. res.seg = rDS;
  512. }
  513. return res;
  514. }
  515. /*****************************************************************************
  516. Scans one machine instruction at offset ip in prog.Image and returns error.
  517. At the same time, fill in low-level icode details for the scanned inst.
  518. ****************************************************************************/
  519. eErrorId scan(uint32_t ip, ICODE &p)
  520. {
  521. PROG &prog(Project::get()->prog);
  522. int op;
  523. p = ICODE();
  524. p.type = LOW_LEVEL;
  525. p.ll()->label = ip; /* ip is absolute offset into image*/
  526. if (ip >= (uint32_t)prog.cbImage)
  527. {
  528. return (IP_OUT_OF_RANGE);
  529. }
  530. int cnt=disassembleOneLibDisasm(ip,p.insn);
  531. if(cnt)
  532. {
  533. convertUsedFlags(p.insn,p);
  534. convertPrefix(p.insn.prefix,p);
  535. }
  536. SegPrefix = RepPrefix = 0;
  537. pInst = prog.image() + ip;
  538. pIcode = &p;
  539. do
  540. {
  541. op = *pInst++; /* First state - trivial */
  542. /* Convert to Icode.opcode */
  543. p.ll()->set(stateTable[op].opcode,stateTable[op].flg & ICODEMASK);
  544. (*stateTable[op].state1)(op); /* Second state */
  545. (*stateTable[op].state2)(op); /* Third state */
  546. } while (stateTable[op].state1 == prefix); /* Loop if prefix */
  547. if(p.insn.group == x86_insn_t::insn_controlflow)
  548. {
  549. if(p.insn.x86_get_branch_target())
  550. decodeBranchTgt(p.insn);
  551. }
  552. // LLOperand conv = convertOperand(*p.insn.get_dest());
  553. // assert(conv==p.ll()->dst);
  554. if (p.ll()->getOpcode())
  555. {
  556. /* Save bytes of image used */
  557. p.ll()->numBytes = (uint8_t)((pInst - prog.image()) - ip);
  558. if(p.insn.is_valid())
  559. assert(p.ll()->numBytes == p.insn.size);
  560. p.ll()->numBytes = p.insn.size;
  561. return ((SegPrefix)? FUNNY_SEGOVR: /* Seg. Override invalid */
  562. (RepPrefix ? FUNNY_REP: NO_ERR));/* REP prefix invalid */
  563. }
  564. /* Else opcode error */
  565. return ((stateTable[op].flg & OP386)? INVALID_386OP: INVALID_OPCODE);
  566. }
  567. /***************************************************************************
  568. relocItem - returns true if uint16_t pointed at is in relocation table
  569. **************************************************************************/
  570. static bool relocItem(const uint8_t *p)
  571. {
  572. PROG &prog(Project::get()->prog);
  573. int i;
  574. uint32_t off = p - prog.image();
  575. for (i = 0; i < prog.cReloc; i++)
  576. if (prog.relocTable[i] == off)
  577. return true;
  578. return false;
  579. }
  580. /***************************************************************************
  581. getWord - returns next uint16_t from image
  582. **************************************************************************/
  583. static uint16_t getWord(void)
  584. {
  585. uint16_t w = LH(pInst);
  586. pInst += 2;
  587. return w;
  588. }
  589. /****************************************************************************
  590. signex - returns uint8_t sign extended to int
  591. ***************************************************************************/
  592. static int signex(uint8_t b)
  593. {
  594. long s = b;
  595. return ((b & 0x80)? (int)(0xFFFFFF00 | s): (int)s);
  596. }
  597. /****************************************************************************
  598. * setAddress - Updates the source or destination field for the current
  599. * icode, based on fdst and the TO_REG flag.
  600. * Note: fdst == true is for the r/m part of the field (dest, unless TO_REG)
  601. * fdst == false is for reg part of the field
  602. ***************************************************************************/
  603. static void setAddress(int i, bool fdst, uint16_t seg, int16_t reg, uint16_t off)
  604. {
  605. /* If not to register (i.e. to r/m), and talking about r/m, then this is dest */
  606. LLOperand *pm = ((stateTable[i].flg & TO_REG) != fdst) ? &pIcode->ll()->m_dst : &pIcode->ll()->src();
  607. /* Set segment. A later procedure (lookupAddr in proclist.c) will
  608. * provide the value of this segment in the field segValue.
  609. */
  610. if (seg) /* segment override */
  611. {
  612. pm->seg = pm->segOver = (eReg)seg;
  613. }
  614. else
  615. { /* no override, check indexed register */
  616. if ((reg >= INDEX_BX_SI) and (reg == INDEX_BP_SI or reg == INDEX_BP_DI or reg == INDEX_BP))
  617. {
  618. pm->seg = rSS; /* indexed on bp */
  619. }
  620. else
  621. {
  622. pm->seg = rDS; /* any other indexed reg */
  623. }
  624. }
  625. pm->regi = (eReg)reg;
  626. pm->off = (int16_t)off;
  627. if (reg and (reg < INDEX_BX_SI) and (stateTable[i].flg & B))
  628. {
  629. pm->regi = Machine_X86::subRegL(pm->regi);
  630. }
  631. if (seg) /* So we can catch invalid use of segment overrides */
  632. {
  633. SegPrefix = 0;
  634. }
  635. }
  636. /****************************************************************************
  637. rm - Decodes r/m part of modrm uint8_t for dst (unless TO_REG) part of icode
  638. ***************************************************************************/
  639. static void rm(int i)
  640. {
  641. uint8_t mod = *pInst >> 6;
  642. uint8_t rm = *pInst++ & 7;
  643. switch (mod) {
  644. case 0: /* No disp unless rm == 6 */
  645. if (rm == 6) {
  646. setAddress(i, true, SegPrefix, 0, getWord());
  647. pIcode->ll()->setFlags(WORD_OFF);
  648. }
  649. else
  650. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, 0);
  651. break;
  652. case 1: /* 1 uint8_t disp */
  653. setAddress(i, true, SegPrefix, rm+INDEX_BX_SI, (uint16_t)signex(*pInst++));
  654. break;
  655. case 2: /* 2 uint8_t disp */
  656. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, getWord());
  657. pIcode->ll()->setFlags(WORD_OFF);
  658. break;
  659. case 3: /* reg */
  660. setAddress(i, true, 0, rm + rAX, 0);
  661. break;
  662. }
  663. //pIcode->insn.get_dest()->
  664. if ((stateTable[i].flg & NSP) and (pIcode->ll()->src().getReg2()==rSP or
  665. pIcode->ll()->m_dst.getReg2()==rSP))
  666. pIcode->ll()->setFlags(NOT_HLL);
  667. }
  668. /****************************************************************************
  669. modrm - Sets up src and dst from modrm uint8_t
  670. ***************************************************************************/
  671. static void modrm(int i)
  672. {
  673. setAddress(i, false, 0, REG(*pInst) + rAX, 0);
  674. rm(i);
  675. }
  676. /****************************************************************************
  677. segrm - seg encoded as reg of modrm
  678. ****************************************************************************/
  679. static void segrm(int i)
  680. {
  681. int reg = REG(*pInst) + rES;
  682. if (reg > rDS or (reg == rCS and (stateTable[i].flg & TO_REG)))
  683. pIcode->ll()->setOpcode((llIcode)0); // setCBW because it has that index
  684. else {
  685. setAddress(i, false, 0, (int16_t)reg, 0);
  686. rm(i);
  687. }
  688. }
  689. /****************************************************************************
  690. regop - src/dst reg encoded as low 3 bits of opcode
  691. ***************************************************************************/
  692. static void regop(int i)
  693. {
  694. setAddress(i, false, 0, ((int16_t)i & 0x7) + rAX, 0);
  695. pIcode->ll()->replaceDst(pIcode->ll()->src());
  696. }
  697. /*****************************************************************************
  698. segop - seg encoded in middle of opcode
  699. *****************************************************************************/
  700. static void segop(int i)
  701. {
  702. if(i==0x1E) {
  703. // printf("es");
  704. }
  705. setAddress(i, true, 0, (((int16_t)i & 0x18) >> 3) + rES, 0);
  706. }
  707. /****************************************************************************
  708. axImp - Plugs an implied AX dst
  709. ***************************************************************************/
  710. static void axImp(int i)
  711. {
  712. setAddress(i, true, 0, rAX, 0);
  713. }
  714. /* Implied AX source */
  715. static void axSrcIm (int )
  716. {
  717. pIcode->ll()->replaceSrc(rAX);//src.regi = rAX;
  718. }
  719. /* Implied AL source */
  720. static void alImp (int )
  721. {
  722. pIcode->ll()->replaceSrc(rAL);//src.regi = rAL;
  723. }
  724. /*****************************************************************************
  725. memImp - Plugs implied src memory operand with any segment override
  726. ****************************************************************************/
  727. static void memImp(int i)
  728. {
  729. setAddress(i, false, SegPrefix, 0, 0);
  730. }
  731. /****************************************************************************
  732. memOnly - Instruction is not valid if modrm refers to register (i.e. mod == 3)
  733. ***************************************************************************/
  734. static void memOnly(int )
  735. {
  736. if ((*pInst & 0xC0) == 0xC0)
  737. pIcode->ll()->setOpcode((llIcode)0);
  738. }
  739. /****************************************************************************
  740. memReg0 - modrm for 'memOnly' and Reg field must also be 0
  741. ****************************************************************************/
  742. static void memReg0(int i)
  743. {
  744. if (REG(*pInst) or (*pInst & 0xC0) == 0xC0)
  745. pIcode->ll()->setOpcode((llIcode)0);
  746. else
  747. rm(i);
  748. }
  749. /***************************************************************************
  750. immed - Sets up dst and opcode from modrm uint8_t
  751. **************************************************************************/
  752. static void immed(int i)
  753. {
  754. static llIcode immedTable[8] = {iADD, iOR, iADC, iSBB, iAND, iSUB, iXOR, iCMP};
  755. pIcode->ll()->setOpcode(immedTable[REG(*pInst)]) ;
  756. rm(i);
  757. if (pIcode->ll()->getOpcode() == iADD or pIcode->ll()->getOpcode() == iSUB)
  758. pIcode->ll()->clrFlags(NOT_HLL); /* Allow ADD/SUB SP, immed */
  759. }
  760. /****************************************************************************
  761. shift - Sets up dst and opcode from modrm uint8_t
  762. ***************************************************************************/
  763. static void shift(int i)
  764. {
  765. static llIcode shiftTable[8] =
  766. {
  767. (llIcode)iROL, (llIcode)iROR, (llIcode)iRCL, (llIcode)iRCR,
  768. (llIcode)iSHL, (llIcode)iSHR, (llIcode)0, (llIcode)iSAR};
  769. pIcode->ll()->setOpcode(shiftTable[REG(*pInst)]);
  770. rm(i);
  771. pIcode->ll()->replaceSrc(rCL); //src.regi =
  772. }
  773. /****************************************************************************
  774. trans - Sets up dst and opcode from modrm uint8_t
  775. ***************************************************************************/
  776. static void trans(int i)
  777. {
  778. static llIcode transTable[8] =
  779. {
  780. (llIcode)iINC, iDEC, (llIcode)iCALL, (llIcode)iCALLF,
  781. (llIcode)iJMP, (llIcode)iJMPF,(llIcode)iPUSH, (llIcode)0
  782. };
  783. LLInst *ll = pIcode->ll();
  784. // if(transTable[REG(*pInst)]==iPUSH) {
  785. // printf("es");
  786. // }
  787. if ((uint8_t)REG(*pInst) < 2 or not (stateTable[i].flg & B)) { /* INC & DEC */
  788. ll->setOpcode(transTable[REG(*pInst)]); /* valid on bytes */
  789. rm(i);
  790. ll->replaceSrc( pIcode->ll()->m_dst );
  791. if (ll->match(iJMP) or ll->match(iCALL) or ll->match(iCALLF))
  792. ll->setFlags(NO_OPS);
  793. else if (ll->match(iINC) or ll->match(iPUSH) or ll->match(iDEC))
  794. ll->setFlags(NO_SRC);
  795. }
  796. }
  797. /****************************************************************************
  798. arith - Sets up dst and opcode from modrm uint8_t
  799. ****************************************************************************/
  800. static void arith(int i)
  801. {
  802. uint8_t opcode;
  803. static llIcode arithTable[8] =
  804. {
  805. iTEST, (llIcode)0, iNOT, iNEG,
  806. iMUL , iIMUL, iDIV, iIDIV
  807. };
  808. opcode = arithTable[REG(*pInst)];
  809. pIcode->ll()->setOpcode((llIcode)opcode);
  810. rm(i);
  811. if (opcode == iTEST)
  812. {
  813. if (stateTable[i].flg & B)
  814. data1(i);
  815. else
  816. data2(i);
  817. }
  818. else if (not (opcode == iNOT or opcode == iNEG))
  819. {
  820. pIcode->ll()->replaceSrc( pIcode->ll()->m_dst );
  821. setAddress(i, true, 0, rAX, 0); /* dst = AX */
  822. }
  823. else if (opcode == iNEG or opcode == iNOT)
  824. pIcode->ll()->setFlags(NO_SRC);
  825. if ((opcode == iDIV) or (opcode == iIDIV))
  826. {
  827. if ( not pIcode->ll()->testFlags(B) )
  828. pIcode->ll()->setFlags(IM_TMP_DST);
  829. }
  830. }
  831. /*****************************************************************************
  832. data1 - Sets up immed from 1 uint8_t data
  833. *****************************************************************************/
  834. static void data1(int i)
  835. {
  836. pIcode->ll()->replaceSrc(LLOperand::CreateImm2((stateTable[i].flg & S_EXT)? signex(*pInst++): *pInst++,1));
  837. pIcode->ll()->setFlags(I);
  838. }
  839. /*****************************************************************************
  840. data2 - Sets up immed from 2 uint8_t data
  841. ****************************************************************************/
  842. static void data2(int )
  843. {
  844. if (relocItem(pInst))
  845. pIcode->ll()->setFlags(SEG_IMMED);
  846. /* ENTER is a special case, it does not take a destination operand,
  847. * but this field is being used as the number of bytes to allocate
  848. * on the stack. The procedure level is stored in the immediate
  849. * field. There is no source operand; therefore, the flag flg is
  850. * set to NO_OPS. */
  851. if (pIcode->ll()->getOpcode() == iENTER)
  852. {
  853. pIcode->ll()->m_dst.off = getWord();
  854. pIcode->ll()->setFlags(NO_OPS);
  855. }
  856. else
  857. pIcode->ll()->replaceSrc(getWord());
  858. pIcode->ll()->setFlags(I);
  859. }
  860. /****************************************************************************
  861. dispM - 2 uint8_t offset without modrm (== mod 0, rm 6) (Note:TO_REG bits are
  862. reversed)
  863. ****************************************************************************/
  864. static void dispM(int i)
  865. {
  866. setAddress(i, false, SegPrefix, 0, getWord());
  867. }
  868. /****************************************************************************
  869. dispN - 2 uint8_t disp as immed relative to ip
  870. ****************************************************************************/
  871. static void dispN(int )
  872. {
  873. //PROG &prog(Project::get()->prog);
  874. /*long off = (short)*/getWord(); /* Signed displacement */
  875. /* Note: the result of the subtraction could be between 32k and 64k, and
  876. still be positive; it is an offset from prog.Image. So this must be
  877. treated as unsigned */
  878. // decodeBranchTgt();
  879. }
  880. /***************************************************************************
  881. dispS - 1 byte disp as immed relative to ip
  882. ***************************************************************************/
  883. static void dispS(int )
  884. {
  885. /*long off =*/ signex(*pInst++); /* Signed displacement */
  886. // decodeBranchTgt();
  887. }
  888. /****************************************************************************
  889. dispF - 4 byte disp as immed 20-bit target address
  890. ***************************************************************************/
  891. static void dispF(int i)
  892. {
  893. uint16_t off = (unsigned)getWord();
  894. uint16_t seg = (unsigned)getWord();
  895. setAddress(i, true, seg, 0, off);
  896. // decodeBranchTgt();
  897. }
  898. /****************************************************************************
  899. prefix - picks up prefix uint8_t for following instruction (LOCK is ignored
  900. on purpose)
  901. ****************************************************************************/
  902. static void prefix(int )
  903. {
  904. if (pIcode->ll()->getOpcode() == iREPE or pIcode->ll()->getOpcode() == iREPNE)
  905. RepPrefix = pIcode->ll()->getOpcode();
  906. else
  907. SegPrefix = pIcode->ll()->getOpcode();
  908. }
  909. inline void BumpOpcode(LLInst &ll)
  910. {
  911. llIcode ic((llIcode)ll.getOpcode());
  912. ic = (llIcode)(((int)ic)+1); // Bump this icode via the int type
  913. ll.setOpcode(ic);
  914. }
  915. /*****************************************************************************
  916. strop - checks RepPrefix and converts string instructions accordingly
  917. *****************************************************************************/
  918. static void strop(int )
  919. {
  920. if (RepPrefix)
  921. {
  922. if ( pIcode->ll()->match(iCMPS) or pIcode->ll()->match(iSCAS) )
  923. {
  924. if(pIcode->insn.prefix & insn_rep_zero)
  925. {
  926. BumpOpcode(*pIcode->ll()); // iCMPS -> iREPE_CMPS
  927. BumpOpcode(*pIcode->ll());
  928. }
  929. else if(pIcode->insn.prefix & insn_rep_notzero)
  930. BumpOpcode(*pIcode->ll()); // iX -> iREPNE_X
  931. }
  932. else
  933. if(pIcode->insn.prefix & insn_rep_zero)
  934. BumpOpcode(*pIcode->ll()); // iX -> iREPE_X
  935. if (pIcode->ll()->match(iREP_LODS) )
  936. pIcode->ll()->setFlags(NOT_HLL);
  937. RepPrefix = 0;
  938. }
  939. }
  940. /***************************************************************************
  941. escop - esc operands
  942. ***************************************************************************/
  943. static void escop(int i)
  944. {
  945. pIcode->ll()->replaceSrc(REG(*pInst) + (uint32_t)((i & 7) << 3));
  946. pIcode->ll()->setFlags(I);
  947. rm(i);
  948. }
  949. /****************************************************************************
  950. const1
  951. ****************************************************************************/
  952. static void const1(int )
  953. {
  954. pIcode->ll()->replaceSrc(1);
  955. pIcode->ll()->setFlags(I);
  956. }
  957. /*****************************************************************************
  958. const3
  959. ****************************************************************************/
  960. static void const3(int )
  961. {
  962. pIcode->ll()->replaceSrc(3);
  963. pIcode->ll()->setFlags(I);
  964. }
  965. /****************************************************************************
  966. none1
  967. ****************************************************************************/
  968. static void none1(int )
  969. {
  970. }
  971. /****************************************************************************
  972. none2 - Sets the NO_OPS flag if the operand is immediate
  973. ****************************************************************************/
  974. static void none2(int )
  975. {
  976. if ( pIcode->ll()->testFlags(I) )
  977. pIcode->ll()->setFlags(NO_OPS);
  978. }
  979. /****************************************************************************
  980. Checks for int 34 to int 3B - if so, converts to ESC nn instruction
  981. ****************************************************************************/
  982. static void checkInt(int )
  983. {
  984. uint16_t wOp = (uint16_t) pIcode->ll()->src().getImm2();
  985. if ((wOp >= 0x34) and (wOp <= 0x3B))
  986. {
  987. /* This is a Borland/Microsoft floating point emulation instruction.
  988. Treat as if it is an ESC opcode */
  989. pIcode->ll()->replaceSrc(wOp - 0x34);
  990. pIcode->ll()->set(iESC,FLOAT_OP);
  991. escop(wOp - 0x34 + 0xD8);
  992. }
  993. }