scanner.cpp 38 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881
  1. /*****************************************************************************
  2. * dcc project scanner module
  3. * Implements a simple state driven scanner to convert 8086 machine code into
  4. * I-code
  5. * (C) Cristina Cifuentes, Jeff Ledermann
  6. ****************************************************************************/
  7. #include <cstring>
  8. #include "dcc.h"
  9. #include "scanner.h"
  10. #include "project.h"
  11. /* Parser flags */
  12. #define TO_REG 0x000100 /* rm is source */
  13. #define S_EXT 0x000200 /* sign extend */
  14. #define OP386 0x000400 /* 386 op-code */
  15. #define NSP 0x000800 /* NOT_HLL if SP is src or dst */
  16. #define ICODEMASK 0xFF00FF /* Masks off parser flags */
  17. static void rm(int i);
  18. static void modrm(int i);
  19. static void segrm(int i);
  20. static void data1(int i);
  21. static void data2(int i);
  22. static void regop(int i);
  23. static void segop(int i);
  24. static void strop(int i);
  25. static void escop(int i);
  26. static void axImp(int i);
  27. static void alImp(int i);
  28. static void axSrcIm(int i);
  29. static void memImp(int i);
  30. static void memReg0(int i);
  31. static void memOnly(int i);
  32. static void dispM(int i);
  33. static void dispS(int i);
  34. static void dispN(int i);
  35. static void dispF(int i);
  36. static void prefix(int i);
  37. static void immed(int i);
  38. static void shift(int i);
  39. static void arith(int i);
  40. static void trans(int i);
  41. static void const1(int i);
  42. static void const3(int i);
  43. static void none1(int i);
  44. static void none2(int i);
  45. static void checkInt(int i);
  46. #define iZERO (llIcode)0 // For neatness
  47. #define IC llIcode
  48. static struct {
  49. void (*state1)(int);
  50. void (*state2)(int);
  51. uint32_t flg;
  52. llIcode opcode;
  53. uint8_t df;
  54. uint8_t uf;
  55. } stateTable[] = {
  56. { modrm, none2, B , iADD , Sf | Zf | Cf , 0 }, /* 00 */
  57. { modrm, none2, 0 , iADD , Sf | Zf | Cf , 0 }, /* 01 */
  58. { modrm, none2, TO_REG | B , iADD , Sf | Zf | Cf , 0 }, /* 02 */
  59. { modrm, none2, TO_REG , iADD , Sf | Zf | Cf , 0 }, /* 03 */
  60. { data1, axImp, B , iADD , Sf | Zf | Cf , 0 }, /* 04 */
  61. { data2, axImp, 0 , iADD , Sf | Zf | Cf , 0 }, /* 05 */
  62. { segop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 06 */
  63. { segop, none2, NO_SRC , iPOP , 0 , 0 }, /* 07 */
  64. { modrm, none2, B , iOR , Sf | Zf | Cf , 0 }, /* 08 */
  65. { modrm, none2, NSP , iOR , Sf | Zf | Cf , 0 }, /* 09 */
  66. { modrm, none2, TO_REG | B , iOR , Sf | Zf | Cf , 0 }, /* 0A */
  67. { modrm, none2, TO_REG | NSP , iOR , Sf | Zf | Cf , 0 }, /* 0B */
  68. { data1, axImp, B , iOR , Sf | Zf | Cf , 0 }, /* 0C */
  69. { data2, axImp, 0 , iOR , Sf | Zf | Cf , 0 }, /* 0D */
  70. { segop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 0E */
  71. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 0F */
  72. { modrm, none2, B , iADC , Sf | Zf | Cf , Cf }, /* 10 */
  73. { modrm, none2, NSP , iADC , Sf | Zf | Cf , Cf }, /* 11 */
  74. { modrm, none2, TO_REG | B , iADC , Sf | Zf | Cf , Cf }, /* 12 */
  75. { modrm, none2, TO_REG | NSP , iADC , Sf | Zf | Cf , Cf }, /* 13 */
  76. { data1, axImp, B , iADC , Sf | Zf | Cf , Cf }, /* 14 */
  77. { data2, axImp, 0 , iADC , Sf | Zf | Cf , Cf }, /* 15 */
  78. { segop, none2, NOT_HLL | NO_SRC , iPUSH , 0 , 0 }, /* 16 */
  79. { segop, none2, NOT_HLL | NO_SRC , iPOP , 0 , 0 }, /* 17 */
  80. { modrm, none2, B , iSBB , Sf | Zf | Cf , Cf }, /* 18 */
  81. { modrm, none2, NSP , iSBB , Sf | Zf | Cf , Cf }, /* 19 */
  82. { modrm, none2, TO_REG | B , iSBB , Sf | Zf | Cf , Cf }, /* 1A */
  83. { modrm, none2, TO_REG | NSP , iSBB , Sf | Zf | Cf , Cf }, /* 1B */
  84. { data1, axImp, B , iSBB , Sf | Zf | Cf , Cf }, /* 1C */
  85. { data2, axImp, 0 , iSBB , Sf | Zf | Cf , Cf }, /* 1D */
  86. { segop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 1E */
  87. { segop, none2, NO_SRC , iPOP , 0 , 0 }, /* 1F */
  88. { modrm, none2, B , iAND , Sf | Zf | Cf , 0 }, /* 20 */
  89. { modrm, none2, NSP , iAND , Sf | Zf | Cf , 0 }, /* 21 */
  90. { modrm, none2, TO_REG | B , iAND , Sf | Zf | Cf , 0 }, /* 22 */
  91. { modrm, none2, TO_REG | NSP , iAND , Sf | Zf | Cf , 0 }, /* 23 */
  92. { data1, axImp, B , iAND , Sf | Zf | Cf , 0 }, /* 24 */
  93. { data2, axImp, 0 , iAND , Sf | Zf | Cf , 0 }, /* 25 */
  94. { prefix, none2, 0 , (IC)rES,0 , 0 }, /* 26 */
  95. { none1, axImp, NOT_HLL | B|NO_SRC , iDAA , Sf | Zf | Cf , 0 }, /* 27 */
  96. { modrm, none2, B , iSUB , Sf | Zf | Cf , 0 }, /* 28 */
  97. { modrm, none2, 0 , iSUB , Sf | Zf | Cf , 0 }, /* 29 */
  98. { modrm, none2, TO_REG | B , iSUB , Sf | Zf | Cf , 0 }, /* 2A */
  99. { modrm, none2, TO_REG , iSUB , Sf | Zf | Cf , 0 }, /* 2B */
  100. { data1, axImp, B , iSUB , Sf | Zf | Cf , 0 }, /* 2C */
  101. { data2, axImp, 0 , iSUB , Sf | Zf | Cf , 0 }, /* 2D */
  102. { prefix, none2, 0 , (IC)rCS,0 , 0 }, /* 2E */
  103. { none1, axImp, NOT_HLL | B|NO_SRC , iDAS , Sf | Zf | Cf , 0 }, /* 2F */
  104. { modrm, none2, B , iXOR , Sf | Zf | Cf , 0 }, /* 30 */
  105. { modrm, none2, NSP , iXOR , Sf | Zf | Cf , 0 }, /* 31 */
  106. { modrm, none2, TO_REG | B , iXOR , Sf | Zf | Cf , 0 }, /* 32 */
  107. { modrm, none2, TO_REG | NSP , iXOR , Sf | Zf | Cf , 0 }, /* 33 */
  108. { data1, axImp, B , iXOR , Sf | Zf | Cf , 0 }, /* 34 */
  109. { data2, axImp, 0 , iXOR , Sf | Zf | Cf , 0 }, /* 35 */
  110. { prefix, none2, 0 , (IC)rSS,0 , 0 }, /* 36 */
  111. { none1, axImp, NOT_HLL | NO_SRC , iAAA , Sf | Zf | Cf , 0 }, /* 37 */
  112. { modrm, none2, B , iCMP , Sf | Zf | Cf , 0 }, /* 38 */
  113. { modrm, none2, NSP , iCMP , Sf | Zf | Cf , 0 }, /* 39 */
  114. { modrm, none2, TO_REG | B , iCMP , Sf | Zf | Cf , 0 }, /* 3A */
  115. { modrm, none2, TO_REG | NSP , iCMP , Sf | Zf | Cf , 0 }, /* 3B */
  116. { data1, axImp, B , iCMP , Sf | Zf | Cf , 0 }, /* 3C */
  117. { data2, axImp, 0 , iCMP , Sf | Zf | Cf , 0 }, /* 3D */
  118. { prefix, none2, 0 , (IC)rDS,0 , 0 }, /* 3E */
  119. { none1, axImp, NOT_HLL | NO_SRC , iAAS , Sf | Zf | Cf , 0 }, /* 3F */
  120. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 40 */
  121. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 41 */
  122. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 42 */
  123. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 43 */
  124. { regop, none2, NOT_HLL , iINC , Sf | Zf , 0 }, /* 44 */
  125. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 45 */
  126. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 46 */
  127. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 47 */
  128. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 48 */
  129. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 49 */
  130. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 4A */
  131. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 4B */
  132. { regop, none2, NOT_HLL , iDEC , Sf | Zf , 0 }, /* 4C */
  133. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 4D */
  134. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 4E */
  135. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 4F */
  136. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 50 */
  137. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 51 */
  138. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 52 */
  139. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 53 */
  140. { regop, none2, NOT_HLL | NO_SRC , iPUSH , 0 , 0 }, /* 54 */
  141. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 55 */
  142. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 56 */
  143. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 57 */
  144. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 58 */
  145. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 59 */
  146. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5A */
  147. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5B */
  148. { regop, none2, NOT_HLL | NO_SRC , iPOP , 0 , 0 }, /* 5C */
  149. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5D */
  150. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5E */
  151. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5F */
  152. { none1, none2, NOT_HLL | NO_OPS , iPUSHA, 0 , 0 }, /* 60 */
  153. { none1, none2, NOT_HLL | NO_OPS , iPOPA , 0 , 0 }, /* 61 */
  154. { memOnly, modrm, TO_REG | NSP , iBOUND, 0 , 0 }, /* 62 */
  155. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 63 */
  156. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 64 */
  157. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 65 */
  158. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 66 */
  159. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 67 */
  160. { data2, none2, NO_SRC , iPUSH , 0 , 0 }, /* 68 */
  161. { modrm, data2, TO_REG | NSP , iIMUL , Sf | Zf | Cf , 0 }, /* 69 */
  162. { data1, none2, S_EXT | NO_SRC , iPUSH , 0 , 0 }, /* 6A */
  163. { modrm, data1, TO_REG | NSP | S_EXT , iIMUL , Sf | Zf | Cf , 0 }, /* 6B */
  164. { strop, memImp, NOT_HLL | B|IM_OPS , iINS , 0 , Df}, /* 6C */
  165. { strop, memImp, NOT_HLL | IM_OPS , iINS , 0 , Df}, /* 6D */
  166. { strop, memImp, NOT_HLL | B|IM_OPS , iOUTS , 0 , Df}, /* 6E */
  167. { strop, memImp, NOT_HLL | IM_OPS , iOUTS , 0 , Df}, /* 6F */
  168. { dispS, none2, NOT_HLL , iJO , 0 , 0 }, /* 70 */
  169. { dispS, none2, NOT_HLL , iJNO , 0 , 0 }, /* 71 */
  170. { dispS, none2, 0 , iJB , 0 , Cf }, /* 72 */
  171. { dispS, none2, 0 , iJAE , 0 , Cf }, /* 73 */
  172. { dispS, none2, 0 , iJE , 0 , Zf }, /* 74 */
  173. { dispS, none2, 0 , iJNE , 0 , Zf }, /* 75 */
  174. { dispS, none2, 0 , iJBE , 0 , Zf | Cf }, /* 76 */
  175. { dispS, none2, 0 , iJA , 0 , Zf | Cf }, /* 77 */
  176. { dispS, none2, 0 , iJS , 0 , Sf }, /* 78 */
  177. { dispS, none2, 0 , iJNS , 0 , Sf }, /* 79 */
  178. { dispS, none2, NOT_HLL , iJP , 0 , 0 }, /* 7A */
  179. { dispS, none2, NOT_HLL , iJNP , 0 , 0 }, /* 7B */
  180. { dispS, none2, 0 , iJL , 0 , Sf }, /* 7C */
  181. { dispS, none2, 0 , iJGE , 0 , Sf }, /* 7D */
  182. { dispS, none2, 0 , iJLE , 0 , Sf | Zf }, /* 7E */
  183. { dispS, none2, 0 , iJG , 0 , Sf | Zf }, /* 7F */
  184. { immed, data1, B , iZERO , 0 , 0 }, /* 80 */
  185. { immed, data2, NSP , iZERO , 0 , 0 }, /* 81 */
  186. { immed, data1, B , iZERO , 0 , 0 }, /* 82 */ /* ?? */
  187. { immed, data1, NSP | S_EXT , iZERO , 0 , 0 }, /* 83 */
  188. { modrm, none2, TO_REG | B , iTEST , Sf | Zf | Cf, 0 }, /* 84 */
  189. { modrm, none2, TO_REG | NSP , iTEST , Sf | Zf | Cf, 0 }, /* 85 */
  190. { modrm, none2, TO_REG | B , iXCHG , 0 , 0 }, /* 86 */
  191. { modrm, none2, TO_REG | NSP , iXCHG , 0 , 0 }, /* 87 */
  192. { modrm, none2, B , iMOV , 0 , 0 }, /* 88 */
  193. { modrm, none2, 0 , iMOV , 0 , 0 }, /* 89 */
  194. { modrm, none2, TO_REG | B , iMOV , 0 , 0 }, /* 8A */
  195. { modrm, none2, TO_REG , iMOV , 0 , 0 }, /* 8B */
  196. { segrm, none2, NSP , iMOV , 0 , 0 }, /* 8C */
  197. { memOnly, modrm, TO_REG | NSP , iLEA , 0 , 0 }, /* 8D */
  198. { segrm, none2, TO_REG | NSP , iMOV , 0 , 0 }, /* 8E */
  199. { memReg0, none2, NO_SRC , iPOP , 0 , 0 }, /* 8F */
  200. { none1, none2, NO_OPS , iNOP , 0 , 0 }, /* 90 */
  201. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 91 */
  202. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 92 */
  203. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 93 */
  204. { regop, axImp, NOT_HLL , iXCHG , 0 , 0 }, /* 94 */
  205. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 95 */
  206. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 96 */
  207. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 97 */
  208. { alImp, axImp, SRC_B | S_EXT , iSIGNEX,0 , 0 }, /* 98 */
  209. {axSrcIm, axImp, IM_DST | S_EXT , iSIGNEX,0 , 0 }, /* 99 */
  210. { dispF, none2, 0 , iCALLF ,0 , 0 }, /* 9A */
  211. { none1, none2, FLOAT_OP| NO_OPS , iWAIT , 0 , 0 }, /* 9B */
  212. { none1, none2, NOT_HLL | NO_OPS , iPUSHF, 0 , 0 }, /* 9C */
  213. { none1, none2, NOT_HLL | NO_OPS , iPOPF , Sf | Zf | Cf | Df,}, /* 9D */
  214. { none1, none2, NOT_HLL | NO_OPS , iSAHF , Sf | Zf | Cf, 0 }, /* 9E */
  215. { none1, none2, NOT_HLL | NO_OPS , iLAHF , 0 , Sf | Zf | Cf }, /* 9F */
  216. { dispM, axImp, B , iMOV , 0 , 0 }, /* A0 */
  217. { dispM, axImp, 0 , iMOV , 0 , 0 }, /* A1 */
  218. { dispM, axImp, TO_REG | B , iMOV , 0 , 0 }, /* A2 */
  219. { dispM, axImp, TO_REG , iMOV , 0 , 0 }, /* A3 */
  220. { strop, memImp, B | IM_OPS , iMOVS , 0 , Df }, /* A4 */
  221. { strop, memImp, IM_OPS , iMOVS , 0 , Df }, /* A5 */
  222. { strop, memImp, B | IM_OPS , iCMPS , Sf | Zf | Cf, Df }, /* A6 */
  223. { strop, memImp, IM_OPS , iCMPS , Sf | Zf | Cf, Df }, /* A7 */
  224. { data1, axImp, B , iTEST , Sf | Zf | Cf, 0 }, /* A8 */
  225. { data2, axImp, 0 , iTEST , Sf | Zf | Cf, 0 }, /* A9 */
  226. { strop, memImp, B | IM_OPS , iSTOS , 0 , Df }, /* AA */
  227. { strop, memImp, IM_OPS , iSTOS , 0 , Df }, /* AB */
  228. { strop, memImp, B | IM_OPS , iLODS , 0 , Df }, /* AC */
  229. { strop, memImp, IM_OPS , iLODS , 0 , Df }, /* AD */
  230. { strop, memImp, B | IM_OPS , iSCAS , Sf | Zf | Cf, Df }, /* AE */
  231. { strop, memImp, IM_OPS , iSCAS , Sf | Zf | Cf, Df }, /* AF */
  232. { regop, data1, B , iMOV , 0 , 0 }, /* B0 */
  233. { regop, data1, B , iMOV , 0 , 0 }, /* B1 */
  234. { regop, data1, B , iMOV , 0 , 0 }, /* B2 */
  235. { regop, data1, B , iMOV , 0 , 0 }, /* B3 */
  236. { regop, data1, B , iMOV , 0 , 0 }, /* B4 */
  237. { regop, data1, B , iMOV , 0 , 0 }, /* B5 */
  238. { regop, data1, B , iMOV , 0 , 0 }, /* B6 */
  239. { regop, data1, B , iMOV , 0 , 0 }, /* B7 */
  240. { regop, data2, 0 , iMOV , 0 , 0 }, /* B8 */
  241. { regop, data2, 0 , iMOV , 0 , 0 }, /* B9 */
  242. { regop, data2, 0 , iMOV , 0 , 0 }, /* BA */
  243. { regop, data2, 0 , iMOV , 0 , 0 }, /* BB */
  244. { regop, data2, NOT_HLL , iMOV , 0 , 0 }, /* BC */
  245. { regop, data2, 0 , iMOV , 0 , 0 }, /* BD */
  246. { regop, data2, 0 , iMOV , 0 , 0 }, /* BE */
  247. { regop, data2, 0 , iMOV , 0 , 0 }, /* BF */
  248. { shift, data1, B , iZERO , 0 , 0 }, /* C0 */
  249. { shift, data1, NSP | SRC_B , iZERO , 0 , 0 }, /* C1 */
  250. { data2, none2, 0 , iRET , 0 , 0 }, /* C2 */
  251. { none1, none2, NO_OPS , iRET , 0 , 0 }, /* C3 */
  252. { memOnly, modrm, TO_REG | NSP , iLES , 0 , 0 }, /* C4 */
  253. { memOnly, modrm, TO_REG | NSP , iLDS , 0 , 0 }, /* C5 */
  254. { memReg0, data1, B , iMOV , 0 , 0 }, /* C6 */
  255. { memReg0, data2, 0 , iMOV , 0 , 0 }, /* C7 */
  256. { data2, data1, 0 , iENTER, 0 , 0 }, /* C8 */
  257. { none1, none2, NO_OPS , iLEAVE, 0 , 0 }, /* C9 */
  258. { data2, none2, 0 , iRETF , 0 , 0 }, /* CA */
  259. { none1, none2, NO_OPS , iRETF , 0 , 0 }, /* CB */
  260. { const3, none2, NOT_HLL , iINT , 0 , 0 }, /* CC */
  261. { data1,checkInt, NOT_HLL , iINT , 0 , 0 }, /* CD */
  262. { none1, none2, NOT_HLL | NO_OPS , iINTO , 0 , 0 }, /* CE */
  263. { none1, none2, NOT_HLL | NO_OPS , iIRET , 0 , 0 }, /* Cf */
  264. { shift, const1, B , iZERO , 0 , 0 }, /* D0 */
  265. { shift, const1, SRC_B , iZERO , 0 , 0 }, /* D1 */
  266. { shift, none1, B , iZERO , 0 , 0 }, /* D2 */
  267. { shift, none1, SRC_B , iZERO , 0 , 0 }, /* D3 */
  268. { data1, axImp, NOT_HLL , iAAM , Sf | Zf | Cf, 0 }, /* D4 */
  269. { data1, axImp, NOT_HLL , iAAD , Sf | Zf | Cf, 0 }, /* D5 */
  270. { none1, none2, 0 , iZERO , 0 , 0 }, /* D6 */
  271. { memImp, axImp, NOT_HLL | B| IM_OPS, iXLAT , 0 , 0 }, /* D7 */
  272. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* D8 */
  273. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* D9 */
  274. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DA */
  275. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DB */
  276. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DC */
  277. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DD */
  278. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DE */
  279. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* Df */
  280. { dispS, none2, 0 , iLOOPNE,0 , Zf }, /* E0 */
  281. { dispS, none2, 0 , iLOOPE, 0 , Zf }, /* E1 */
  282. { dispS, none2, 0 , iLOOP , 0 , 0 }, /* E2 */
  283. { dispS, none2, 0 , iJCXZ , 0 , 0 }, /* E3 */
  284. { data1, axImp, NOT_HLL | B|NO_SRC , iIN , 0 , 0 }, /* E4 */
  285. { data1, axImp, NOT_HLL | NO_SRC , iIN , 0 , 0 }, /* E5 */
  286. { data1, axImp, NOT_HLL | B|NO_SRC , iOUT , 0 , 0 }, /* E6 */
  287. { data1, axImp, NOT_HLL | NO_SRC , iOUT , 0 , 0 }, /* E7 */
  288. { dispN, none2, 0 , iCALL , 0 , 0 }, /* E8 */
  289. { dispN, none2, 0 , iJMP , 0 , 0 }, /* E9 */
  290. { dispF, none2, 0 , iJMPF , 0 , 0 }, /* EA */
  291. { dispS, none2, 0 , iJMP , 0 , 0 }, /* EB */
  292. { none1, axImp, NOT_HLL | B|NO_SRC , iIN , 0 , 0 }, /* EC */
  293. { none1, axImp, NOT_HLL | NO_SRC , iIN , 0 , 0 }, /* ED */
  294. { none1, axImp, NOT_HLL | B|NO_SRC , iOUT , 0 , 0 }, /* EE */
  295. { none1, axImp, NOT_HLL | NO_SRC , iOUT , 0 , 0 }, /* EF */
  296. { none1, none2, NOT_HLL | NO_OPS , iLOCK , 0 , 0 }, /* F0 */
  297. { none1, none2, 0 , iZERO , 0 , 0 }, /* F1 */
  298. { prefix, none2, 0 , iREPNE, 0 , 0 }, /* F2 */
  299. { prefix, none2, 0 , iREPE , 0 , 0 }, /* F3 */
  300. { none1, none2, NOT_HLL | NO_OPS , iHLT , 0 , 0 }, /* F4 */
  301. { none1, none2, NO_OPS , iCMC , Cf, Cf }, /* F5 */
  302. { arith, none1, B , iZERO , 0 , 0 }, /* F6 */
  303. { arith, none1, NSP , iZERO , 0 , 0 }, /* F7 */
  304. { none1, none2, NO_OPS , iCLC , Cf, 0 }, /* F8 */
  305. { none1, none2, NO_OPS , iSTC , Cf, 0 }, /* F9 */
  306. { none1, none2, NOT_HLL | NO_OPS , iCLI , 0 , 0 }, /* FA */
  307. { none1, none2, NOT_HLL | NO_OPS , iSTI , 0 , 0 }, /* FB */
  308. { none1, none2, NO_OPS , iCLD , Df, 0 }, /* FC */
  309. { none1, none2, NO_OPS , iSTD , Df, 0 }, /* FD */
  310. { trans, none1, B , iZERO , 0 , 0 }, /* FE */
  311. { trans, none1, NSP , iZERO , 0 , 0 } /* FF */
  312. } ;
  313. static uint16_t SegPrefix, RepPrefix;
  314. static uint8_t *pInst; /* Ptr. to current uint8_t of instruction */
  315. static ICODE * pIcode; /* Ptr to Icode record filled in by scan() */
  316. /*****************************************************************************
  317. Scans one machine instruction at offset ip in prog.Image and returns error.
  318. At the same time, fill in low-level icode details for the scanned inst.
  319. ****************************************************************************/
  320. eErrorId scan(uint32_t ip, ICODE &p)
  321. {
  322. PROG &prog(Project::get()->prog);
  323. int op;
  324. p = ICODE();
  325. p.type = LOW_LEVEL;
  326. p.ll()->label = ip; /* ip is absolute offset into image*/
  327. if (ip >= (uint32_t)prog.cbImage)
  328. {
  329. return (IP_OUT_OF_RANGE);
  330. }
  331. SegPrefix = RepPrefix = 0;
  332. pInst = prog.Image + ip;
  333. pIcode = &p;
  334. do
  335. {
  336. op = *pInst++; /* First state - trivial */
  337. /* Convert to Icode.opcode */
  338. p.ll()->set(stateTable[op].opcode,stateTable[op].flg & ICODEMASK);
  339. p.ll()->flagDU.d = stateTable[op].df;
  340. p.ll()->flagDU.u = stateTable[op].uf;
  341. (*stateTable[op].state1)(op); /* Second state */
  342. (*stateTable[op].state2)(op); /* Third state */
  343. } while (stateTable[op].state1 == prefix); /* Loop if prefix */
  344. if (p.ll()->getOpcode())
  345. {
  346. /* Save bytes of image used */
  347. p.ll()->numBytes = (uint8_t)((pInst - prog.Image) - ip);
  348. return ((SegPrefix)? FUNNY_SEGOVR: /* Seg. Override invalid */
  349. (RepPrefix ? FUNNY_REP: NO_ERR));/* REP prefix invalid */
  350. }
  351. /* Else opcode error */
  352. return ((stateTable[op].flg & OP386)? INVALID_386OP: INVALID_OPCODE);
  353. }
  354. /***************************************************************************
  355. relocItem - returns true if uint16_t pointed at is in relocation table
  356. **************************************************************************/
  357. static bool relocItem(uint8_t *p)
  358. {
  359. PROG &prog(Project::get()->prog);
  360. int i;
  361. uint32_t off = p - prog.Image;
  362. for (i = 0; i < prog.cReloc; i++)
  363. if (prog.relocTable[i] == off)
  364. return true;
  365. return false;
  366. }
  367. /***************************************************************************
  368. getWord - returns next uint16_t from image
  369. **************************************************************************/
  370. static uint16_t getWord(void)
  371. {
  372. uint16_t w = LH(pInst);
  373. pInst += 2;
  374. return w;
  375. }
  376. /****************************************************************************
  377. signex - returns uint8_t sign extended to int
  378. ***************************************************************************/
  379. static int signex(uint8_t b)
  380. {
  381. long s = b;
  382. return ((b & 0x80)? (int)(0xFFFFFF00 | s): (int)s);
  383. }
  384. /****************************************************************************
  385. * setAddress - Updates the source or destination field for the current
  386. * icode, based on fdst and the TO_REG flag.
  387. * Note: fdst == true is for the r/m part of the field (dest, unless TO_REG)
  388. * fdst == false is for reg part of the field
  389. ***************************************************************************/
  390. static void setAddress(int i, boolT fdst, uint16_t seg, int16_t reg, uint16_t off)
  391. {
  392. LLOperand *pm;
  393. /* If not to register (i.e. to r/m), and talking about r/m, then this is dest */
  394. pm = (!(stateTable[i].flg & TO_REG) == fdst) ?
  395. &pIcode->ll()->dst : &pIcode->ll()->src();
  396. /* Set segment. A later procedure (lookupAddr in proclist.c) will
  397. * provide the value of this segment in the field segValue. */
  398. if (seg) /* segment override */
  399. {
  400. pm->seg = pm->segOver = (eReg)seg;
  401. }
  402. else
  403. { /* no override, check indexed register */
  404. if ((reg >= INDEX_BX_SI) && (reg == INDEX_BP_SI || reg == INDEX_BP_DI || reg == INDEX_BP))
  405. {
  406. pm->seg = rSS; /* indexed on bp */
  407. }
  408. else
  409. {
  410. pm->seg = rDS; /* any other indexed reg */
  411. }
  412. }
  413. pm->regi = (eReg)reg;
  414. pm->off = (int16_t)off;
  415. if (reg && reg < INDEX_BX_SI && (stateTable[i].flg & B))
  416. {
  417. pm->regi = Machine_X86::subRegL(pm->regi);
  418. }
  419. if (seg) /* So we can catch invalid use of segment overrides */
  420. {
  421. SegPrefix = 0;
  422. }
  423. }
  424. /****************************************************************************
  425. rm - Decodes r/m part of modrm uint8_t for dst (unless TO_REG) part of icode
  426. ***************************************************************************/
  427. static void rm(int i)
  428. {
  429. uint8_t mod = *pInst >> 6;
  430. uint8_t rm = *pInst++ & 7;
  431. switch (mod) {
  432. case 0: /* No disp unless rm == 6 */
  433. if (rm == 6) {
  434. setAddress(i, true, SegPrefix, 0, getWord());
  435. pIcode->ll()->setFlags(WORD_OFF);
  436. }
  437. else
  438. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, 0);
  439. break;
  440. case 1: /* 1 uint8_t disp */
  441. setAddress(i, true, SegPrefix, rm+INDEX_BX_SI, (uint16_t)signex(*pInst++));
  442. break;
  443. case 2: /* 2 uint8_t disp */
  444. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, getWord());
  445. pIcode->ll()->setFlags(WORD_OFF);
  446. break;
  447. case 3: /* reg */
  448. setAddress(i, true, 0, rm + rAX, 0);
  449. break;
  450. }
  451. if ((stateTable[i].flg & NSP) && (pIcode->ll()->src().getReg2()==rSP ||
  452. pIcode->ll()->dst.getReg2()==rSP))
  453. pIcode->ll()->setFlags(NOT_HLL);
  454. }
  455. /****************************************************************************
  456. modrm - Sets up src and dst from modrm uint8_t
  457. ***************************************************************************/
  458. static void modrm(int i)
  459. {
  460. setAddress(i, false, 0, REG(*pInst) + rAX, 0);
  461. rm(i);
  462. }
  463. /****************************************************************************
  464. segrm - seg encoded as reg of modrm
  465. ****************************************************************************/
  466. static void segrm(int i)
  467. {
  468. int reg = REG(*pInst) + rES;
  469. if (reg > rDS || (reg == rCS && (stateTable[i].flg & TO_REG)))
  470. pIcode->ll()->setOpcode((llIcode)0); // setCBW because it has that index
  471. else {
  472. setAddress(i, false, 0, (int16_t)reg, 0);
  473. rm(i);
  474. }
  475. }
  476. /****************************************************************************
  477. regop - src/dst reg encoded as low 3 bits of opcode
  478. ***************************************************************************/
  479. static void regop(int i)
  480. {
  481. setAddress(i, false, 0, ((int16_t)i & 7) + rAX, 0);
  482. pIcode->ll()->replaceDst(LLOperand::CreateReg2(pIcode->ll()->src().getReg2()));
  483. // pIcode->ll()->dst.regi = pIcode->ll()->src.regi;
  484. }
  485. /*****************************************************************************
  486. segop - seg encoded in middle of opcode
  487. *****************************************************************************/
  488. static void segop(int i)
  489. {
  490. setAddress(i, true, 0, (((int16_t)i & 0x18) >> 3) + rES, 0);
  491. }
  492. /****************************************************************************
  493. axImp - Plugs an implied AX dst
  494. ***************************************************************************/
  495. static void axImp(int i)
  496. {
  497. setAddress(i, true, 0, rAX, 0);
  498. }
  499. /* Implied AX source */
  500. static void axSrcIm (int )
  501. {
  502. pIcode->ll()->replaceSrc(rAX);//src.regi = rAX;
  503. }
  504. /* Implied AL source */
  505. static void alImp (int )
  506. {
  507. pIcode->ll()->replaceSrc(rAL);//src.regi = rAL;
  508. }
  509. /*****************************************************************************
  510. memImp - Plugs implied src memory operand with any segment override
  511. ****************************************************************************/
  512. static void memImp(int i)
  513. {
  514. setAddress(i, false, SegPrefix, 0, 0);
  515. }
  516. /****************************************************************************
  517. memOnly - Instruction is not valid if modrm refers to register (i.e. mod == 3)
  518. ***************************************************************************/
  519. static void memOnly(int )
  520. {
  521. if ((*pInst & 0xC0) == 0xC0)
  522. pIcode->ll()->setOpcode((llIcode)0);
  523. }
  524. /****************************************************************************
  525. memReg0 - modrm for 'memOnly' and Reg field must also be 0
  526. ****************************************************************************/
  527. static void memReg0(int i)
  528. {
  529. if (REG(*pInst) || (*pInst & 0xC0) == 0xC0)
  530. pIcode->ll()->setOpcode((llIcode)0);
  531. else
  532. rm(i);
  533. }
  534. /***************************************************************************
  535. immed - Sets up dst and opcode from modrm uint8_t
  536. **************************************************************************/
  537. static void immed(int i)
  538. {
  539. static llIcode immedTable[8] = {iADD, iOR, iADC, iSBB, iAND, iSUB, iXOR, iCMP};
  540. static uint8_t uf[8] = { 0, 0, Cf, Cf, 0, 0, 0, 0 };
  541. pIcode->ll()->setOpcode(immedTable[REG(*pInst)]) ;
  542. pIcode->ll()->flagDU.u = uf[REG(*pInst)];
  543. pIcode->ll()->flagDU.d = (Sf | Zf | Cf);
  544. rm(i);
  545. if (pIcode->ll()->getOpcode() == iADD || pIcode->ll()->getOpcode() == iSUB)
  546. pIcode->ll()->clrFlags(NOT_HLL); /* Allow ADD/SUB SP, immed */
  547. }
  548. /****************************************************************************
  549. shift - Sets up dst and opcode from modrm uint8_t
  550. ***************************************************************************/
  551. static void shift(int i)
  552. {
  553. static llIcode shiftTable[8] =
  554. {
  555. (llIcode)iROL, (llIcode)iROR, (llIcode)iRCL, (llIcode)iRCR,
  556. (llIcode)iSHL, (llIcode)iSHR, (llIcode)0, (llIcode)iSAR};
  557. static uint8_t uf[8] = {0, 0, Cf, Cf, 0, 0, 0, 0 };
  558. static uint8_t df[8] = {Cf, Cf, Cf, Cf, Sf | Zf | Cf,
  559. Sf | Zf | Cf, 0, Sf | Zf | Cf};
  560. pIcode->ll()->setOpcode(shiftTable[REG(*pInst)]);
  561. pIcode->ll()->flagDU.u = uf[REG(*pInst)];
  562. pIcode->ll()->flagDU.d = df[REG(*pInst)];
  563. rm(i);
  564. pIcode->ll()->replaceSrc(rCL); //src.regi =
  565. }
  566. /****************************************************************************
  567. trans - Sets up dst and opcode from modrm uint8_t
  568. ***************************************************************************/
  569. static void trans(int i)
  570. {
  571. static llIcode transTable[8] =
  572. {
  573. (llIcode)iINC, (llIcode)iDEC, (llIcode)iCALL, (llIcode)iCALLF,
  574. (llIcode)iJMP, (llIcode)iJMPF,(llIcode)iPUSH, (llIcode)0
  575. };
  576. static uint8_t df[8] = {Sf | Zf, Sf | Zf, 0, 0, 0, 0, 0, 0};
  577. LLInst *ll = pIcode->ll();
  578. if ((uint8_t)REG(*pInst) < 2 || !(stateTable[i].flg & B)) { /* INC & DEC */
  579. ll->setOpcode(transTable[REG(*pInst)]); /* valid on bytes */
  580. ll->flagDU.d = df[REG(*pInst)];
  581. rm(i);
  582. ll->replaceSrc( pIcode->ll()->dst );
  583. if (ll->match(iJMP) || ll->match(iCALL) || ll->match(iCALLF))
  584. ll->setFlags(NO_OPS);
  585. else if (ll->match(iINC) || ll->match(iPUSH) || ll->match(iDEC))
  586. ll->setFlags(NO_SRC);
  587. }
  588. }
  589. /****************************************************************************
  590. arith - Sets up dst and opcode from modrm uint8_t
  591. ****************************************************************************/
  592. static void arith(int i)
  593. {
  594. uint8_t opcode;
  595. static llIcode arithTable[8] =
  596. {
  597. iTEST , (llIcode)0, iNOT, iNEG,
  598. iMUL , iIMUL, iDIV, iIDIV
  599. };
  600. static uint8_t df[8] = {Sf | Zf | Cf, 0, 0, Sf | Zf | Cf,
  601. Sf | Zf | Cf, Sf | Zf | Cf, Sf | Zf | Cf,
  602. Sf | Zf | Cf};
  603. opcode = arithTable[REG(*pInst)];
  604. pIcode->ll()->setOpcode((llIcode)opcode);
  605. pIcode->ll()->flagDU.d = df[REG(*pInst)];
  606. rm(i);
  607. if (opcode == iTEST)
  608. {
  609. if (stateTable[i].flg & B)
  610. data1(i);
  611. else
  612. data2(i);
  613. }
  614. else if (!(opcode == iNOT || opcode == iNEG))
  615. {
  616. pIcode->ll()->replaceSrc( pIcode->ll()->dst );
  617. setAddress(i, true, 0, rAX, 0); /* dst = AX */
  618. }
  619. else if (opcode == iNEG || opcode == iNOT)
  620. pIcode->ll()->setFlags(NO_SRC);
  621. if ((opcode == iDIV) || (opcode == iIDIV))
  622. {
  623. if ( not pIcode->ll()->testFlags(B) )
  624. pIcode->ll()->setFlags(IM_TMP_DST);
  625. }
  626. }
  627. /*****************************************************************************
  628. data1 - Sets up immed from 1 uint8_t data
  629. *****************************************************************************/
  630. static void data1(int i)
  631. {
  632. pIcode->ll()->replaceSrc(LLOperand::CreateImm2((stateTable[i].flg & S_EXT)? signex(*pInst++): *pInst++));
  633. pIcode->ll()->setFlags(I);
  634. }
  635. /*****************************************************************************
  636. data2 - Sets up immed from 2 uint8_t data
  637. ****************************************************************************/
  638. static void data2(int )
  639. {
  640. if (relocItem(pInst))
  641. pIcode->ll()->setFlags(SEG_IMMED);
  642. /* ENTER is a special case, it does not take a destination operand,
  643. * but this field is being used as the number of bytes to allocate
  644. * on the stack. The procedure level is stored in the immediate
  645. * field. There is no source operand; therefore, the flag flg is
  646. * set to NO_OPS. */
  647. if (pIcode->ll()->getOpcode() == iENTER)
  648. {
  649. pIcode->ll()->dst.off = getWord();
  650. pIcode->ll()->setFlags(NO_OPS);
  651. }
  652. else
  653. pIcode->ll()->replaceSrc(getWord());
  654. pIcode->ll()->setFlags(I);
  655. }
  656. /****************************************************************************
  657. dispM - 2 uint8_t offset without modrm (== mod 0, rm 6) (Note:TO_REG bits are
  658. reversed)
  659. ****************************************************************************/
  660. static void dispM(int i)
  661. {
  662. setAddress(i, false, SegPrefix, 0, getWord());
  663. }
  664. /****************************************************************************
  665. dispN - 2 uint8_t disp as immed relative to ip
  666. ****************************************************************************/
  667. static void dispN(int )
  668. {
  669. PROG &prog(Project::get()->prog);
  670. long off = (short)getWord(); /* Signed displacement */
  671. /* Note: the result of the subtraction could be between 32k and 64k, and
  672. still be positive; it is an offset from prog.Image. So this must be
  673. treated as unsigned */
  674. pIcode->ll()->replaceSrc((uint32_t)(off + (unsigned)(pInst - prog.Image)));
  675. pIcode->ll()->setFlags(I);
  676. }
  677. /***************************************************************************
  678. dispS - 1 uint8_t disp as immed relative to ip
  679. ***************************************************************************/
  680. static void dispS(int )
  681. {
  682. PROG &prog(Project::get()->prog);
  683. long off = signex(*pInst++); /* Signed displacement */
  684. pIcode->ll()->replaceSrc((uint32_t)(off + (unsigned)(pInst - prog.Image)));
  685. pIcode->ll()->setFlags(I);
  686. }
  687. /****************************************************************************
  688. dispF - 4 uint8_t disp as immed 20-bit target address
  689. ***************************************************************************/
  690. static void dispF(int )
  691. {
  692. uint32_t off = (unsigned)getWord();
  693. uint32_t seg = (unsigned)getWord();
  694. pIcode->ll()->replaceSrc(off + ((uint32_t)(unsigned)seg << 4));
  695. pIcode->ll()->setFlags(I);
  696. }
  697. /****************************************************************************
  698. prefix - picks up prefix uint8_t for following instruction (LOCK is ignored
  699. on purpose)
  700. ****************************************************************************/
  701. static void prefix(int )
  702. {
  703. if (pIcode->ll()->getOpcode() == iREPE || pIcode->ll()->getOpcode() == iREPNE)
  704. RepPrefix = pIcode->ll()->getOpcode();
  705. else
  706. SegPrefix = pIcode->ll()->getOpcode();
  707. }
  708. inline void BumpOpcode(LLInst &ll)
  709. {
  710. llIcode ic((llIcode)ll.getOpcode());
  711. ic = (llIcode)(((int)ic)+1); // Bump this icode via the int type
  712. ll.setOpcode(ic);
  713. }
  714. /*****************************************************************************
  715. strop - checks RepPrefix and converts string instructions accordingly
  716. *****************************************************************************/
  717. static void strop(int )
  718. {
  719. if (RepPrefix)
  720. {
  721. // pIcode->ll()->getOpcode() += ((pIcode->ll()->getOpcode() == iCMPS ||
  722. // pIcode->ll()->getOpcode() == iSCAS)
  723. // && RepPrefix == iREPE)? 2: 1;
  724. if ((pIcode->ll()->match(iCMPS) || pIcode->ll()->match(iSCAS) ) && RepPrefix == iREPE)
  725. BumpOpcode(*pIcode->ll()); // += 2
  726. BumpOpcode(*pIcode->ll()); // else += 1
  727. if (pIcode->ll()->match(iREP_LODS) )
  728. pIcode->ll()->setFlags(NOT_HLL);
  729. RepPrefix = 0;
  730. }
  731. }
  732. /***************************************************************************
  733. escop - esc operands
  734. ***************************************************************************/
  735. static void escop(int i)
  736. {
  737. pIcode->ll()->replaceSrc(REG(*pInst) + (uint32_t)((i & 7) << 3));
  738. pIcode->ll()->setFlags(I);
  739. rm(i);
  740. }
  741. /****************************************************************************
  742. const1
  743. ****************************************************************************/
  744. static void const1(int )
  745. {
  746. pIcode->ll()->replaceSrc(1);
  747. pIcode->ll()->setFlags(I);
  748. }
  749. /*****************************************************************************
  750. const3
  751. ****************************************************************************/
  752. static void const3(int )
  753. {
  754. pIcode->ll()->replaceSrc(3);
  755. pIcode->ll()->setFlags(I);
  756. }
  757. /****************************************************************************
  758. none1
  759. ****************************************************************************/
  760. static void none1(int )
  761. {
  762. }
  763. /****************************************************************************
  764. none2 - Sets the NO_OPS flag if the operand is immediate
  765. ****************************************************************************/
  766. static void none2(int )
  767. {
  768. if ( pIcode->ll()->testFlags(I) )
  769. pIcode->ll()->setFlags(NO_OPS);
  770. }
  771. /****************************************************************************
  772. Checks for int 34 to int 3B - if so, converts to ESC nn instruction
  773. ****************************************************************************/
  774. static void checkInt(int )
  775. {
  776. uint16_t wOp = (uint16_t) pIcode->ll()->src().getImm2();
  777. if ((wOp >= 0x34) && (wOp <= 0x3B))
  778. {
  779. /* This is a Borland/Microsoft floating point emulation instruction.
  780. Treat as if it is an ESC opcode */
  781. pIcode->ll()->replaceSrc(wOp - 0x34);
  782. pIcode->ll()->set(iESC,FLOAT_OP);
  783. escop(wOp - 0x34 + 0xD8);
  784. }
  785. }