scanner.cpp 39 KB

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  1. /*****************************************************************************
  2. * dcc project scanner module
  3. * Implements a simple state driven scanner to convert 8086 machine code into
  4. * I-code
  5. * (C) Cristina Cifuentes, Jeff Ledermann
  6. ****************************************************************************/
  7. #include <cstring>
  8. #include "dcc.h"
  9. #include "scanner.h"
  10. #include "project.h"
  11. /* Parser flags */
  12. #define TO_REG 0x000100 /* rm is source */
  13. #define S_EXT 0x000200 /* sign extend */
  14. #define OP386 0x000400 /* 386 op-code */
  15. #define NSP 0x000800 /* NOT_HLL if SP is src or dst */
  16. // defined in Enums.h #define ICODEMASK 0xFF00FF /* Masks off parser flags */
  17. static void rm(int i);
  18. static void modrm(int i);
  19. static void segrm(int i);
  20. static void data1(int i);
  21. static void data2(int i);
  22. static void regop(int i);
  23. static void segop(int i);
  24. static void strop(int i);
  25. static void escop(int i);
  26. static void axImp(int i);
  27. static void alImp(int i);
  28. static void axSrcIm(int i);
  29. static void memImp(int i);
  30. static void memReg0(int i);
  31. static void memOnly(int i);
  32. static void dispM(int i);
  33. static void dispS(int i);
  34. static void dispN(int i);
  35. static void dispF(int i);
  36. static void prefix(int i);
  37. static void immed(int i);
  38. static void shift(int i);
  39. static void arith(int i);
  40. static void trans(int i);
  41. static void const1(int i);
  42. static void const3(int i);
  43. static void none1(int i);
  44. static void none2(int i);
  45. static void checkInt(int i);
  46. #define iZERO (llIcode)0 // For neatness
  47. #define IC llIcode
  48. static struct {
  49. void (*state1)(int);
  50. void (*state2)(int);
  51. uint32_t flg;
  52. llIcode opcode;
  53. } stateTable[] = {
  54. { modrm, none2, B , iADD }, /* 00 */
  55. { modrm, none2, 0 , iADD }, /* 01 */
  56. { modrm, none2, TO_REG | B , iADD }, /* 02 */
  57. { modrm, none2, TO_REG , iADD }, /* 03 */
  58. { data1, axImp, B , iADD }, /* 04 */
  59. { data2, axImp, 0 , iADD }, /* 05 */
  60. { segop, none2, NO_SRC , iPUSH }, /* 06 */
  61. { segop, none2, NO_SRC , iPOP }, /* 07 */
  62. { modrm, none2, B , iOR }, /* 08 */
  63. { modrm, none2, NSP , iOR }, /* 09 */
  64. { modrm, none2, TO_REG | B , iOR }, /* 0A */
  65. { modrm, none2, TO_REG | NSP , iOR }, /* 0B */
  66. { data1, axImp, B , iOR }, /* 0C */
  67. { data2, axImp, 0 , iOR }, /* 0D */
  68. { segop, none2, NO_SRC , iPUSH }, /* 0E */
  69. { none1, none2, OP386 , iZERO }, /* 0F */
  70. { modrm, none2, B , iADC }, /* 10 */
  71. { modrm, none2, NSP , iADC }, /* 11 */
  72. { modrm, none2, TO_REG | B , iADC }, /* 12 */
  73. { modrm, none2, TO_REG | NSP , iADC }, /* 13 */
  74. { data1, axImp, B , iADC }, /* 14 */
  75. { data2, axImp, 0 , iADC }, /* 15 */
  76. { segop, none2, NOT_HLL | NO_SRC , iPUSH }, /* 16 */
  77. { segop, none2, NOT_HLL | NO_SRC , iPOP }, /* 17 */
  78. { modrm, none2, B , iSBB }, /* 18 */
  79. { modrm, none2, NSP , iSBB }, /* 19 */
  80. { modrm, none2, TO_REG | B , iSBB }, /* 1A */
  81. { modrm, none2, TO_REG | NSP , iSBB }, /* 1B */
  82. { data1, axImp, B , iSBB }, /* 1C */
  83. { data2, axImp, 0 , iSBB }, /* 1D */
  84. { segop, none2, NO_SRC , iPUSH }, /* 1E */
  85. { segop, none2, NO_SRC , iPOP }, /* 1F */
  86. { modrm, none2, B , iAND }, /* 20 */
  87. { modrm, none2, NSP , iAND }, /* 21 */
  88. { modrm, none2, TO_REG | B , iAND }, /* 22 */
  89. { modrm, none2, TO_REG | NSP , iAND }, /* 23 */
  90. { data1, axImp, B , iAND }, /* 24 */
  91. { data2, axImp, 0 , iAND }, /* 25 */
  92. { prefix, none2, 0 , (IC)rES}, /* 26 */
  93. { none1, axImp, NOT_HLL | B|NO_SRC , iDAA }, /* 27 */
  94. { modrm, none2, B , iSUB }, /* 28 */
  95. { modrm, none2, 0 , iSUB }, /* 29 */
  96. { modrm, none2, TO_REG | B , iSUB }, /* 2A */
  97. { modrm, none2, TO_REG , iSUB }, /* 2B */
  98. { data1, axImp, B , iSUB }, /* 2C */
  99. { data2, axImp, 0 , iSUB }, /* 2D */
  100. { prefix, none2, 0 , (IC)rCS}, /* 2E */
  101. { none1, axImp, NOT_HLL | B|NO_SRC , iDAS }, /* 2F */
  102. { modrm, none2, B , iXOR }, /* 30 */
  103. { modrm, none2, NSP , iXOR }, /* 31 */
  104. { modrm, none2, TO_REG | B , iXOR }, /* 32 */
  105. { modrm, none2, TO_REG | NSP , iXOR }, /* 33 */
  106. { data1, axImp, B , iXOR }, /* 34 */
  107. { data2, axImp, 0 , iXOR }, /* 35 */
  108. { prefix, none2, 0 , (IC)rSS}, /* 36 */
  109. { none1, axImp, NOT_HLL | NO_SRC , iAAA }, /* 37 */
  110. { modrm, none2, B , iCMP }, /* 38 */
  111. { modrm, none2, NSP , iCMP }, /* 39 */
  112. { modrm, none2, TO_REG | B , iCMP }, /* 3A */
  113. { modrm, none2, TO_REG | NSP , iCMP }, /* 3B */
  114. { data1, axImp, B , iCMP }, /* 3C */
  115. { data2, axImp, 0 , iCMP }, /* 3D */
  116. { prefix, none2, 0 , (IC)rDS}, /* 3E */
  117. { none1, axImp, NOT_HLL | NO_SRC , iAAS }, /* 3F */
  118. { regop, none2, 0 , iINC }, /* 40 */
  119. { regop, none2, 0 , iINC }, /* 41 */
  120. { regop, none2, 0 , iINC }, /* 42 */
  121. { regop, none2, 0 , iINC }, /* 43 */
  122. { regop, none2, NOT_HLL , iINC }, /* 44 */
  123. { regop, none2, 0 , iINC }, /* 45 */
  124. { regop, none2, 0 , iINC }, /* 46 */
  125. { regop, none2, 0 , iINC }, /* 47 */
  126. { regop, none2, 0 , iDEC }, /* 48 */
  127. { regop, none2, 0 , iDEC }, /* 49 */
  128. { regop, none2, 0 , iDEC }, /* 4A */
  129. { regop, none2, 0 , iDEC }, /* 4B */
  130. { regop, none2, NOT_HLL , iDEC }, /* 4C */
  131. { regop, none2, 0 , iDEC }, /* 4D */
  132. { regop, none2, 0 , iDEC }, /* 4E */
  133. { regop, none2, 0 , iDEC }, /* 4F */
  134. { regop, none2, NO_SRC , iPUSH }, /* 50 */
  135. { regop, none2, NO_SRC , iPUSH }, /* 51 */
  136. { regop, none2, NO_SRC , iPUSH }, /* 52 */
  137. { regop, none2, NO_SRC , iPUSH }, /* 53 */
  138. { regop, none2, NOT_HLL | NO_SRC , iPUSH }, /* 54 */
  139. { regop, none2, NO_SRC , iPUSH }, /* 55 */
  140. { regop, none2, NO_SRC , iPUSH }, /* 56 */
  141. { regop, none2, NO_SRC , iPUSH }, /* 57 */
  142. { regop, none2, NO_SRC , iPOP }, /* 58 */
  143. { regop, none2, NO_SRC , iPOP }, /* 59 */
  144. { regop, none2, NO_SRC , iPOP }, /* 5A */
  145. { regop, none2, NO_SRC , iPOP }, /* 5B */
  146. { regop, none2, NOT_HLL | NO_SRC , iPOP }, /* 5C */
  147. { regop, none2, NO_SRC , iPOP }, /* 5D */
  148. { regop, none2, NO_SRC , iPOP }, /* 5E */
  149. { regop, none2, NO_SRC , iPOP }, /* 5F */
  150. { none1, none2, NOT_HLL | NO_OPS , iPUSHA}, /* 60 */
  151. { none1, none2, NOT_HLL | NO_OPS , iPOPA }, /* 61 */
  152. { memOnly, modrm, TO_REG | NSP , iBOUND}, /* 62 */
  153. { none1, none2, OP386 , iZERO }, /* 63 */
  154. { none1, none2, OP386 , iZERO }, /* 64 */
  155. { none1, none2, OP386 , iZERO }, /* 65 */
  156. { none1, none2, OP386 , iZERO }, /* 66 */
  157. { none1, none2, OP386 , iZERO }, /* 67 */
  158. { data2, none2, NO_SRC , iPUSH }, /* 68 */
  159. { modrm, data2, TO_REG | NSP , iIMUL }, /* 69 */
  160. { data1, none2, S_EXT | NO_SRC , iPUSH }, /* 6A */
  161. { modrm, data1, TO_REG | NSP | S_EXT , iIMUL }, /* 6B */
  162. { strop, memImp, NOT_HLL | B|IM_OPS , iINS }, /* 6C */
  163. { strop, memImp, NOT_HLL | IM_OPS , iINS }, /* 6D */
  164. { strop, memImp, NOT_HLL | B|IM_OPS , iOUTS }, /* 6E */
  165. { strop, memImp, NOT_HLL | IM_OPS , iOUTS }, /* 6F */
  166. { dispS, none2, NOT_HLL , iJO }, /* 70 */
  167. { dispS, none2, NOT_HLL , iJNO }, /* 71 */
  168. { dispS, none2, 0 , iJB }, /* 72 */
  169. { dispS, none2, 0 , iJAE }, /* 73 */
  170. { dispS, none2, 0 , iJE }, /* 74 */
  171. { dispS, none2, 0 , iJNE }, /* 75 */
  172. { dispS, none2, 0 , iJBE }, /* 76 */
  173. { dispS, none2, 0 , iJA }, /* 77 */
  174. { dispS, none2, 0 , iJS }, /* 78 */
  175. { dispS, none2, 0 , iJNS }, /* 79 */
  176. { dispS, none2, NOT_HLL , iJP }, /* 7A */
  177. { dispS, none2, NOT_HLL , iJNP }, /* 7B */
  178. { dispS, none2, 0 , iJL }, /* 7C */
  179. { dispS, none2, 0 , iJGE }, /* 7D */
  180. { dispS, none2, 0 , iJLE }, /* 7E */
  181. { dispS, none2, 0 , iJG }, /* 7F */
  182. { immed, data1, B , iZERO }, /* 80 */
  183. { immed, data2, NSP , iZERO }, /* 81 */
  184. { immed, data1, B , iZERO }, /* 82 */ /* ?? */
  185. { immed, data1, NSP | S_EXT , iZERO }, /* 83 */
  186. { modrm, none2, TO_REG | B , iTEST }, /* 84 */
  187. { modrm, none2, TO_REG | NSP , iTEST }, /* 85 */
  188. { modrm, none2, TO_REG | B , iXCHG }, /* 86 */
  189. { modrm, none2, TO_REG | NSP , iXCHG }, /* 87 */
  190. { modrm, none2, B , iMOV }, /* 88 */
  191. { modrm, none2, 0 , iMOV }, /* 89 */
  192. { modrm, none2, TO_REG | B , iMOV }, /* 8A */
  193. { modrm, none2, TO_REG , iMOV }, /* 8B */
  194. { segrm, none2, NSP , iMOV }, /* 8C */
  195. { memOnly, modrm, TO_REG | NSP , iLEA }, /* 8D */
  196. { segrm, none2, TO_REG | NSP , iMOV }, /* 8E */
  197. { memReg0, none2, NO_SRC , iPOP }, /* 8F */
  198. { none1, none2, NO_OPS , iNOP }, /* 90 */
  199. { regop, axImp, 0 , iXCHG }, /* 91 */
  200. { regop, axImp, 0 , iXCHG }, /* 92 */
  201. { regop, axImp, 0 , iXCHG }, /* 93 */
  202. { regop, axImp, NOT_HLL , iXCHG }, /* 94 */
  203. { regop, axImp, 0 , iXCHG }, /* 95 */
  204. { regop, axImp, 0 , iXCHG }, /* 96 */
  205. { regop, axImp, 0 , iXCHG }, /* 97 */
  206. { alImp, axImp, SRC_B | S_EXT , iSIGNEX}, /* 98 */
  207. {axSrcIm, axImp, IM_DST | S_EXT , iSIGNEX}, /* 99 */
  208. { dispF, none2, 0 , iCALLF }, /* 9A */
  209. { none1, none2, FLOAT_OP| NO_OPS , iWAIT }, /* 9B */
  210. { none1, none2, NOT_HLL | NO_OPS , iPUSHF}, /* 9C */
  211. { none1, none2, NOT_HLL | NO_OPS , iPOPF }, /* 9D */
  212. { none1, none2, NOT_HLL | NO_OPS , iSAHF }, /* 9E */
  213. { none1, none2, NOT_HLL | NO_OPS , iLAHF }, /* 9F */
  214. { dispM, axImp, B , iMOV }, /* A0 */
  215. { dispM, axImp, 0 , iMOV }, /* A1 */
  216. { dispM, axImp, TO_REG | B , iMOV }, /* A2 */
  217. { dispM, axImp, TO_REG , iMOV }, /* A3 */
  218. { strop, memImp, B | IM_OPS , iMOVS }, /* A4 */
  219. { strop, memImp, IM_OPS , iMOVS }, /* A5 */
  220. { strop, memImp, B | IM_OPS , iCMPS }, /* A6 */
  221. { strop, memImp, IM_OPS , iCMPS }, /* A7 */
  222. { data1, axImp, B , iTEST }, /* A8 */
  223. { data2, axImp, 0 , iTEST }, /* A9 */
  224. { strop, memImp, B | IM_OPS , iSTOS }, /* AA */
  225. { strop, memImp, IM_OPS , iSTOS }, /* AB */
  226. { strop, memImp, B | IM_OPS , iLODS }, /* AC */
  227. { strop, memImp, IM_OPS , iLODS }, /* AD */
  228. { strop, memImp, B | IM_OPS , iSCAS }, /* AE */
  229. { strop, memImp, IM_OPS , iSCAS }, /* AF */
  230. { regop, data1, B , iMOV }, /* B0 */
  231. { regop, data1, B , iMOV }, /* B1 */
  232. { regop, data1, B , iMOV }, /* B2 */
  233. { regop, data1, B , iMOV }, /* B3 */
  234. { regop, data1, B , iMOV }, /* B4 */
  235. { regop, data1, B , iMOV }, /* B5 */
  236. { regop, data1, B , iMOV }, /* B6 */
  237. { regop, data1, B , iMOV }, /* B7 */
  238. { regop, data2, 0 , iMOV }, /* B8 */
  239. { regop, data2, 0 , iMOV }, /* B9 */
  240. { regop, data2, 0 , iMOV }, /* BA */
  241. { regop, data2, 0 , iMOV }, /* BB */
  242. { regop, data2, NOT_HLL , iMOV }, /* BC */
  243. { regop, data2, 0 , iMOV }, /* BD */
  244. { regop, data2, 0 , iMOV }, /* BE */
  245. { regop, data2, 0 , iMOV }, /* BF */
  246. { shift, data1, B , iZERO }, /* C0 */
  247. { shift, data1, NSP | SRC_B , iZERO }, /* C1 */
  248. { data2, none2, 0 , iRET }, /* C2 */
  249. { none1, none2, NO_OPS , iRET }, /* C3 */
  250. { memOnly, modrm, TO_REG | NSP , iLES }, /* C4 */
  251. { memOnly, modrm, TO_REG | NSP , iLDS }, /* C5 */
  252. { memReg0, data1, B , iMOV }, /* C6 */
  253. { memReg0, data2, 0 , iMOV }, /* C7 */
  254. { data2, data1, 0 , iENTER}, /* C8 */
  255. { none1, none2, NO_OPS , iLEAVE}, /* C9 */
  256. { data2, none2, 0 , iRETF }, /* CA */
  257. { none1, none2, NO_OPS , iRETF }, /* CB */
  258. { const3, none2, NOT_HLL , iINT }, /* CC */
  259. { data1,checkInt, NOT_HLL , iINT }, /* CD */
  260. { none1, none2, NOT_HLL | NO_OPS , iINTO }, /* CE */
  261. { none1, none2, NOT_HLL | NO_OPS , iIRET }, /* Cf */
  262. { shift, const1, B , iZERO }, /* D0 */
  263. { shift, const1, SRC_B , iZERO }, /* D1 */
  264. { shift, none1, B , iZERO }, /* D2 */
  265. { shift, none1, SRC_B , iZERO }, /* D3 */
  266. { data1, axImp, NOT_HLL , iAAM }, /* D4 */
  267. { data1, axImp, NOT_HLL , iAAD }, /* D5 */
  268. { none1, none2, 0 , iZERO }, /* D6 */
  269. { memImp, axImp, NOT_HLL | B| IM_OPS , iXLAT }, /* D7 */
  270. { escop, none2, FLOAT_OP , iESC }, /* D8 */
  271. { escop, none2, FLOAT_OP , iESC }, /* D9 */
  272. { escop, none2, FLOAT_OP , iESC }, /* DA */
  273. { escop, none2, FLOAT_OP , iESC }, /* DB */
  274. { escop, none2, FLOAT_OP , iESC }, /* DC */
  275. { escop, none2, FLOAT_OP , iESC }, /* DD */
  276. { escop, none2, FLOAT_OP , iESC }, /* DE */
  277. { escop, none2, FLOAT_OP , iESC }, /* Df */
  278. { dispS, none2, 0 , iLOOPNE}, /* E0 */
  279. { dispS, none2, 0 , iLOOPE}, /* E1 */
  280. { dispS, none2, 0 , iLOOP }, /* E2 */
  281. { dispS, none2, 0 , iJCXZ }, /* E3 */
  282. { data1, axImp, NOT_HLL | B|NO_SRC , iIN }, /* E4 */
  283. { data1, axImp, NOT_HLL | NO_SRC , iIN }, /* E5 */
  284. { data1, axImp, NOT_HLL | B|NO_SRC , iOUT }, /* E6 */
  285. { data1, axImp, NOT_HLL | NO_SRC , iOUT }, /* E7 */
  286. { dispN, none2, 0 , iCALL }, /* E8 */
  287. { dispN, none2, 0 , iJMP }, /* E9 */
  288. { dispF, none2, 0 , iJMPF }, /* EA */
  289. { dispS, none2, 0 , iJMP }, /* EB */
  290. { none1, axImp, NOT_HLL | B|NO_SRC , iIN }, /* EC */
  291. { none1, axImp, NOT_HLL | NO_SRC , iIN }, /* ED */
  292. { none1, axImp, NOT_HLL | B|NO_SRC , iOUT }, /* EE */
  293. { none1, axImp, NOT_HLL | NO_SRC , iOUT }, /* EF */
  294. { none1, none2, NOT_HLL | NO_OPS , iLOCK }, /* F0 */
  295. { none1, none2, 0 , iZERO }, /* F1 */
  296. { prefix, none2, 0 , iREPNE}, /* F2 */
  297. { prefix, none2, 0 , iREPE }, /* F3 */
  298. { none1, none2, NOT_HLL | NO_OPS , iHLT }, /* F4 */
  299. { none1, none2, NO_OPS , iCMC }, /* F5 */
  300. { arith, none1, B , iZERO }, /* F6 */
  301. { arith, none1, NSP , iZERO }, /* F7 */
  302. { none1, none2, NO_OPS , iCLC }, /* F8 */
  303. { none1, none2, NO_OPS , iSTC }, /* F9 */
  304. { none1, none2, NOT_HLL | NO_OPS , iCLI }, /* FA */
  305. { none1, none2, NOT_HLL | NO_OPS , iSTI }, /* FB */
  306. { none1, none2, NO_OPS , iCLD }, /* FC */
  307. { none1, none2, NO_OPS , iSTD }, /* FD */
  308. { trans, none1, B , iZERO }, /* FE */
  309. { trans, none1, NSP , iZERO } /* FF */
  310. } ;
  311. static uint16_t SegPrefix, RepPrefix;
  312. static uint8_t *pInst; /* Ptr. to current uint8_t of instruction */
  313. static ICODE * pIcode; /* Ptr to Icode record filled in by scan() */
  314. /*****************************************************************************
  315. Scans one machine instruction at offset ip in prog.Image and returns error.
  316. At the same time, fill in low-level icode details for the scanned inst.
  317. ****************************************************************************/
  318. static void convertUsedFlags(x86_insn_t &from,ICODE &to)
  319. {
  320. to.ll()->flagDU.d=0;
  321. to.ll()->flagDU.u=0;
  322. if(from.containsFlag(insn_eflag_carry,from.flags_set))
  323. to.ll()->flagDU.d |= Cf;
  324. if(from.containsFlag(insn_eflag_sign,from.flags_set))
  325. to.ll()->flagDU.d |= Sf;
  326. if(from.containsFlag(insn_eflag_zero,from.flags_set))
  327. to.ll()->flagDU.d |= Zf;
  328. if(from.containsFlag(insn_eflag_direction,from.flags_set))
  329. to.ll()->flagDU.d |= Df;
  330. if(from.containsFlag(insn_eflag_carry,from.flags_tested))
  331. to.ll()->flagDU.u |= Cf;
  332. if(from.containsFlag(insn_eflag_sign,from.flags_tested))
  333. to.ll()->flagDU.u |= Sf;
  334. if(from.containsFlag(insn_eflag_zero,from.flags_tested))
  335. to.ll()->flagDU.u |= Zf;
  336. if(from.containsFlag(insn_eflag_direction,from.flags_tested))
  337. to.ll()->flagDU.u |= Df;
  338. }
  339. /****************************************************************************
  340. Checks for int 34 to int 3B - if so, converts to ESC nn instruction
  341. ****************************************************************************/
  342. static void fixFloatEmulation(x86_insn_t &insn)
  343. {
  344. if(insn.group!=x86_insn_t::insn_interrupt)
  345. return;
  346. PROG &prog(Project::get()->prog);
  347. uint16_t wOp=insn.x86_get_imm()->data.word;
  348. if ((wOp < 0x34) || (wOp > 0x3B))
  349. return;
  350. uint8_t buf[16];
  351. /* This is a Borland/Microsoft floating point emulation instruction. Treat as if it is an ESC opcode */
  352. int actual_valid_bytes=std::min(16U,prog.cbImage-insn.offset);
  353. memcpy(buf,prog.Image+insn.offset,actual_valid_bytes);
  354. X86_Disasm ds(opt_16_bit);
  355. x86_insn_t patched_insn;
  356. //patch actual instruction into buffer;
  357. buf[1] = wOp-0x34+0xD8;
  358. ds.x86_disasm(buf,actual_valid_bytes,0,1,&patched_insn);
  359. patched_insn.addr = insn.addr; // actual address
  360. patched_insn.offset = insn.offset; // actual offset
  361. insn = patched_insn;
  362. insn.size += 1; // to account for emulator call INT
  363. }
  364. int disassembleOneLibDisasm(uint32_t ip,x86_insn_t &l)
  365. {
  366. PROG &prog(Project::get()->prog);
  367. X86_Disasm ds(opt_16_bit);
  368. int cnt=ds.x86_disasm(prog.Image,prog.cbImage,0,ip,&l);
  369. if(cnt && l.is_valid())
  370. {
  371. fixFloatEmulation(l); //can change 'l'
  372. }
  373. if(l.is_valid())
  374. return l.size;
  375. return 0;
  376. }
  377. eReg convertRegister(const x86_reg_t &reg)
  378. {
  379. eReg regmap[]={ rUNDEF,
  380. rUNDEF,rUNDEF,rUNDEF,rUNDEF, //eax ecx ebx edx
  381. rUNDEF,rUNDEF,rUNDEF,rUNDEF, //esp ebp esi edi
  382. rAX,rCX,rDX,rBX,
  383. rSP,rBP,rSI,rDI,
  384. rAL,rCL,rDL,rBL,
  385. rAH,rCH,rDH,rBH
  386. };
  387. assert(reg.id<sizeof(regmap)/sizeof(eReg));
  388. return regmap[reg.id];
  389. }
  390. LLOperand convertOperand(const x86_op_t &from)
  391. {
  392. switch(from.type)
  393. {
  394. case op_unused:
  395. break;
  396. case op_register:
  397. return LLOperand::CreateReg2(convertRegister(from.data.reg));
  398. case op_immediate:
  399. return LLOperand::CreateImm2(from.data.sdword);
  400. default:
  401. fprintf(stderr,"convertOperand does not know how to convert %d\n",from.type);
  402. }
  403. return LLOperand::CreateImm2(0);
  404. }
  405. eErrorId scan(uint32_t ip, ICODE &p)
  406. {
  407. PROG &prog(Project::get()->prog);
  408. int op;
  409. p = ICODE();
  410. p.type = LOW_LEVEL;
  411. p.ll()->label = ip; /* ip is absolute offset into image*/
  412. if (ip >= (uint32_t)prog.cbImage)
  413. {
  414. return (IP_OUT_OF_RANGE);
  415. }
  416. int cnt=disassembleOneLibDisasm(ip,p.insn);
  417. if(cnt)
  418. {
  419. convertUsedFlags(p.insn,p);
  420. }
  421. SegPrefix = RepPrefix = 0;
  422. pInst = prog.Image + ip;
  423. pIcode = &p;
  424. do
  425. {
  426. op = *pInst++; /* First state - trivial */
  427. /* Convert to Icode.opcode */
  428. p.ll()->set(stateTable[op].opcode,stateTable[op].flg & ICODEMASK);
  429. (*stateTable[op].state1)(op); /* Second state */
  430. (*stateTable[op].state2)(op); /* Third state */
  431. } while (stateTable[op].state1 == prefix); /* Loop if prefix */
  432. if (p.ll()->getOpcode())
  433. {
  434. /* Save bytes of image used */
  435. p.ll()->numBytes = (uint8_t)((pInst - prog.Image) - ip);
  436. if(p.insn.is_valid())
  437. assert(p.ll()->numBytes == p.insn.size);
  438. return ((SegPrefix)? FUNNY_SEGOVR: /* Seg. Override invalid */
  439. (RepPrefix ? FUNNY_REP: NO_ERR));/* REP prefix invalid */
  440. }
  441. /* Else opcode error */
  442. return ((stateTable[op].flg & OP386)? INVALID_386OP: INVALID_OPCODE);
  443. }
  444. /***************************************************************************
  445. relocItem - returns true if uint16_t pointed at is in relocation table
  446. **************************************************************************/
  447. static bool relocItem(uint8_t *p)
  448. {
  449. PROG &prog(Project::get()->prog);
  450. int i;
  451. uint32_t off = p - prog.Image;
  452. for (i = 0; i < prog.cReloc; i++)
  453. if (prog.relocTable[i] == off)
  454. return true;
  455. return false;
  456. }
  457. /***************************************************************************
  458. getWord - returns next uint16_t from image
  459. **************************************************************************/
  460. static uint16_t getWord(void)
  461. {
  462. uint16_t w = LH(pInst);
  463. pInst += 2;
  464. return w;
  465. }
  466. /****************************************************************************
  467. signex - returns uint8_t sign extended to int
  468. ***************************************************************************/
  469. static int signex(uint8_t b)
  470. {
  471. long s = b;
  472. return ((b & 0x80)? (int)(0xFFFFFF00 | s): (int)s);
  473. }
  474. /****************************************************************************
  475. * setAddress - Updates the source or destination field for the current
  476. * icode, based on fdst and the TO_REG flag.
  477. * Note: fdst == true is for the r/m part of the field (dest, unless TO_REG)
  478. * fdst == false is for reg part of the field
  479. ***************************************************************************/
  480. static void setAddress(int i, boolT fdst, uint16_t seg, int16_t reg, uint16_t off)
  481. {
  482. LLOperand *pm;
  483. /* If not to register (i.e. to r/m), and talking about r/m, then this is dest */
  484. pm = (!(stateTable[i].flg & TO_REG) == fdst) ?
  485. &pIcode->ll()->dst : &pIcode->ll()->src();
  486. /* Set segment. A later procedure (lookupAddr in proclist.c) will
  487. * provide the value of this segment in the field segValue. */
  488. if (seg) /* segment override */
  489. {
  490. pm->seg = pm->segOver = (eReg)seg;
  491. }
  492. else
  493. { /* no override, check indexed register */
  494. if ((reg >= INDEX_BX_SI) && (reg == INDEX_BP_SI || reg == INDEX_BP_DI || reg == INDEX_BP))
  495. {
  496. pm->seg = rSS; /* indexed on bp */
  497. }
  498. else
  499. {
  500. pm->seg = rDS; /* any other indexed reg */
  501. }
  502. }
  503. pm->regi = (eReg)reg;
  504. pm->off = (int16_t)off;
  505. if (reg && reg < INDEX_BX_SI && (stateTable[i].flg & B))
  506. {
  507. pm->regi = Machine_X86::subRegL(pm->regi);
  508. }
  509. if (seg) /* So we can catch invalid use of segment overrides */
  510. {
  511. SegPrefix = 0;
  512. }
  513. }
  514. /****************************************************************************
  515. rm - Decodes r/m part of modrm uint8_t for dst (unless TO_REG) part of icode
  516. ***************************************************************************/
  517. static void rm(int i)
  518. {
  519. uint8_t mod = *pInst >> 6;
  520. uint8_t rm = *pInst++ & 7;
  521. switch (mod) {
  522. case 0: /* No disp unless rm == 6 */
  523. if (rm == 6) {
  524. setAddress(i, true, SegPrefix, 0, getWord());
  525. pIcode->ll()->setFlags(WORD_OFF);
  526. }
  527. else
  528. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, 0);
  529. break;
  530. case 1: /* 1 uint8_t disp */
  531. setAddress(i, true, SegPrefix, rm+INDEX_BX_SI, (uint16_t)signex(*pInst++));
  532. break;
  533. case 2: /* 2 uint8_t disp */
  534. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, getWord());
  535. pIcode->ll()->setFlags(WORD_OFF);
  536. break;
  537. case 3: /* reg */
  538. setAddress(i, true, 0, rm + rAX, 0);
  539. break;
  540. }
  541. if ((stateTable[i].flg & NSP) && (pIcode->ll()->src().getReg2()==rSP ||
  542. pIcode->ll()->dst.getReg2()==rSP))
  543. pIcode->ll()->setFlags(NOT_HLL);
  544. }
  545. /****************************************************************************
  546. modrm - Sets up src and dst from modrm uint8_t
  547. ***************************************************************************/
  548. static void modrm(int i)
  549. {
  550. setAddress(i, false, 0, REG(*pInst) + rAX, 0);
  551. rm(i);
  552. }
  553. /****************************************************************************
  554. segrm - seg encoded as reg of modrm
  555. ****************************************************************************/
  556. static void segrm(int i)
  557. {
  558. int reg = REG(*pInst) + rES;
  559. if (reg > rDS || (reg == rCS && (stateTable[i].flg & TO_REG)))
  560. pIcode->ll()->setOpcode((llIcode)0); // setCBW because it has that index
  561. else {
  562. setAddress(i, false, 0, (int16_t)reg, 0);
  563. rm(i);
  564. }
  565. }
  566. /****************************************************************************
  567. regop - src/dst reg encoded as low 3 bits of opcode
  568. ***************************************************************************/
  569. static void regop(int i)
  570. {
  571. setAddress(i, false, 0, ((int16_t)i & 7) + rAX, 0);
  572. pIcode->ll()->replaceDst(LLOperand::CreateReg2(pIcode->ll()->src().getReg2()));
  573. // pIcode->ll()->dst.regi = pIcode->ll()->src.regi;
  574. }
  575. /*****************************************************************************
  576. segop - seg encoded in middle of opcode
  577. *****************************************************************************/
  578. static void segop(int i)
  579. {
  580. setAddress(i, true, 0, (((int16_t)i & 0x18) >> 3) + rES, 0);
  581. }
  582. /****************************************************************************
  583. axImp - Plugs an implied AX dst
  584. ***************************************************************************/
  585. static void axImp(int i)
  586. {
  587. setAddress(i, true, 0, rAX, 0);
  588. }
  589. /* Implied AX source */
  590. static void axSrcIm (int )
  591. {
  592. pIcode->ll()->replaceSrc(rAX);//src.regi = rAX;
  593. }
  594. /* Implied AL source */
  595. static void alImp (int )
  596. {
  597. pIcode->ll()->replaceSrc(rAL);//src.regi = rAL;
  598. }
  599. /*****************************************************************************
  600. memImp - Plugs implied src memory operand with any segment override
  601. ****************************************************************************/
  602. static void memImp(int i)
  603. {
  604. setAddress(i, false, SegPrefix, 0, 0);
  605. }
  606. /****************************************************************************
  607. memOnly - Instruction is not valid if modrm refers to register (i.e. mod == 3)
  608. ***************************************************************************/
  609. static void memOnly(int )
  610. {
  611. if ((*pInst & 0xC0) == 0xC0)
  612. pIcode->ll()->setOpcode((llIcode)0);
  613. }
  614. /****************************************************************************
  615. memReg0 - modrm for 'memOnly' and Reg field must also be 0
  616. ****************************************************************************/
  617. static void memReg0(int i)
  618. {
  619. if (REG(*pInst) || (*pInst & 0xC0) == 0xC0)
  620. pIcode->ll()->setOpcode((llIcode)0);
  621. else
  622. rm(i);
  623. }
  624. /***************************************************************************
  625. immed - Sets up dst and opcode from modrm uint8_t
  626. **************************************************************************/
  627. static void immed(int i)
  628. {
  629. static llIcode immedTable[8] = {iADD, iOR, iADC, iSBB, iAND, iSUB, iXOR, iCMP};
  630. pIcode->ll()->setOpcode(immedTable[REG(*pInst)]) ;
  631. rm(i);
  632. if (pIcode->ll()->getOpcode() == iADD || pIcode->ll()->getOpcode() == iSUB)
  633. pIcode->ll()->clrFlags(NOT_HLL); /* Allow ADD/SUB SP, immed */
  634. }
  635. /****************************************************************************
  636. shift - Sets up dst and opcode from modrm uint8_t
  637. ***************************************************************************/
  638. static void shift(int i)
  639. {
  640. static llIcode shiftTable[8] =
  641. {
  642. (llIcode)iROL, (llIcode)iROR, (llIcode)iRCL, (llIcode)iRCR,
  643. (llIcode)iSHL, (llIcode)iSHR, (llIcode)0, (llIcode)iSAR};
  644. pIcode->ll()->setOpcode(shiftTable[REG(*pInst)]);
  645. rm(i);
  646. pIcode->ll()->replaceSrc(rCL); //src.regi =
  647. }
  648. /****************************************************************************
  649. trans - Sets up dst and opcode from modrm uint8_t
  650. ***************************************************************************/
  651. static void trans(int i)
  652. {
  653. static llIcode transTable[8] =
  654. {
  655. (llIcode)iINC, (llIcode)iDEC, (llIcode)iCALL, (llIcode)iCALLF,
  656. (llIcode)iJMP, (llIcode)iJMPF,(llIcode)iPUSH, (llIcode)0
  657. };
  658. LLInst *ll = pIcode->ll();
  659. if ((uint8_t)REG(*pInst) < 2 || !(stateTable[i].flg & B)) { /* INC & DEC */
  660. ll->setOpcode(transTable[REG(*pInst)]); /* valid on bytes */
  661. rm(i);
  662. ll->replaceSrc( pIcode->ll()->dst );
  663. if (ll->match(iJMP) || ll->match(iCALL) || ll->match(iCALLF))
  664. ll->setFlags(NO_OPS);
  665. else if (ll->match(iINC) || ll->match(iPUSH) || ll->match(iDEC))
  666. ll->setFlags(NO_SRC);
  667. }
  668. }
  669. /****************************************************************************
  670. arith - Sets up dst and opcode from modrm uint8_t
  671. ****************************************************************************/
  672. static void arith(int i)
  673. {
  674. uint8_t opcode;
  675. static llIcode arithTable[8] =
  676. {
  677. iTEST , (llIcode)0, iNOT, iNEG,
  678. iMUL , iIMUL, iDIV, iIDIV
  679. };
  680. opcode = arithTable[REG(*pInst)];
  681. pIcode->ll()->setOpcode((llIcode)opcode);
  682. rm(i);
  683. if (opcode == iTEST)
  684. {
  685. if (stateTable[i].flg & B)
  686. data1(i);
  687. else
  688. data2(i);
  689. }
  690. else if (!(opcode == iNOT || opcode == iNEG))
  691. {
  692. pIcode->ll()->replaceSrc( pIcode->ll()->dst );
  693. setAddress(i, true, 0, rAX, 0); /* dst = AX */
  694. }
  695. else if (opcode == iNEG || opcode == iNOT)
  696. pIcode->ll()->setFlags(NO_SRC);
  697. if ((opcode == iDIV) || (opcode == iIDIV))
  698. {
  699. if ( not pIcode->ll()->testFlags(B) )
  700. pIcode->ll()->setFlags(IM_TMP_DST);
  701. }
  702. }
  703. /*****************************************************************************
  704. data1 - Sets up immed from 1 uint8_t data
  705. *****************************************************************************/
  706. static void data1(int i)
  707. {
  708. pIcode->ll()->replaceSrc(LLOperand::CreateImm2((stateTable[i].flg & S_EXT)? signex(*pInst++): *pInst++));
  709. pIcode->ll()->setFlags(I);
  710. }
  711. /*****************************************************************************
  712. data2 - Sets up immed from 2 uint8_t data
  713. ****************************************************************************/
  714. static void data2(int )
  715. {
  716. if (relocItem(pInst))
  717. pIcode->ll()->setFlags(SEG_IMMED);
  718. /* ENTER is a special case, it does not take a destination operand,
  719. * but this field is being used as the number of bytes to allocate
  720. * on the stack. The procedure level is stored in the immediate
  721. * field. There is no source operand; therefore, the flag flg is
  722. * set to NO_OPS. */
  723. if (pIcode->ll()->getOpcode() == iENTER)
  724. {
  725. pIcode->ll()->dst.off = getWord();
  726. pIcode->ll()->setFlags(NO_OPS);
  727. }
  728. else
  729. pIcode->ll()->replaceSrc(getWord());
  730. pIcode->ll()->setFlags(I);
  731. }
  732. /****************************************************************************
  733. dispM - 2 uint8_t offset without modrm (== mod 0, rm 6) (Note:TO_REG bits are
  734. reversed)
  735. ****************************************************************************/
  736. static void dispM(int i)
  737. {
  738. setAddress(i, false, SegPrefix, 0, getWord());
  739. }
  740. /****************************************************************************
  741. dispN - 2 uint8_t disp as immed relative to ip
  742. ****************************************************************************/
  743. static void dispN(int )
  744. {
  745. PROG &prog(Project::get()->prog);
  746. long off = (short)getWord(); /* Signed displacement */
  747. /* Note: the result of the subtraction could be between 32k and 64k, and
  748. still be positive; it is an offset from prog.Image. So this must be
  749. treated as unsigned */
  750. pIcode->ll()->replaceSrc((uint32_t)(off + (unsigned)(pInst - prog.Image)));
  751. pIcode->ll()->setFlags(I);
  752. }
  753. /***************************************************************************
  754. dispS - 1 uint8_t disp as immed relative to ip
  755. ***************************************************************************/
  756. static void dispS(int )
  757. {
  758. PROG &prog(Project::get()->prog);
  759. long off = signex(*pInst++); /* Signed displacement */
  760. pIcode->ll()->replaceSrc((uint32_t)(off + (unsigned)(pInst - prog.Image)));
  761. pIcode->ll()->setFlags(I);
  762. }
  763. /****************************************************************************
  764. dispF - 4 uint8_t disp as immed 20-bit target address
  765. ***************************************************************************/
  766. static void dispF(int )
  767. {
  768. uint32_t off = (unsigned)getWord();
  769. uint32_t seg = (unsigned)getWord();
  770. pIcode->ll()->replaceSrc(off + ((uint32_t)(unsigned)seg << 4));
  771. pIcode->ll()->setFlags(I);
  772. }
  773. /****************************************************************************
  774. prefix - picks up prefix uint8_t for following instruction (LOCK is ignored
  775. on purpose)
  776. ****************************************************************************/
  777. static void prefix(int )
  778. {
  779. if (pIcode->ll()->getOpcode() == iREPE || pIcode->ll()->getOpcode() == iREPNE)
  780. RepPrefix = pIcode->ll()->getOpcode();
  781. else
  782. SegPrefix = pIcode->ll()->getOpcode();
  783. }
  784. inline void BumpOpcode(LLInst &ll)
  785. {
  786. llIcode ic((llIcode)ll.getOpcode());
  787. ic = (llIcode)(((int)ic)+1); // Bump this icode via the int type
  788. ll.setOpcode(ic);
  789. }
  790. /*****************************************************************************
  791. strop - checks RepPrefix and converts string instructions accordingly
  792. *****************************************************************************/
  793. static void strop(int )
  794. {
  795. if (RepPrefix)
  796. {
  797. // pIcode->ll()->getOpcode() += ((pIcode->ll()->getOpcode() == iCMPS ||
  798. // pIcode->ll()->getOpcode() == iSCAS)
  799. // && RepPrefix == iREPE)? 2: 1;
  800. if ((pIcode->ll()->match(iCMPS) || pIcode->ll()->match(iSCAS) ) && RepPrefix == iREPE)
  801. BumpOpcode(*pIcode->ll()); // += 2
  802. BumpOpcode(*pIcode->ll()); // else += 1
  803. if (pIcode->ll()->match(iREP_LODS) )
  804. pIcode->ll()->setFlags(NOT_HLL);
  805. RepPrefix = 0;
  806. }
  807. }
  808. /***************************************************************************
  809. escop - esc operands
  810. ***************************************************************************/
  811. static void escop(int i)
  812. {
  813. pIcode->ll()->replaceSrc(REG(*pInst) + (uint32_t)((i & 7) << 3));
  814. pIcode->ll()->setFlags(I);
  815. rm(i);
  816. }
  817. /****************************************************************************
  818. const1
  819. ****************************************************************************/
  820. static void const1(int )
  821. {
  822. pIcode->ll()->replaceSrc(1);
  823. pIcode->ll()->setFlags(I);
  824. }
  825. /*****************************************************************************
  826. const3
  827. ****************************************************************************/
  828. static void const3(int )
  829. {
  830. pIcode->ll()->replaceSrc(3);
  831. pIcode->ll()->setFlags(I);
  832. }
  833. /****************************************************************************
  834. none1
  835. ****************************************************************************/
  836. static void none1(int )
  837. {
  838. }
  839. /****************************************************************************
  840. none2 - Sets the NO_OPS flag if the operand is immediate
  841. ****************************************************************************/
  842. static void none2(int )
  843. {
  844. if ( pIcode->ll()->testFlags(I) )
  845. pIcode->ll()->setFlags(NO_OPS);
  846. }
  847. /****************************************************************************
  848. Checks for int 34 to int 3B - if so, converts to ESC nn instruction
  849. ****************************************************************************/
  850. static void checkInt(int )
  851. {
  852. uint16_t wOp = (uint16_t) pIcode->ll()->src().getImm2();
  853. if ((wOp >= 0x34) && (wOp <= 0x3B))
  854. {
  855. /* This is a Borland/Microsoft floating point emulation instruction.
  856. Treat as if it is an ESC opcode */
  857. pIcode->ll()->replaceSrc(wOp - 0x34);
  858. pIcode->ll()->set(iESC,FLOAT_OP);
  859. escop(wOp - 0x34 + 0xD8);
  860. }
  861. }