ia32_insn.h 20 KB

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  1. #ifndef IA32_INSN_H
  2. #define IA32_INSN_H
  3. /* this file contains the structure of opcode definitions and the
  4. * constants they use */
  5. #include <sys/types.h>
  6. #include "libdis.h"
  7. #define GET_BYTE( buf, buf_len ) buf_len ? *buf : 0
  8. #define OP_SIZE_16 1
  9. #define OP_SIZE_32 2
  10. #define ADDR_SIZE_16 4
  11. #define ADDR_SIZE_32 8
  12. #define MAX_INSTRUCTION_SIZE 20
  13. /* invalid instructions are handled by returning 0 [error] from the
  14. * function, setting the size of the insn to 1 byte, and copying
  15. * the byte at the start of the invalid insn into the x86_insn_t.
  16. * if the caller is saving the x86_insn_t for invalid instructions,
  17. * instead of discarding them, this will maintain a consistent
  18. * address space in the x86_insn_ts */
  19. #define INVALID_INSN ((size_t) -1) /* return value for invalid insn */
  20. #define MAKE_INVALID( i, buf ) \
  21. strcpy( i->mnemonic, "invalid" ); \
  22. x86_oplist_free( i ); \
  23. i->size = 1; \
  24. i->group = insn_none; \
  25. i->type = insn_invalid; \
  26. memcpy( i->bytes, buf, 1 );
  27. size_t ia32_disasm_addr( unsigned char * buf, size_t buf_len,
  28. x86_insn_t *insn);
  29. /* --------------------------------------------------------- Table Lookup */
  30. /* IA32 Instruction defintion for ia32_opcodes.c */
  31. struct ia32_insn_t{
  32. unsigned int table; /* escape to this sub-table */
  33. unsigned int mnem_flag; /* Flags referring to mnemonic */
  34. unsigned int notes; /* Notes for this instruction */
  35. unsigned int dest_flag, src_flag, aux_flag; /* and for specific operands */
  36. unsigned int cpu; /* minimumCPU [AND with clocks?? */
  37. char mnemonic[16]; /* buffers for building instruction */
  38. char mnemonic_att[16]; /* at&t style mnemonic name */
  39. int32_t dest;
  40. int32_t src;
  41. int32_t aux;
  42. unsigned int flags_effected;
  43. unsigned int implicit_ops; /* implicit operands */
  44. };
  45. /* --------------------------------------------------------- Prefixes */
  46. /* Prefix Flags */
  47. /* Prefixes, same order as in the manual */
  48. /* had to reverse the values of the first three as they were entered into
  49. * libdis.h incorrectly. */
  50. #define PREFIX_LOCK 0x0004
  51. #define PREFIX_REPNZ 0x0002
  52. #define PREFIX_REPZ 0x0001
  53. #define PREFIX_OP_SIZE 0x0010
  54. #define PREFIX_ADDR_SIZE 0x0020
  55. #define PREFIX_CS 0x0100
  56. #define PREFIX_SS 0x0200
  57. #define PREFIX_DS 0x0300
  58. #define PREFIX_ES 0x0400
  59. #define PREFIX_FS 0x0500
  60. #define PREFIX_GS 0x0600
  61. #define PREFIX_TAKEN 0x1000 /* branch taken */
  62. #define PREFIX_NOTTAKEN 0x2000 /* branch not taken */
  63. #define PREFIX_REG_MASK 0x0F00
  64. #define BRANCH_HINT_MASK 0x3000
  65. #define PREFIX_PRINT_MASK 0x000F /* printable prefixes */
  66. #define PREFIX_MASK 0xFFFF
  67. /* ---------------------------------------------------------- CPU Type */
  68. #define cpu_8086 0x0001
  69. #define cpu_80286 0x0002
  70. #define cpu_80386 0x0003
  71. #define cpu_80387 0x0004 /* originally these were a co-proc */
  72. #define cpu_80486 0x0005
  73. #define cpu_PENTIUM 0x0006
  74. #define cpu_PENTPRO 0x0007
  75. #define cpu_PENTIUM2 0x0008
  76. #define cpu_PENTIUM3 0x0009
  77. #define cpu_PENTIUM4 0x000A
  78. #define cpu_K6 0x0010
  79. #define cpu_K7 0x0020
  80. #define cpu_ATHLON 0x0030
  81. #define CPU_MODEL_MASK 0xFFFF
  82. #define CPU_MODEL(cpu) (cpu & CPU_MODEL_MASK)
  83. /* intel instruction subsets */
  84. #define isa_GP 0x10000 /* General Purpose Instructions */
  85. #define isa_FPU 0x20000 /* FPU instructions */
  86. #define isa_FPUMGT 0x30000 /* FPU/SIMD Management */
  87. #define isa_MMX 0x40000 /* MMX */
  88. #define isa_SSE1 0x50000 /* SSE */
  89. #define isa_SSE2 0x60000 /* SSE 2 */
  90. #define isa_SSE3 0x70000 /* SSE 3 */
  91. #define isa_3DNOW 0x80000 /* AMD 3d Now */
  92. #define isa_SYS 0x90000 /* System Instructions */
  93. #define ISA_SUBSET_MASK 0xFFFF0000
  94. #define ISA_SUBSET(isa) (isa & ISA_SUBSET_MASK)
  95. /* ------------------------------------------------------ Operand Decoding */
  96. #define ARG_NONE 0
  97. /* Using a mask allows us to store info such as OP_SIGNED in the
  98. * operand flags field */
  99. #define OPFLAGS_MASK 0x0000FFFF
  100. /* Operand Addressing Methods, per intel manual */
  101. #define ADDRMETH_MASK 0x00FF0000
  102. /* note: for instructions with implied operands, use no ADDRMETH */
  103. #define ADDRMETH_A 0x00010000
  104. #define ADDRMETH_C 0x00020000
  105. #define ADDRMETH_D 0x00030000
  106. #define ADDRMETH_E 0x00040000
  107. #define ADDRMETH_F 0x00050000
  108. #define ADDRMETH_G 0x00060000
  109. #define ADDRMETH_I 0x00070000
  110. #define ADDRMETH_J 0x00080000
  111. #define ADDRMETH_M 0x00090000
  112. #define ADDRMETH_O 0x000A0000
  113. #define ADDRMETH_P 0x000B0000
  114. #define ADDRMETH_Q 0x000C0000
  115. #define ADDRMETH_R 0x000D0000
  116. #define ADDRMETH_S 0x000E0000
  117. #define ADDRMETH_T 0x000F0000
  118. #define ADDRMETH_V 0x00100000
  119. #define ADDRMETH_W 0x00110000
  120. #define ADDRMETH_X 0x00120000
  121. #define ADDRMETH_Y 0x00130000
  122. #define ADDRMETH_RR 0x00140000 /* gen reg hard-coded in opcode */
  123. #define ADDRMETH_RS 0x00150000 /* seg reg hard-coded in opcode */
  124. #define ADDRMETH_RT 0x00160000 /* test reg hard-coded in opcode */
  125. #define ADDRMETH_RF 0x00170000 /* fpu reg hard-coded in opcode */
  126. #define ADDRMETH_II 0x00180000 /* immediate hard-coded in opcode */
  127. #define ADDRMETH_PP 0x00190000 /* mm reg ONLY in modr/m field */
  128. #define ADDRMETH_VV 0x001A0000 /* xmm reg ONLY in mod/rm field */
  129. /* Operand Types, per intel manual */
  130. #define OPTYPE_MASK 0xFF000000
  131. #define OPTYPE_a 0x01000000 /* BOUND: h:h or w:w */
  132. #define OPTYPE_b 0x02000000 /* byte */
  133. #define OPTYPE_c 0x03000000 /* byte or word */
  134. #define OPTYPE_d 0x04000000 /* word */
  135. #define OPTYPE_dq 0x05000000 /* qword */
  136. #define OPTYPE_p 0x06000000 /* 16:16 or 16:32 pointer */
  137. #define OPTYPE_pi 0x07000000 /* dword MMX reg */
  138. #define OPTYPE_ps 0x08000000 /* 128-bit single fp */
  139. #define OPTYPE_q 0x09000000 /* dword */
  140. #define OPTYPE_s 0x0A000000 /* 6-byte descriptor */
  141. #define OPTYPE_ss 0x0B000000 /* scalar of 128-bit single fp */
  142. #define OPTYPE_si 0x0C000000 /* word general register */
  143. #define OPTYPE_v 0x0D000000 /* hword or word */
  144. #define OPTYPE_w 0x0E000000 /* hword */
  145. #define OPTYPE_m 0x0F000000 /* to handle LEA */
  146. #define OPTYPE_none 0xFF000000 /* no valid operand size, INVLPG */
  147. /* custom ones for FPU instructions */
  148. #define OPTYPE_fs 0x10000000 /* pointer to single-real*/
  149. #define OPTYPE_fd 0x20000000 /* pointer to double real */
  150. #define OPTYPE_fe 0x30000000 /* pointer to extended real */
  151. #define OPTYPE_fb 0x40000000 /* pointer to packed BCD */
  152. #define OPTYPE_fv 0x50000000 /* pointer to FPU env: 14|28-bytes */
  153. #define OPTYPE_ft 0x60000000 /* pointer to FPU state: 94|108-bytes */
  154. #define OPTYPE_fx 0x70000000 /* pointer to FPU regs: 512 bites */
  155. #define OPTYPE_fp 0x80000000 /* general fpu register: dbl ext */
  156. /* SSE2 operand types */
  157. #define OPTYPE_sd 0x90000000 /* scalar of 128-bit double fp */
  158. #define OPTYPE_pd 0xA0000000 /* 128-bit double fp */
  159. /* ---------------------------------------------- Opcode Table Descriptions */
  160. /* the table type describes how to handle byte/size increments before
  161. * and after lookup. Some tables re-use the current byte, others
  162. * consume a byte only if the ModR/M encodes no operands, etc */
  163. enum ia32_tbl_type_id {
  164. tbl_opcode = 0, /* standard opcode table: no surprises */
  165. tbl_prefix, /* Prefix Override, e.g. 66/F2/F3 */
  166. tbl_suffix, /* 3D Now style */
  167. tbl_extension, /* ModR/M extension: 00-FF -> 00-07 */
  168. tbl_ext_ext, /* extension of modr/m using R/M field */
  169. tbl_fpu, /* fpu table: 00-BF -> 00-0F */
  170. tbl_fpu_ext /* fpu extension : C0-FF -> 00-1F */
  171. };
  172. /* How it works:
  173. * Bytes are 'consumed' if the next table lookup requires that the byte
  174. * pointer be advanced in the instruction stream. 'Does not consume' means
  175. * that, when the lookup function recurses, the same byte it re-used in the
  176. * new table. It also means that size is not decremented, for example when
  177. * a ModR/M byte is used. Note that tbl_extension (ModR/M) instructions that
  178. * do not increase the size of an insn with their operands have a forced
  179. 3 size increase in the lookup algo. Weird, yes, confusing, yes, welcome
  180. * to the Intel ISA. Another note: tbl_prefix is used as an override, so an
  181. * empty insn in a prefix table causes the instruction in the original table
  182. * to be used, rather than an invalid insn being generated.
  183. * tbl_opcode uses current byte and consumes it
  184. * tbl_prefix uses current byte but does not consume it
  185. * tbl_suffix uses and consumes last byte in insn
  186. * tbl_extension uses current byte but does not consume it
  187. * tbl_ext_ext uses current byte but does not consume it
  188. * tbl_fpu uses current byte and consumes it
  189. * tbl_fpu_ext uses current byte but does not consume it
  190. */
  191. /* Convenience struct for opcode tables : these will be stored in a
  192. * 'table of tables' so we can use a table index instead of a pointer */
  193. typedef struct { /* Assembly instruction tables */
  194. ia32_insn_t *table; /* Pointer to table of instruction encodings */
  195. enum ia32_tbl_type_id type;
  196. unsigned char shift; /* amount to shift modrm byte */
  197. unsigned char mask; /* bit mask for look up */
  198. unsigned char minlim,maxlim; /* limits on min/max entries. */
  199. } ia32_table_desc_t;
  200. /* ---------------------------------------------- 'Cooked' Operand Type Info */
  201. /* Permissions: */
  202. #define OP_R 0x001 /* operand is READ */
  203. #define OP_W 0x002 /* operand is WRITTEN */
  204. #define OP_RW 0x003 /* (OP_R|OP_W): convenience macro */
  205. #define OP_X 0x004 /* operand is EXECUTED */
  206. #define OP_PERM_MASK 0x0000007 /* perms are NOT mutually exclusive */
  207. #define OP_PERM( type ) (type & OP_PERM_MASK)
  208. /* Flags */
  209. #define OP_SIGNED 0x010 /* operand is signed */
  210. #define OP_FLAG_MASK 0x0F0 /* mods are NOT mutually exclusive */
  211. #define OP_FLAGS( type ) (type & OP_FLAG_MASK)
  212. #define OP_REG_MASK 0x0000FFFF /* lower WORD is register ID */
  213. #define OP_REGTBL_MASK 0xFFFF0000 /* higher word is register type [gen/dbg] */
  214. #define OP_REGID( type ) (type & OP_REG_MASK)
  215. #define OP_REGTYPE( type ) (type & OP_REGTBL_MASK)
  216. /* ------------------------------------------'Cooked' Instruction Type Info */
  217. /* high-bit opcode types/insn meta-types */
  218. #define INS_FLAG_PREFIX 0x10000000 /* insn is a prefix */
  219. #define INS_FLAG_SUFFIX 0x20000000 /* followed by a suffix byte */
  220. #define INS_FLAG_MASK 0xFF000000
  221. /* insn notes */
  222. #define INS_NOTE_RING0 0x00000001 /* insn is privileged */
  223. #define INS_NOTE_SMM 0x00000002 /* Sys Mgt Mode only */
  224. #define INS_NOTE_SERIAL 0x00000004 /* serializes */
  225. #define INS_NOTE_NONSWAP 0x00000008 /* insn is not swapped in att format */ // could be separate field?
  226. #define INS_NOTE_NOSUFFIX 0x00000010 /* insn has no size suffix in att format */ // could be separate field?
  227. //#define INS_NOTE_NMI
  228. #define INS_INVALID 0
  229. /* instruction groups */
  230. #define INS_EXEC 0x1000
  231. #define INS_ARITH 0x2000
  232. #define INS_LOGIC 0x3000
  233. #define INS_STACK 0x4000
  234. #define INS_COND 0x5000
  235. #define INS_LOAD 0x6000
  236. #define INS_ARRAY 0x7000
  237. #define INS_BIT 0x8000
  238. #define INS_FLAG 0x9000
  239. #define INS_FPU 0xA000
  240. #define INS_TRAPS 0xD000
  241. #define INS_SYSTEM 0xE000
  242. #define INS_OTHER 0xF000
  243. #define INS_GROUP_MASK 0xF000
  244. #define INS_GROUP( type ) ( type & INS_GROUP_MASK )
  245. /* INS_EXEC group */
  246. #define INS_BRANCH (INS_EXEC | 0x01) /* Unconditional branch */
  247. #define INS_BRANCHCC (INS_EXEC | 0x02) /* Conditional branch */
  248. #define INS_CALL (INS_EXEC | 0x03) /* Jump to subroutine */
  249. #define INS_CALLCC (INS_EXEC | 0x04) /* Jump to subroutine */
  250. #define INS_RET (INS_EXEC | 0x05) /* Return from subroutine */
  251. /* INS_ARITH group */
  252. #define INS_ADD (INS_ARITH | 0x01)
  253. #define INS_SUB (INS_ARITH | 0x02)
  254. #define INS_MUL (INS_ARITH | 0x03)
  255. #define INS_DIV (INS_ARITH | 0x04)
  256. #define INS_INC (INS_ARITH | 0x05) /* increment */
  257. #define INS_DEC (INS_ARITH | 0x06) /* decrement */
  258. #define INS_SHL (INS_ARITH | 0x07) /* shift right */
  259. #define INS_SHR (INS_ARITH | 0x08) /* shift left */
  260. #define INS_ROL (INS_ARITH | 0x09) /* rotate left */
  261. #define INS_ROR (INS_ARITH | 0x0A) /* rotate right */
  262. #define INS_MIN (INS_ARITH | 0x0B) /* min func */
  263. #define INS_MAX (INS_ARITH | 0x0C) /* max func */
  264. #define INS_AVG (INS_ARITH | 0x0D) /* avg func */
  265. #define INS_FLR (INS_ARITH | 0x0E) /* floor func */
  266. #define INS_CEIL (INS_ARITH | 0x0F) /* ceiling func */
  267. /* INS_LOGIC group */
  268. #define INS_AND (INS_LOGIC | 0x01)
  269. #define INS_OR (INS_LOGIC | 0x02)
  270. #define INS_XOR (INS_LOGIC | 0x03)
  271. #define INS_NOT (INS_LOGIC | 0x04)
  272. #define INS_NEG (INS_LOGIC | 0x05)
  273. #define INS_NAND (INS_LOGIC | 0x06)
  274. /* INS_STACK group */
  275. #define INS_PUSH (INS_STACK | 0x01)
  276. #define INS_POP (INS_STACK | 0x02)
  277. #define INS_PUSHREGS (INS_STACK | 0x03) /* push register context */
  278. #define INS_POPREGS (INS_STACK | 0x04) /* pop register context */
  279. #define INS_PUSHFLAGS (INS_STACK | 0x05) /* push all flags */
  280. #define INS_POPFLAGS (INS_STACK | 0x06) /* pop all flags */
  281. #define INS_ENTER (INS_STACK | 0x07) /* enter stack frame */
  282. #define INS_LEAVE (INS_STACK | 0x08) /* leave stack frame */
  283. /* INS_COND group */
  284. #define INS_TEST (INS_COND | 0x01)
  285. #define INS_CMP (INS_COND | 0x02)
  286. /* INS_LOAD group */
  287. #define INS_MOV (INS_LOAD | 0x01)
  288. #define INS_MOVCC (INS_LOAD | 0x02)
  289. #define INS_XCHG (INS_LOAD | 0x03)
  290. #define INS_XCHGCC (INS_LOAD | 0x04)
  291. #define INS_CONV (INS_LOAD | 0x05) /* move and convert type */
  292. /* INS_ARRAY group */
  293. #define INS_STRCMP (INS_ARRAY | 0x01)
  294. #define INS_STRLOAD (INS_ARRAY | 0x02)
  295. #define INS_STRMOV (INS_ARRAY | 0x03)
  296. #define INS_STRSTOR (INS_ARRAY | 0x04)
  297. #define INS_XLAT (INS_ARRAY | 0x05)
  298. /* INS_BIT group */
  299. #define INS_BITTEST (INS_BIT | 0x01)
  300. #define INS_BITSET (INS_BIT | 0x02)
  301. #define INS_BITCLR (INS_BIT | 0x03)
  302. /* INS_FLAG group */
  303. #define INS_CLEARCF (INS_FLAG | 0x01) /* clear Carry flag */
  304. #define INS_CLEARZF (INS_FLAG | 0x02) /* clear Zero flag */
  305. #define INS_CLEAROF (INS_FLAG | 0x03) /* clear Overflow flag */
  306. #define INS_CLEARDF (INS_FLAG | 0x04) /* clear Direction flag */
  307. #define INS_CLEARSF (INS_FLAG | 0x05) /* clear Sign flag */
  308. #define INS_CLEARPF (INS_FLAG | 0x06) /* clear Parity flag */
  309. #define INS_SETCF (INS_FLAG | 0x07)
  310. #define INS_SETZF (INS_FLAG | 0x08)
  311. #define INS_SETOF (INS_FLAG | 0x09)
  312. #define INS_SETDF (INS_FLAG | 0x0A)
  313. #define INS_SETSF (INS_FLAG | 0x0B)
  314. #define INS_SETPF (INS_FLAG | 0x0C)
  315. #define INS_TOGCF (INS_FLAG | 0x10) /* toggle */
  316. #define INS_TOGZF (INS_FLAG | 0x20)
  317. #define INS_TOGOF (INS_FLAG | 0x30)
  318. #define INS_TOGDF (INS_FLAG | 0x40)
  319. #define INS_TOGSF (INS_FLAG | 0x50)
  320. #define INS_TOGPF (INS_FLAG | 0x60)
  321. /* INS_FPU */
  322. #define INS_FMOV (INS_FPU | 0x1)
  323. #define INS_FMOVCC (INS_FPU | 0x2)
  324. #define INS_FNEG (INS_FPU | 0x3)
  325. #define INS_FABS (INS_FPU | 0x4)
  326. #define INS_FADD (INS_FPU | 0x5)
  327. #define INS_FSUB (INS_FPU | 0x6)
  328. #define INS_FMUL (INS_FPU | 0x7)
  329. #define INS_FDIV (INS_FPU | 0x8)
  330. #define INS_FSQRT (INS_FPU | 0x9)
  331. #define INS_FCMP (INS_FPU | 0xA)
  332. #define INS_FCOS (INS_FPU | 0xC) /* cosine */
  333. #define INS_FLDPI (INS_FPU | 0xD) /* load pi */
  334. #define INS_FLDZ (INS_FPU | 0xE) /* load 0 */
  335. #define INS_FTAN (INS_FPU | 0xF) /* tanget */
  336. #define INS_FSINE (INS_FPU | 0x10) /* sine */
  337. #define INS_FSYS (INS_FPU | 0x20) /* misc */
  338. /* INS_TRAP */
  339. #define INS_TRAP (INS_TRAPS | 0x01) /* generate trap */
  340. #define INS_TRAPCC (INS_TRAPS | 0x02) /* conditional trap gen */
  341. #define INS_TRET (INS_TRAPS | 0x03) /* return from trap */
  342. #define INS_BOUNDS (INS_TRAPS | 0x04) /* gen bounds trap */
  343. #define INS_DEBUG (INS_TRAPS | 0x05) /* gen breakpoint trap */
  344. #define INS_TRACE (INS_TRAPS | 0x06) /* gen single step trap */
  345. #define INS_INVALIDOP (INS_TRAPS | 0x07) /* gen invalid insn */
  346. #define INS_OFLOW (INS_TRAPS | 0x08) /* gen overflow trap */
  347. #define INS_ICEBP (INS_TRAPS | 0x09) /* ICE breakpoint */
  348. /* INS_SYSTEM */
  349. #define INS_HALT (INS_SYSTEM | 0x01) /* halt machine */
  350. #define INS_IN (INS_SYSTEM | 0x02) /* input form port */
  351. #define INS_OUT (INS_SYSTEM | 0x03) /* output to port */
  352. #define INS_CPUID (INS_SYSTEM | 0x04) /* identify cpu */
  353. #define INS_LMSW (INS_SYSTEM | 0x05) /* load machine status word (CR0[3:0]) */
  354. #define INS_SMSW (INS_SYSTEM | 0x06) /* store machine status word (CR0[3:0]) */
  355. #define INS_CLTS (INS_SYSTEM | 0x07) /* clear task switched flag (CR0[3]) */
  356. /* INS_OTHER */
  357. #define INS_NOP (INS_OTHER | 0x01)
  358. #define INS_BCDCONV (INS_OTHER | 0x02) /* convert to/from BCD */
  359. #define INS_SZCONV (INS_OTHER | 0x03) /* convert size of operand */
  360. #define INS_SALC (INS_OTHER | 0x04) /* set %al on carry */
  361. #define INS_UNKNOWN (INS_OTHER | 0x05)
  362. #define INS_TYPE_MASK 0xFFFF
  363. #define INS_TYPE( type ) ( type & INS_TYPE_MASK )
  364. /* flags effected by instruction */
  365. #define INS_TEST_CARRY 0x01 /* carry */
  366. #define INS_TEST_ZERO 0x02 /* zero/equal */
  367. #define INS_TEST_OFLOW 0x04 /* overflow */
  368. #define INS_TEST_DIR 0x08 /* direction */
  369. #define INS_TEST_SIGN 0x10 /* negative */
  370. #define INS_TEST_PARITY 0x20 /* parity */
  371. #define INS_TEST_OR 0x40 /* used in jle */
  372. #define INS_TEST_NCARRY 0x100 /* ! carry */
  373. #define INS_TEST_NZERO 0x200 /* ! zero */
  374. #define INS_TEST_NOFLOW 0x400 /* ! oflow */
  375. #define INS_TEST_NDIR 0x800 /* ! dir */
  376. #define INS_TEST_NSIGN 0x1000 /* ! sign */
  377. #define INS_TEST_NPARITY 0x2000 /* ! parity */
  378. /* SF == OF */
  379. #define INS_TEST_SFEQOF 0x4000
  380. /* SF != OF */
  381. #define INS_TEST_SFNEOF 0x8000
  382. #define INS_TEST_ALL INS_TEST_CARRY | INS_TEST_ZERO | \
  383. INS_TEST_OFLOW | INS_TEST_SIGN | \
  384. INS_TEST_PARITY
  385. #define INS_SET_CARRY 0x010000 /* carry */
  386. #define INS_SET_ZERO 0x020000 /* zero/equal */
  387. #define INS_SET_OFLOW 0x040000 /* overflow */
  388. #define INS_SET_DIR 0x080000 /* direction */
  389. #define INS_SET_SIGN 0x100000 /* negative */
  390. #define INS_SET_PARITY 0x200000 /* parity */
  391. #define INS_SET_NCARRY 0x1000000
  392. #define INS_SET_NZERO 0x2000000
  393. #define INS_SET_NOFLOW 0x4000000
  394. #define INS_SET_NDIR 0x8000000
  395. #define INS_SET_NSIGN 0x10000000
  396. #define INS_SET_NPARITY 0x20000000
  397. #define INS_SET_SFEQOF 0x40000000
  398. #define INS_SET_SFNEOF 0x80000000
  399. #define INS_SET_ALL INS_SET_CARRY | INS_SET_ZERO | \
  400. INS_SET_OFLOW | INS_SET_SIGN | \
  401. INS_SET_PARITY
  402. #define INS_TEST_MASK 0x0000FFFF
  403. #define INS_FLAGS_TEST(x) (x & INS_TEST_MASK)
  404. #define INS_SET_MASK 0xFFFF0000
  405. #define INS_FLAGS_SET(x) (x & INS_SET_MASK)
  406. #if 0
  407. /* TODO: actually start using these */
  408. #define X86_PAIR_NP 1 /* not pairable; execs in U */
  409. #define X86_PAIR_PU 2 /* pairable in U pipe */
  410. #define X86_PAIR_PV 3 /* pairable in V pipe */
  411. #define X86_PAIR_UV 4 /* pairable in UV pipe */
  412. #define X86_PAIR_FX 5 /* pairable with FXCH */
  413. #define X86_EXEC_PORT_0 1
  414. #define X86_EXEC_PORT_1 2
  415. #define X86_EXEC_PORT_2 4
  416. #define X86_EXEC_PORT_3 8
  417. #define X86_EXEC_PORT_4 16
  418. #define X86_EXEC_UNITS
  419. typedef struct { /* representation of an insn during decoding */
  420. uint32_t flags; /* runtime settings */
  421. /* instruction prefixes and other foolishness */
  422. uint32_t prefix; /* encoding of prefix */
  423. char prefix_str[16]; /* mnemonics for prefix */
  424. uint32_t branch_hint; /* gah! */
  425. unsigned int cpu_ver; /* TODO: cpu version */
  426. unsigned int clocks; /* TODO: clock cycles: min/max */
  427. unsigned char last_prefix;
  428. /* runtime intruction decoding helpers */
  429. unsigned char mode; /* 16, 32, 64 */
  430. unsigned char gen_regs; /* offset of default general reg set */
  431. unsigned char sz_operand; /* operand size for insn */
  432. unsigned char sz_address; /* address size for insn */
  433. unsigned char uops; /* uops per insn */
  434. unsigned char pairing; /* np,pu,pv.lv */
  435. unsigned char exec_unit;
  436. unsigned char exec_port;
  437. unsigned char latency;
  438. } ia32_info_t;
  439. #define MODE_32 0 /* default */
  440. #define MODE_16 1
  441. #define MODE_64 2
  442. #endif
  443. #endif