INTEL_BUGS 580 B

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  1. PMOVMSKB
  2. Gd, Pq1H
  3. PMOVMSKB
  4. (66)
  5. Gd, Vdq1H
  6. should be
  7. PMOVMSKB
  8. Gd, Qq1H
  9. PMOVMSKB
  10. (66)
  11. Gd, Wdq1H
  12. The instruction represented by this opcode expression does not support any
  13. operand to be a memory location.
  14. MASKMOVQ
  15. Pq, Pq1H
  16. MASKMOVDQU
  17. (66)
  18. Vdq, Vdq1H
  19. should be
  20. MASKMOVQ
  21. Pq, Pq1H
  22. MASKMOVDQU
  23. (66)
  24. Vdq, Wdq1H
  25. MOVMSKPS
  26. Gd, Vps1H
  27. MOVMSKPD
  28. (66)
  29. Gd, Vpd1H
  30. should be
  31. MOVMSKPS
  32. Gd, Wps1H
  33. MOVMSKPD
  34. (66)
  35. Gd, Wpd1H
  36. The opcode table entries for LFS, LGS, and LSS
  37. L[FGS]S
  38. Mp
  39. should be
  40. L[FGS]S
  41. Gv,Mp
  42. MOVHLPS
  43. Vps, Vps
  44. MOVLHPS
  45. Vps, Vps
  46. should be
  47. MOVHLPS
  48. Vps, Wps
  49. MOVLHPS
  50. Vps, Wps