scanner.cpp 38 KB

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  1. /*****************************************************************************
  2. * dcc project scanner module
  3. * Implements a simple state driven scanner to convert 8086 machine code into
  4. * I-code
  5. * (C) Cristina Cifuentes, Jeff Ledermann
  6. ****************************************************************************/
  7. #include <cstring>
  8. #include "dcc.h"
  9. #include "scanner.h"
  10. #include "project.h"
  11. /* Parser flags */
  12. #define TO_REG 0x000100 /* rm is source */
  13. #define S_EXT 0x000200 /* sign extend */
  14. #define OP386 0x000400 /* 386 op-code */
  15. #define NSP 0x000800 /* NOT_HLL if SP is src or dst */
  16. #define ICODEMASK 0xFF00FF /* Masks off parser flags */
  17. static void rm(int i);
  18. static void modrm(int i);
  19. static void segrm(int i);
  20. static void data1(int i);
  21. static void data2(int i);
  22. static void regop(int i);
  23. static void segop(int i);
  24. static void strop(int i);
  25. static void escop(int i);
  26. static void axImp(int i);
  27. static void alImp(int i);
  28. static void axSrcIm(int i);
  29. static void memImp(int i);
  30. static void memReg0(int i);
  31. static void memOnly(int i);
  32. static void dispM(int i);
  33. static void dispS(int i);
  34. static void dispN(int i);
  35. static void dispF(int i);
  36. static void prefix(int i);
  37. static void immed(int i);
  38. static void shift(int i);
  39. static void arith(int i);
  40. static void trans(int i);
  41. static void const1(int i);
  42. static void const3(int i);
  43. static void none1(int i);
  44. static void none2(int i);
  45. static void checkInt(int i);
  46. #define iZERO (llIcode)0 // For neatness
  47. #define IC llIcode
  48. static struct {
  49. void (*state1)(int);
  50. void (*state2)(int);
  51. uint32_t flg;
  52. llIcode opcode;
  53. uint8_t df;
  54. uint8_t uf;
  55. } stateTable[] = {
  56. { modrm, none2, B , iADD , Sf | Zf | Cf , 0 }, /* 00 */
  57. { modrm, none2, 0 , iADD , Sf | Zf | Cf , 0 }, /* 01 */
  58. { modrm, none2, TO_REG | B , iADD , Sf | Zf | Cf , 0 }, /* 02 */
  59. { modrm, none2, TO_REG , iADD , Sf | Zf | Cf , 0 }, /* 03 */
  60. { data1, axImp, B , iADD , Sf | Zf | Cf , 0 }, /* 04 */
  61. { data2, axImp, 0 , iADD , Sf | Zf | Cf , 0 }, /* 05 */
  62. { segop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 06 */
  63. { segop, none2, NO_SRC , iPOP , 0 , 0 }, /* 07 */
  64. { modrm, none2, B , iOR , Sf | Zf | Cf , 0 }, /* 08 */
  65. { modrm, none2, NSP , iOR , Sf | Zf | Cf , 0 }, /* 09 */
  66. { modrm, none2, TO_REG | B , iOR , Sf | Zf | Cf , 0 }, /* 0A */
  67. { modrm, none2, TO_REG | NSP , iOR , Sf | Zf | Cf , 0 }, /* 0B */
  68. { data1, axImp, B , iOR , Sf | Zf | Cf , 0 }, /* 0C */
  69. { data2, axImp, 0 , iOR , Sf | Zf | Cf , 0 }, /* 0D */
  70. { segop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 0E */
  71. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 0F */
  72. { modrm, none2, B , iADC , Sf | Zf | Cf , Cf }, /* 10 */
  73. { modrm, none2, NSP , iADC , Sf | Zf | Cf , Cf }, /* 11 */
  74. { modrm, none2, TO_REG | B , iADC , Sf | Zf | Cf , Cf }, /* 12 */
  75. { modrm, none2, TO_REG | NSP , iADC , Sf | Zf | Cf , Cf }, /* 13 */
  76. { data1, axImp, B , iADC , Sf | Zf | Cf , Cf }, /* 14 */
  77. { data2, axImp, 0 , iADC , Sf | Zf | Cf , Cf }, /* 15 */
  78. { segop, none2, NOT_HLL | NO_SRC , iPUSH , 0 , 0 }, /* 16 */
  79. { segop, none2, NOT_HLL | NO_SRC , iPOP , 0 , 0 }, /* 17 */
  80. { modrm, none2, B , iSBB , Sf | Zf | Cf , Cf }, /* 18 */
  81. { modrm, none2, NSP , iSBB , Sf | Zf | Cf , Cf }, /* 19 */
  82. { modrm, none2, TO_REG | B , iSBB , Sf | Zf | Cf , Cf }, /* 1A */
  83. { modrm, none2, TO_REG | NSP , iSBB , Sf | Zf | Cf , Cf }, /* 1B */
  84. { data1, axImp, B , iSBB , Sf | Zf | Cf , Cf }, /* 1C */
  85. { data2, axImp, 0 , iSBB , Sf | Zf | Cf , Cf }, /* 1D */
  86. { segop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 1E */
  87. { segop, none2, NO_SRC , iPOP , 0 , 0 }, /* 1F */
  88. { modrm, none2, B , iAND , Sf | Zf | Cf , 0 }, /* 20 */
  89. { modrm, none2, NSP , iAND , Sf | Zf | Cf , 0 }, /* 21 */
  90. { modrm, none2, TO_REG | B , iAND , Sf | Zf | Cf , 0 }, /* 22 */
  91. { modrm, none2, TO_REG | NSP , iAND , Sf | Zf | Cf , 0 }, /* 23 */
  92. { data1, axImp, B , iAND , Sf | Zf | Cf , 0 }, /* 24 */
  93. { data2, axImp, 0 , iAND , Sf | Zf | Cf , 0 }, /* 25 */
  94. { prefix, none2, 0 , (IC)rES,0 , 0 }, /* 26 */
  95. { none1, axImp, NOT_HLL | B|NO_SRC , iDAA , Sf | Zf | Cf , 0 }, /* 27 */
  96. { modrm, none2, B , iSUB , Sf | Zf | Cf , 0 }, /* 28 */
  97. { modrm, none2, 0 , iSUB , Sf | Zf | Cf , 0 }, /* 29 */
  98. { modrm, none2, TO_REG | B , iSUB , Sf | Zf | Cf , 0 }, /* 2A */
  99. { modrm, none2, TO_REG , iSUB , Sf | Zf | Cf , 0 }, /* 2B */
  100. { data1, axImp, B , iSUB , Sf | Zf | Cf , 0 }, /* 2C */
  101. { data2, axImp, 0 , iSUB , Sf | Zf | Cf , 0 }, /* 2D */
  102. { prefix, none2, 0 , (IC)rCS,0 , 0 }, /* 2E */
  103. { none1, axImp, NOT_HLL | B|NO_SRC , iDAS , Sf | Zf | Cf , 0 }, /* 2F */
  104. { modrm, none2, B , iXOR , Sf | Zf | Cf , 0 }, /* 30 */
  105. { modrm, none2, NSP , iXOR , Sf | Zf | Cf , 0 }, /* 31 */
  106. { modrm, none2, TO_REG | B , iXOR , Sf | Zf | Cf , 0 }, /* 32 */
  107. { modrm, none2, TO_REG | NSP , iXOR , Sf | Zf | Cf , 0 }, /* 33 */
  108. { data1, axImp, B , iXOR , Sf | Zf | Cf , 0 }, /* 34 */
  109. { data2, axImp, 0 , iXOR , Sf | Zf | Cf , 0 }, /* 35 */
  110. { prefix, none2, 0 , (IC)rSS,0 , 0 }, /* 36 */
  111. { none1, axImp, NOT_HLL | NO_SRC , iAAA , Sf | Zf | Cf , 0 }, /* 37 */
  112. { modrm, none2, B , iCMP , Sf | Zf | Cf , 0 }, /* 38 */
  113. { modrm, none2, NSP , iCMP , Sf | Zf | Cf , 0 }, /* 39 */
  114. { modrm, none2, TO_REG | B , iCMP , Sf | Zf | Cf , 0 }, /* 3A */
  115. { modrm, none2, TO_REG | NSP , iCMP , Sf | Zf | Cf , 0 }, /* 3B */
  116. { data1, axImp, B , iCMP , Sf | Zf | Cf , 0 }, /* 3C */
  117. { data2, axImp, 0 , iCMP , Sf | Zf | Cf , 0 }, /* 3D */
  118. { prefix, none2, 0 , (IC)rDS,0 , 0 }, /* 3E */
  119. { none1, axImp, NOT_HLL | NO_SRC , iAAS , Sf | Zf | Cf , 0 }, /* 3F */
  120. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 40 */
  121. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 41 */
  122. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 42 */
  123. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 43 */
  124. { regop, none2, NOT_HLL , iINC , Sf | Zf , 0 }, /* 44 */
  125. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 45 */
  126. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 46 */
  127. { regop, none2, 0 , iINC , Sf | Zf , 0 }, /* 47 */
  128. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 48 */
  129. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 49 */
  130. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 4A */
  131. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 4B */
  132. { regop, none2, NOT_HLL , iDEC , Sf | Zf , 0 }, /* 4C */
  133. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 4D */
  134. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 4E */
  135. { regop, none2, 0 , iDEC , Sf | Zf , 0 }, /* 4F */
  136. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 50 */
  137. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 51 */
  138. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 52 */
  139. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 53 */
  140. { regop, none2, NOT_HLL | NO_SRC , iPUSH , 0 , 0 }, /* 54 */
  141. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 55 */
  142. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 56 */
  143. { regop, none2, NO_SRC , iPUSH , 0 , 0 }, /* 57 */
  144. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 58 */
  145. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 59 */
  146. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5A */
  147. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5B */
  148. { regop, none2, NOT_HLL | NO_SRC , iPOP , 0 , 0 }, /* 5C */
  149. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5D */
  150. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5E */
  151. { regop, none2, NO_SRC , iPOP , 0 , 0 }, /* 5F */
  152. { none1, none2, NOT_HLL | NO_OPS , iPUSHA, 0 , 0 }, /* 60 */
  153. { none1, none2, NOT_HLL | NO_OPS , iPOPA , 0 , 0 }, /* 61 */
  154. { memOnly, modrm, TO_REG | NSP , iBOUND, 0 , 0 }, /* 62 */
  155. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 63 */
  156. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 64 */
  157. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 65 */
  158. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 66 */
  159. { none1, none2, OP386 , iZERO , 0 , 0 }, /* 67 */
  160. { data2, none2, NO_SRC , iPUSH , 0 , 0 }, /* 68 */
  161. { modrm, data2, TO_REG | NSP , iIMUL , Sf | Zf | Cf , 0 }, /* 69 */
  162. { data1, none2, S_EXT | NO_SRC , iPUSH , 0 , 0 }, /* 6A */
  163. { modrm, data1, TO_REG | NSP | S_EXT , iIMUL , Sf | Zf | Cf , 0 }, /* 6B */
  164. { strop, memImp, NOT_HLL | B|IM_OPS , iINS , 0 , Df}, /* 6C */
  165. { strop, memImp, NOT_HLL | IM_OPS , iINS , 0 , Df}, /* 6D */
  166. { strop, memImp, NOT_HLL | B|IM_OPS , iOUTS , 0 , Df}, /* 6E */
  167. { strop, memImp, NOT_HLL | IM_OPS , iOUTS , 0 , Df}, /* 6F */
  168. { dispS, none2, NOT_HLL , iJO , 0 , 0 }, /* 70 */
  169. { dispS, none2, NOT_HLL , iJNO , 0 , 0 }, /* 71 */
  170. { dispS, none2, 0 , iJB , 0 , Cf }, /* 72 */
  171. { dispS, none2, 0 , iJAE , 0 , Cf }, /* 73 */
  172. { dispS, none2, 0 , iJE , 0 , Zf }, /* 74 */
  173. { dispS, none2, 0 , iJNE , 0 , Zf }, /* 75 */
  174. { dispS, none2, 0 , iJBE , 0 , Zf | Cf }, /* 76 */
  175. { dispS, none2, 0 , iJA , 0 , Zf | Cf }, /* 77 */
  176. { dispS, none2, 0 , iJS , 0 , Sf }, /* 78 */
  177. { dispS, none2, 0 , iJNS , 0 , Sf }, /* 79 */
  178. { dispS, none2, NOT_HLL , iJP , 0 , 0 }, /* 7A */
  179. { dispS, none2, NOT_HLL , iJNP , 0 , 0 }, /* 7B */
  180. { dispS, none2, 0 , iJL , 0 , Sf }, /* 7C */
  181. { dispS, none2, 0 , iJGE , 0 , Sf }, /* 7D */
  182. { dispS, none2, 0 , iJLE , 0 , Sf | Zf }, /* 7E */
  183. { dispS, none2, 0 , iJG , 0 , Sf | Zf }, /* 7F */
  184. { immed, data1, B , iZERO , 0 , 0 }, /* 80 */
  185. { immed, data2, NSP , iZERO , 0 , 0 }, /* 81 */
  186. { immed, data1, B , iZERO , 0 , 0 }, /* 82 */ /* ?? */
  187. { immed, data1, NSP | S_EXT , iZERO , 0 , 0 }, /* 83 */
  188. { modrm, none2, TO_REG | B , iTEST , Sf | Zf | Cf, 0 }, /* 84 */
  189. { modrm, none2, TO_REG | NSP , iTEST , Sf | Zf | Cf, 0 }, /* 85 */
  190. { modrm, none2, TO_REG | B , iXCHG , 0 , 0 }, /* 86 */
  191. { modrm, none2, TO_REG | NSP , iXCHG , 0 , 0 }, /* 87 */
  192. { modrm, none2, B , iMOV , 0 , 0 }, /* 88 */
  193. { modrm, none2, 0 , iMOV , 0 , 0 }, /* 89 */
  194. { modrm, none2, TO_REG | B , iMOV , 0 , 0 }, /* 8A */
  195. { modrm, none2, TO_REG , iMOV , 0 , 0 }, /* 8B */
  196. { segrm, none2, NSP , iMOV , 0 , 0 }, /* 8C */
  197. { memOnly, modrm, TO_REG | NSP , iLEA , 0 , 0 }, /* 8D */
  198. { segrm, none2, TO_REG | NSP , iMOV , 0 , 0 }, /* 8E */
  199. { memReg0, none2, NO_SRC , iPOP , 0 , 0 }, /* 8F */
  200. { none1, none2, NO_OPS , iNOP , 0 , 0 }, /* 90 */
  201. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 91 */
  202. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 92 */
  203. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 93 */
  204. { regop, axImp, NOT_HLL , iXCHG , 0 , 0 }, /* 94 */
  205. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 95 */
  206. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 96 */
  207. { regop, axImp, 0 , iXCHG , 0 , 0 }, /* 97 */
  208. { alImp, axImp, SRC_B | S_EXT , iSIGNEX,0 , 0 }, /* 98 */
  209. {axSrcIm, axImp, IM_DST | S_EXT , iSIGNEX,0 , 0 }, /* 99 */
  210. { dispF, none2, 0 , iCALLF ,0 , 0 }, /* 9A */
  211. { none1, none2, FLOAT_OP| NO_OPS , iWAIT , 0 , 0 }, /* 9B */
  212. { none1, none2, NOT_HLL | NO_OPS , iPUSHF, 0 , 0 }, /* 9C */
  213. { none1, none2, NOT_HLL | NO_OPS , iPOPF , Sf | Zf | Cf | Df,}, /* 9D */
  214. { none1, none2, NOT_HLL | NO_OPS , iSAHF , Sf | Zf | Cf, 0 }, /* 9E */
  215. { none1, none2, NOT_HLL | NO_OPS , iLAHF , 0 , Sf | Zf | Cf }, /* 9F */
  216. { dispM, axImp, B , iMOV , 0 , 0 }, /* A0 */
  217. { dispM, axImp, 0 , iMOV , 0 , 0 }, /* A1 */
  218. { dispM, axImp, TO_REG | B , iMOV , 0 , 0 }, /* A2 */
  219. { dispM, axImp, TO_REG , iMOV , 0 , 0 }, /* A3 */
  220. { strop, memImp, B | IM_OPS , iMOVS , 0 , Df }, /* A4 */
  221. { strop, memImp, IM_OPS , iMOVS , 0 , Df }, /* A5 */
  222. { strop, memImp, B | IM_OPS , iCMPS , Sf | Zf | Cf, Df }, /* A6 */
  223. { strop, memImp, IM_OPS , iCMPS , Sf | Zf | Cf, Df }, /* A7 */
  224. { data1, axImp, B , iTEST , Sf | Zf | Cf, 0 }, /* A8 */
  225. { data2, axImp, 0 , iTEST , Sf | Zf | Cf, 0 }, /* A9 */
  226. { strop, memImp, B | IM_OPS , iSTOS , 0 , Df }, /* AA */
  227. { strop, memImp, IM_OPS , iSTOS , 0 , Df }, /* AB */
  228. { strop, memImp, B | IM_OPS , iLODS , 0 , Df }, /* AC */
  229. { strop, memImp, IM_OPS , iLODS , 0 , Df }, /* AD */
  230. { strop, memImp, B | IM_OPS , iSCAS , Sf | Zf | Cf, Df }, /* AE */
  231. { strop, memImp, IM_OPS , iSCAS , Sf | Zf | Cf, Df }, /* AF */
  232. { regop, data1, B , iMOV , 0 , 0 }, /* B0 */
  233. { regop, data1, B , iMOV , 0 , 0 }, /* B1 */
  234. { regop, data1, B , iMOV , 0 , 0 }, /* B2 */
  235. { regop, data1, B , iMOV , 0 , 0 }, /* B3 */
  236. { regop, data1, B , iMOV , 0 , 0 }, /* B4 */
  237. { regop, data1, B , iMOV , 0 , 0 }, /* B5 */
  238. { regop, data1, B , iMOV , 0 , 0 }, /* B6 */
  239. { regop, data1, B , iMOV , 0 , 0 }, /* B7 */
  240. { regop, data2, 0 , iMOV , 0 , 0 }, /* B8 */
  241. { regop, data2, 0 , iMOV , 0 , 0 }, /* B9 */
  242. { regop, data2, 0 , iMOV , 0 , 0 }, /* BA */
  243. { regop, data2, 0 , iMOV , 0 , 0 }, /* BB */
  244. { regop, data2, NOT_HLL , iMOV , 0 , 0 }, /* BC */
  245. { regop, data2, 0 , iMOV , 0 , 0 }, /* BD */
  246. { regop, data2, 0 , iMOV , 0 , 0 }, /* BE */
  247. { regop, data2, 0 , iMOV , 0 , 0 }, /* BF */
  248. { shift, data1, B , iZERO , 0 , 0 }, /* C0 */
  249. { shift, data1, NSP | SRC_B , iZERO , 0 , 0 }, /* C1 */
  250. { data2, none2, 0 , iRET , 0 , 0 }, /* C2 */
  251. { none1, none2, NO_OPS , iRET , 0 , 0 }, /* C3 */
  252. { memOnly, modrm, TO_REG | NSP , iLES , 0 , 0 }, /* C4 */
  253. { memOnly, modrm, TO_REG | NSP , iLDS , 0 , 0 }, /* C5 */
  254. { memReg0, data1, B , iMOV , 0 , 0 }, /* C6 */
  255. { memReg0, data2, 0 , iMOV , 0 , 0 }, /* C7 */
  256. { data2, data1, 0 , iENTER, 0 , 0 }, /* C8 */
  257. { none1, none2, NO_OPS , iLEAVE, 0 , 0 }, /* C9 */
  258. { data2, none2, 0 , iRETF , 0 , 0 }, /* CA */
  259. { none1, none2, NO_OPS , iRETF , 0 , 0 }, /* CB */
  260. { const3, none2, NOT_HLL , iINT , 0 , 0 }, /* CC */
  261. { data1,checkInt, NOT_HLL , iINT , 0 , 0 }, /* CD */
  262. { none1, none2, NOT_HLL | NO_OPS , iINTO , 0 , 0 }, /* CE */
  263. { none1, none2, NOT_HLL | NO_OPS , iIRET , 0 , 0 }, /* Cf */
  264. { shift, const1, B , iZERO , 0 , 0 }, /* D0 */
  265. { shift, const1, SRC_B , iZERO , 0 , 0 }, /* D1 */
  266. { shift, none1, B , iZERO , 0 , 0 }, /* D2 */
  267. { shift, none1, SRC_B , iZERO , 0 , 0 }, /* D3 */
  268. { data1, axImp, NOT_HLL , iAAM , Sf | Zf | Cf, 0 }, /* D4 */
  269. { data1, axImp, NOT_HLL , iAAD , Sf | Zf | Cf, 0 }, /* D5 */
  270. { none1, none2, 0 , iZERO , 0 , 0 }, /* D6 */
  271. { memImp, axImp, NOT_HLL | B| IM_OPS, iXLAT , 0 , 0 }, /* D7 */
  272. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* D8 */
  273. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* D9 */
  274. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DA */
  275. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DB */
  276. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DC */
  277. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DD */
  278. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* DE */
  279. { escop, none2, FLOAT_OP , iESC , 0 , 0 }, /* Df */
  280. { dispS, none2, 0 , iLOOPNE,0 , Zf }, /* E0 */
  281. { dispS, none2, 0 , iLOOPE, 0 , Zf }, /* E1 */
  282. { dispS, none2, 0 , iLOOP , 0 , 0 }, /* E2 */
  283. { dispS, none2, 0 , iJCXZ , 0 , 0 }, /* E3 */
  284. { data1, axImp, NOT_HLL | B|NO_SRC , iIN , 0 , 0 }, /* E4 */
  285. { data1, axImp, NOT_HLL | NO_SRC , iIN , 0 , 0 }, /* E5 */
  286. { data1, axImp, NOT_HLL | B|NO_SRC , iOUT , 0 , 0 }, /* E6 */
  287. { data1, axImp, NOT_HLL | NO_SRC , iOUT , 0 , 0 }, /* E7 */
  288. { dispN, none2, 0 , iCALL , 0 , 0 }, /* E8 */
  289. { dispN, none2, 0 , iJMP , 0 , 0 }, /* E9 */
  290. { dispF, none2, 0 , iJMPF , 0 , 0 }, /* EA */
  291. { dispS, none2, 0 , iJMP , 0 , 0 }, /* EB */
  292. { none1, axImp, NOT_HLL | B|NO_SRC , iIN , 0 , 0 }, /* EC */
  293. { none1, axImp, NOT_HLL | NO_SRC , iIN , 0 , 0 }, /* ED */
  294. { none1, axImp, NOT_HLL | B|NO_SRC , iOUT , 0 , 0 }, /* EE */
  295. { none1, axImp, NOT_HLL | NO_SRC , iOUT , 0 , 0 }, /* EF */
  296. { none1, none2, NOT_HLL | NO_OPS , iLOCK , 0 , 0 }, /* F0 */
  297. { none1, none2, 0 , iZERO , 0 , 0 }, /* F1 */
  298. { prefix, none2, 0 , iREPNE, 0 , 0 }, /* F2 */
  299. { prefix, none2, 0 , iREPE , 0 , 0 }, /* F3 */
  300. { none1, none2, NOT_HLL | NO_OPS , iHLT , 0 , 0 }, /* F4 */
  301. { none1, none2, NO_OPS , iCMC , Cf, Cf }, /* F5 */
  302. { arith, none1, B , iZERO , 0 , 0 }, /* F6 */
  303. { arith, none1, NSP , iZERO , 0 , 0 }, /* F7 */
  304. { none1, none2, NO_OPS , iCLC , Cf, 0 }, /* F8 */
  305. { none1, none2, NO_OPS , iSTC , Cf, 0 }, /* F9 */
  306. { none1, none2, NOT_HLL | NO_OPS , iCLI , 0 , 0 }, /* FA */
  307. { none1, none2, NOT_HLL | NO_OPS , iSTI , 0 , 0 }, /* FB */
  308. { none1, none2, NO_OPS , iCLD , Df, 0 }, /* FC */
  309. { none1, none2, NO_OPS , iSTD , Df, 0 }, /* FD */
  310. { trans, none1, B , iZERO , 0 , 0 }, /* FE */
  311. { trans, none1, NSP , iZERO , 0 , 0 } /* FF */
  312. } ;
  313. static uint16_t SegPrefix, RepPrefix;
  314. static uint8_t *pInst; /* Ptr. to current uint8_t of instruction */
  315. static ICODE * pIcode; /* Ptr to Icode record filled in by scan() */
  316. /*****************************************************************************
  317. Scans one machine instruction at offset ip in prog.Image and returns error.
  318. At the same time, fill in low-level icode details for the scanned inst.
  319. ****************************************************************************/
  320. eErrorId scan(uint32_t ip, ICODE &p)
  321. {
  322. PROG &prog(Project::get()->prog);
  323. int op;
  324. p = ICODE();
  325. p.type = LOW_LEVEL;
  326. p.ll()->label = ip; /* ip is absolute offset into image*/
  327. if (ip >= (uint32_t)prog.cbImage)
  328. {
  329. return (IP_OUT_OF_RANGE);
  330. }
  331. SegPrefix = RepPrefix = 0;
  332. pInst = prog.Image + ip;
  333. pIcode = &p;
  334. do
  335. {
  336. op = *pInst++; /* First state - trivial */
  337. /* Convert to Icode.opcode */
  338. p.ll()->set(stateTable[op].opcode,stateTable[op].flg & ICODEMASK);
  339. p.ll()->flagDU.d = stateTable[op].df;
  340. p.ll()->flagDU.u = stateTable[op].uf;
  341. (*stateTable[op].state1)(op); /* Second state */
  342. (*stateTable[op].state2)(op); /* Third state */
  343. } while (stateTable[op].state1 == prefix); /* Loop if prefix */
  344. if (p.ll()->getOpcode())
  345. {
  346. /* Save bytes of image used */
  347. p.ll()->numBytes = (uint8_t)((pInst - prog.Image) - ip);
  348. return ((SegPrefix)? FUNNY_SEGOVR: /* Seg. Override invalid */
  349. (RepPrefix ? FUNNY_REP: NO_ERR));/* REP prefix invalid */
  350. }
  351. /* Else opcode error */
  352. return ((stateTable[op].flg & OP386)? INVALID_386OP: INVALID_OPCODE);
  353. }
  354. /***************************************************************************
  355. relocItem - returns true if uint16_t pointed at is in relocation table
  356. **************************************************************************/
  357. static bool relocItem(uint8_t *p)
  358. {
  359. PROG &prog(Project::get()->prog);
  360. int i;
  361. uint32_t off = p - prog.Image;
  362. for (i = 0; i < prog.cReloc; i++)
  363. if (prog.relocTable[i] == off)
  364. return true;
  365. return false;
  366. }
  367. /***************************************************************************
  368. getWord - returns next uint16_t from image
  369. **************************************************************************/
  370. static uint16_t getWord(void)
  371. {
  372. uint16_t w = LH(pInst);
  373. pInst += 2;
  374. return w;
  375. }
  376. /****************************************************************************
  377. signex - returns uint8_t sign extended to int
  378. ***************************************************************************/
  379. static int signex(uint8_t b)
  380. {
  381. long s = b;
  382. return ((b & 0x80)? (int)(0xFFFFFF00 | s): (int)s);
  383. }
  384. /****************************************************************************
  385. * setAddress - Updates the source or destination field for the current
  386. * icode, based on fdst and the TO_REG flag.
  387. * Note: fdst == true is for the r/m part of the field (dest, unless TO_REG)
  388. * fdst == false is for reg part of the field
  389. ***************************************************************************/
  390. static void setAddress(int i, boolT fdst, uint16_t seg, int16_t reg, uint16_t off)
  391. {
  392. LLOperand *pm;
  393. /* If not to register (i.e. to r/m), and talking about r/m,
  394. then this is dest */
  395. pm = (!(stateTable[i].flg & TO_REG) == fdst) ?
  396. &pIcode->ll()->dst : &pIcode->ll()->src;
  397. /* Set segment. A later procedure (lookupAddr in proclist.c) will
  398. * provide the value of this segment in the field segValue. */
  399. if (seg) /* segment override */
  400. {
  401. pm->seg = pm->segOver = (eReg)seg;
  402. }
  403. else
  404. { /* no override, check indexed register */
  405. if ((reg >= INDEX_BX_SI) && (reg == INDEX_BP_SI ||
  406. reg == INDEX_BP_DI || reg == INDEX_BP))
  407. {
  408. pm->seg = rSS; /* indexed on bp */
  409. }
  410. else
  411. {
  412. pm->seg = rDS; /* any other indexed reg */
  413. }
  414. }
  415. pm->regi = (eReg)reg;
  416. pm->off = (int16_t)off;
  417. if (reg && reg < INDEX_BX_SI && (stateTable[i].flg & B))
  418. {
  419. pm->regi = Machine_X86::subRegL(pm->regi);
  420. }
  421. if (seg) /* So we can catch invalid use of segment overrides */
  422. {
  423. SegPrefix = 0;
  424. }
  425. }
  426. /****************************************************************************
  427. rm - Decodes r/m part of modrm uint8_t for dst (unless TO_REG) part of icode
  428. ***************************************************************************/
  429. static void rm(int i)
  430. {
  431. uint8_t mod = *pInst >> 6;
  432. uint8_t rm = *pInst++ & 7;
  433. switch (mod) {
  434. case 0: /* No disp unless rm == 6 */
  435. if (rm == 6) {
  436. setAddress(i, true, SegPrefix, 0, getWord());
  437. pIcode->ll()->setFlags(WORD_OFF);
  438. }
  439. else
  440. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, 0);
  441. break;
  442. case 1: /* 1 uint8_t disp */
  443. setAddress(i, true, SegPrefix, rm+INDEX_BX_SI, (uint16_t)signex(*pInst++));
  444. break;
  445. case 2: /* 2 uint8_t disp */
  446. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, getWord());
  447. pIcode->ll()->setFlags(WORD_OFF);
  448. break;
  449. case 3: /* reg */
  450. setAddress(i, true, 0, rm + rAX, 0);
  451. break;
  452. }
  453. if ((stateTable[i].flg & NSP) && (pIcode->ll()->src.regi==rSP ||
  454. pIcode->ll()->dst.regi==rSP))
  455. pIcode->ll()->setFlags(NOT_HLL);
  456. }
  457. /****************************************************************************
  458. modrm - Sets up src and dst from modrm uint8_t
  459. ***************************************************************************/
  460. static void modrm(int i)
  461. {
  462. setAddress(i, false, 0, REG(*pInst) + rAX, 0);
  463. rm(i);
  464. }
  465. /****************************************************************************
  466. segrm - seg encoded as reg of modrm
  467. ****************************************************************************/
  468. static void segrm(int i)
  469. {
  470. int reg = REG(*pInst) + rES;
  471. if (reg > rDS || (reg == rCS && (stateTable[i].flg & TO_REG)))
  472. pIcode->ll()->setOpcode((llIcode)0); // setCBW because it has that index
  473. else {
  474. setAddress(i, false, 0, (int16_t)reg, 0);
  475. rm(i);
  476. }
  477. }
  478. /****************************************************************************
  479. regop - src/dst reg encoded as low 3 bits of opcode
  480. ***************************************************************************/
  481. static void regop(int i)
  482. {
  483. setAddress(i, false, 0, ((int16_t)i & 7) + rAX, 0);
  484. pIcode->ll()->dst.regi = pIcode->ll()->src.regi;
  485. }
  486. /*****************************************************************************
  487. segop - seg encoded in middle of opcode
  488. *****************************************************************************/
  489. static void segop(int i)
  490. {
  491. setAddress(i, true, 0, (((int16_t)i & 0x18) >> 3) + rES, 0);
  492. }
  493. /****************************************************************************
  494. axImp - Plugs an implied AX dst
  495. ***************************************************************************/
  496. static void axImp(int i)
  497. {
  498. setAddress(i, true, 0, rAX, 0);
  499. }
  500. /* Implied AX source */
  501. static void axSrcIm (int )
  502. {
  503. pIcode->ll()->src.regi = rAX;
  504. }
  505. /* Implied AL source */
  506. static void alImp (int )
  507. {
  508. pIcode->ll()->src.regi = rAL;
  509. }
  510. /*****************************************************************************
  511. memImp - Plugs implied src memory operand with any segment override
  512. ****************************************************************************/
  513. static void memImp(int i)
  514. {
  515. setAddress(i, false, SegPrefix, 0, 0);
  516. }
  517. /****************************************************************************
  518. memOnly - Instruction is not valid if modrm refers to register (i.e. mod == 3)
  519. ***************************************************************************/
  520. static void memOnly(int )
  521. {
  522. if ((*pInst & 0xC0) == 0xC0)
  523. pIcode->ll()->setOpcode((llIcode)0);
  524. }
  525. /****************************************************************************
  526. memReg0 - modrm for 'memOnly' and Reg field must also be 0
  527. ****************************************************************************/
  528. static void memReg0(int i)
  529. {
  530. if (REG(*pInst) || (*pInst & 0xC0) == 0xC0)
  531. pIcode->ll()->setOpcode((llIcode)0);
  532. else
  533. rm(i);
  534. }
  535. /***************************************************************************
  536. immed - Sets up dst and opcode from modrm uint8_t
  537. **************************************************************************/
  538. static void immed(int i)
  539. {
  540. static llIcode immedTable[8] = {iADD, iOR, iADC, iSBB, iAND, iSUB, iXOR, iCMP};
  541. static uint8_t uf[8] = { 0, 0, Cf, Cf, 0, 0, 0, 0 };
  542. pIcode->ll()->setOpcode(immedTable[REG(*pInst)]) ;
  543. pIcode->ll()->flagDU.u = uf[REG(*pInst)];
  544. pIcode->ll()->flagDU.d = (Sf | Zf | Cf);
  545. rm(i);
  546. if (pIcode->ll()->getOpcode() == iADD || pIcode->ll()->getOpcode() == iSUB)
  547. pIcode->ll()->clrFlags(NOT_HLL); /* Allow ADD/SUB SP, immed */
  548. }
  549. /****************************************************************************
  550. shift - Sets up dst and opcode from modrm uint8_t
  551. ***************************************************************************/
  552. static void shift(int i)
  553. {
  554. static llIcode shiftTable[8] =
  555. {
  556. (llIcode)iROL, (llIcode)iROR, (llIcode)iRCL, (llIcode)iRCR,
  557. (llIcode)iSHL, (llIcode)iSHR, (llIcode)0, (llIcode)iSAR};
  558. static uint8_t uf[8] = {0, 0, Cf, Cf, 0, 0, 0, 0 };
  559. static uint8_t df[8] = {Cf, Cf, Cf, Cf, Sf | Zf | Cf,
  560. Sf | Zf | Cf, 0, Sf | Zf | Cf};
  561. pIcode->ll()->setOpcode(shiftTable[REG(*pInst)]);
  562. pIcode->ll()->flagDU.u = uf[REG(*pInst)];
  563. pIcode->ll()->flagDU.d = df[REG(*pInst)];
  564. rm(i);
  565. pIcode->ll()->src.regi = rCL;
  566. }
  567. /****************************************************************************
  568. trans - Sets up dst and opcode from modrm uint8_t
  569. ***************************************************************************/
  570. static void trans(int i)
  571. {
  572. static llIcode transTable[8] =
  573. {
  574. (llIcode)iINC, (llIcode)iDEC, (llIcode)iCALL, (llIcode)iCALLF,
  575. (llIcode)iJMP, (llIcode)iJMPF,(llIcode)iPUSH, (llIcode)0
  576. };
  577. static uint8_t df[8] = {Sf | Zf, Sf | Zf, 0, 0, 0, 0, 0, 0};
  578. LLInst *ll = pIcode->ll();
  579. if ((uint8_t)REG(*pInst) < 2 || !(stateTable[i].flg & B)) { /* INC & DEC */
  580. ll->setOpcode(transTable[REG(*pInst)]); /* valid on bytes */
  581. ll->flagDU.d = df[REG(*pInst)];
  582. rm(i);
  583. ll->src = pIcode->ll()->dst;
  584. if (ll->match(iJMP) || ll->match(iCALL) || ll->match(iCALLF))
  585. ll->setFlags(NO_OPS);
  586. else if (ll->match(iINC) || ll->match(iPUSH) || ll->match(iDEC))
  587. ll->setFlags(NO_SRC);
  588. }
  589. }
  590. /****************************************************************************
  591. arith - Sets up dst and opcode from modrm uint8_t
  592. ****************************************************************************/
  593. static void arith(int i)
  594. {
  595. uint8_t opcode;
  596. static llIcode arithTable[8] =
  597. {
  598. iTEST , (llIcode)0, iNOT, iNEG,
  599. iMUL , iIMUL, iDIV, iIDIV
  600. };
  601. static uint8_t df[8] = {Sf | Zf | Cf, 0, 0, Sf | Zf | Cf,
  602. Sf | Zf | Cf, Sf | Zf | Cf, Sf | Zf | Cf,
  603. Sf | Zf | Cf};
  604. opcode = arithTable[REG(*pInst)];
  605. pIcode->ll()->setOpcode((llIcode)opcode);
  606. pIcode->ll()->flagDU.d = df[REG(*pInst)];
  607. rm(i);
  608. if (opcode == iTEST)
  609. {
  610. if (stateTable[i].flg & B)
  611. data1(i);
  612. else
  613. data2(i);
  614. }
  615. else if (!(opcode == iNOT || opcode == iNEG))
  616. {
  617. pIcode->ll()->src = pIcode->ll()->dst;
  618. setAddress(i, true, 0, rAX, 0); /* dst = AX */
  619. }
  620. else if (opcode == iNEG || opcode == iNOT)
  621. pIcode->ll()->setFlags(NO_SRC);
  622. if ((opcode == iDIV) || (opcode == iIDIV))
  623. {
  624. if ( not pIcode->ll()->testFlags(B) )
  625. pIcode->ll()->setFlags(IM_TMP_DST);
  626. }
  627. }
  628. /*****************************************************************************
  629. data1 - Sets up immed from 1 uint8_t data
  630. *****************************************************************************/
  631. static void data1(int i)
  632. {
  633. pIcode->ll()->src.SetImmediateOp( (stateTable[i].flg & S_EXT)? signex(*pInst++): *pInst++ );
  634. pIcode->ll()->setFlags(I);
  635. }
  636. /*****************************************************************************
  637. data2 - Sets up immed from 2 uint8_t data
  638. ****************************************************************************/
  639. static void data2(int )
  640. {
  641. if (relocItem(pInst))
  642. pIcode->ll()->setFlags(SEG_IMMED);
  643. /* ENTER is a special case, it does not take a destination operand,
  644. * but this field is being used as the number of bytes to allocate
  645. * on the stack. The procedure level is stored in the immediate
  646. * field. There is no source operand; therefore, the flag flg is
  647. * set to NO_OPS. */
  648. if (pIcode->ll()->getOpcode() == iENTER)
  649. {
  650. pIcode->ll()->dst.off = getWord();
  651. pIcode->ll()->setFlags(NO_OPS);
  652. }
  653. else
  654. pIcode->ll()->src.SetImmediateOp(getWord());
  655. pIcode->ll()->setFlags(I);
  656. }
  657. /****************************************************************************
  658. dispM - 2 uint8_t offset without modrm (== mod 0, rm 6) (Note:TO_REG bits are
  659. reversed)
  660. ****************************************************************************/
  661. static void dispM(int i)
  662. {
  663. setAddress(i, false, SegPrefix, 0, getWord());
  664. }
  665. /****************************************************************************
  666. dispN - 2 uint8_t disp as immed relative to ip
  667. ****************************************************************************/
  668. static void dispN(int )
  669. {
  670. PROG &prog(Project::get()->prog);
  671. long off = (short)getWord(); /* Signed displacement */
  672. /* Note: the result of the subtraction could be between 32k and 64k, and
  673. still be positive; it is an offset from prog.Image. So this must be
  674. treated as unsigned */
  675. pIcode->ll()->src.SetImmediateOp((uint32_t)(off + (unsigned)(pInst - prog.Image)));
  676. pIcode->ll()->setFlags(I);
  677. }
  678. /***************************************************************************
  679. dispS - 1 uint8_t disp as immed relative to ip
  680. ***************************************************************************/
  681. static void dispS(int )
  682. {
  683. PROG &prog(Project::get()->prog);
  684. long off = signex(*pInst++); /* Signed displacement */
  685. pIcode->ll()->src.SetImmediateOp((uint32_t)(off + (unsigned)(pInst - prog.Image)));
  686. pIcode->ll()->setFlags(I);
  687. }
  688. /****************************************************************************
  689. dispF - 4 uint8_t disp as immed 20-bit target address
  690. ***************************************************************************/
  691. static void dispF(int )
  692. {
  693. uint32_t off = (unsigned)getWord();
  694. uint32_t seg = (unsigned)getWord();
  695. pIcode->ll()->src.SetImmediateOp(off + ((uint32_t)(unsigned)seg << 4));
  696. pIcode->ll()->setFlags(I);
  697. }
  698. /****************************************************************************
  699. prefix - picks up prefix uint8_t for following instruction (LOCK is ignored
  700. on purpose)
  701. ****************************************************************************/
  702. static void prefix(int )
  703. {
  704. if (pIcode->ll()->getOpcode() == iREPE || pIcode->ll()->getOpcode() == iREPNE)
  705. RepPrefix = pIcode->ll()->getOpcode();
  706. else
  707. SegPrefix = pIcode->ll()->getOpcode();
  708. }
  709. inline void BumpOpcode(LLInst &ll)
  710. {
  711. llIcode ic((llIcode)ll.getOpcode());
  712. ic = (llIcode)(((int)ic)+1); // Bump this icode via the int type
  713. ll.setOpcode(ic);
  714. }
  715. /*****************************************************************************
  716. strop - checks RepPrefix and converts string instructions accordingly
  717. *****************************************************************************/
  718. static void strop(int )
  719. {
  720. if (RepPrefix)
  721. {
  722. // pIcode->ll()->getOpcode() += ((pIcode->ll()->getOpcode() == iCMPS ||
  723. // pIcode->ll()->getOpcode() == iSCAS)
  724. // && RepPrefix == iREPE)? 2: 1;
  725. if ((pIcode->ll()->match(iCMPS) || pIcode->ll()->match(iSCAS) ) && RepPrefix == iREPE)
  726. BumpOpcode(*pIcode->ll()); // += 2
  727. BumpOpcode(*pIcode->ll()); // else += 1
  728. if (pIcode->ll()->match(iREP_LODS) )
  729. pIcode->ll()->setFlags(NOT_HLL);
  730. RepPrefix = 0;
  731. }
  732. }
  733. /***************************************************************************
  734. escop - esc operands
  735. ***************************************************************************/
  736. static void escop(int i)
  737. {
  738. pIcode->ll()->src.SetImmediateOp(REG(*pInst) + (uint32_t)((i & 7) << 3));
  739. pIcode->ll()->setFlags(I);
  740. rm(i);
  741. }
  742. /****************************************************************************
  743. const1
  744. ****************************************************************************/
  745. static void const1(int )
  746. {
  747. pIcode->ll()->src.SetImmediateOp(1);
  748. pIcode->ll()->setFlags(I);
  749. }
  750. /*****************************************************************************
  751. const3
  752. ****************************************************************************/
  753. static void const3(int )
  754. {
  755. pIcode->ll()->src.SetImmediateOp(3);
  756. pIcode->ll()->setFlags(I);
  757. }
  758. /****************************************************************************
  759. none1
  760. ****************************************************************************/
  761. static void none1(int )
  762. {
  763. }
  764. /****************************************************************************
  765. none2 - Sets the NO_OPS flag if the operand is immediate
  766. ****************************************************************************/
  767. static void none2(int )
  768. {
  769. if ( pIcode->ll()->testFlags(I) )
  770. pIcode->ll()->setFlags(NO_OPS);
  771. }
  772. /****************************************************************************
  773. Checks for int 34 to int 3B - if so, converts to ESC nn instruction
  774. ****************************************************************************/
  775. static void checkInt(int )
  776. {
  777. uint16_t wOp = (uint16_t) pIcode->ll()->src.op();
  778. if ((wOp >= 0x34) && (wOp <= 0x3B))
  779. {
  780. /* This is a Borland/Microsoft floating point emulation instruction.
  781. Treat as if it is an ESC opcode */
  782. pIcode->ll()->src.SetImmediateOp(wOp - 0x34);
  783. pIcode->ll()->set(iESC,FLOAT_OP);
  784. escop(wOp - 0x34 + 0xD8);
  785. }
  786. }