scanner.cpp 42 KB

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  1. /*****************************************************************************
  2. * dcc project scanner module
  3. * Implements a simple state driven scanner to convert 8086 machine code into
  4. * I-code
  5. * (C) Cristina Cifuentes, Jeff Ledermann
  6. ****************************************************************************/
  7. #include <cstring>
  8. #include <map>
  9. #include <string>
  10. #include "dcc.h"
  11. #include "scanner.h"
  12. #include "project.h"
  13. /* Parser flags */
  14. #define TO_REG 0x000100 /* rm is source */
  15. #define S_EXT 0x000200 /* sign extend */
  16. #define OP386 0x000400 /* 386 op-code */
  17. #define NSP 0x000800 /* NOT_HLL if SP is src or dst */
  18. // defined in Enums.h #define ICODEMASK 0xFF00FF /* Masks off parser flags */
  19. static void rm(int i);
  20. static void modrm(int i);
  21. static void segrm(int i);
  22. static void data1(int i);
  23. static void data2(int i);
  24. static void regop(int i);
  25. static void segop(int i);
  26. static void strop(int i);
  27. static void escop(int i);
  28. static void axImp(int i);
  29. static void alImp(int i);
  30. static void axSrcIm(int i);
  31. static void memImp(int i);
  32. static void memReg0(int i);
  33. static void memOnly(int i);
  34. static void dispM(int i);
  35. static void dispS(int i);
  36. static void dispN(int i);
  37. static void dispF(int i);
  38. static void prefix(int i);
  39. static void immed(int i);
  40. static void shift(int i);
  41. static void arith(int i);
  42. static void trans(int i);
  43. static void const1(int i);
  44. static void const3(int i);
  45. static void none1(int i);
  46. static void none2(int i);
  47. static void checkInt(int i);
  48. #define iZERO (llIcode)0 // For neatness
  49. #define IC llIcode
  50. static struct {
  51. void (*state1)(int);
  52. void (*state2)(int);
  53. uint32_t flg;
  54. llIcode opcode;
  55. } stateTable[] = {
  56. { modrm, none2, B , iADD }, /* 00 */
  57. { modrm, none2, 0 , iADD }, /* 01 */
  58. { modrm, none2, TO_REG | B , iADD }, /* 02 */
  59. { modrm, none2, TO_REG , iADD }, /* 03 */
  60. { data1, axImp, B , iADD }, /* 04 */
  61. { data2, axImp, 0 , iADD }, /* 05 */
  62. { segop, none2, NO_SRC , iPUSH }, /* 06 */
  63. { segop, none2, NO_SRC , iPOP }, /* 07 */
  64. { modrm, none2, B , iOR }, /* 08 */
  65. { modrm, none2, NSP , iOR }, /* 09 */
  66. { modrm, none2, TO_REG | B , iOR }, /* 0A */
  67. { modrm, none2, TO_REG | NSP , iOR }, /* 0B */
  68. { data1, axImp, B , iOR }, /* 0C */
  69. { data2, axImp, 0 , iOR }, /* 0D */
  70. { segop, none2, NO_SRC , iPUSH }, /* 0E */
  71. { none1, none2, OP386 , iZERO }, /* 0F */
  72. { modrm, none2, B , iADC }, /* 10 */
  73. { modrm, none2, NSP , iADC }, /* 11 */
  74. { modrm, none2, TO_REG | B , iADC }, /* 12 */
  75. { modrm, none2, TO_REG | NSP , iADC }, /* 13 */
  76. { data1, axImp, B , iADC }, /* 14 */
  77. { data2, axImp, 0 , iADC }, /* 15 */
  78. { segop, none2, NOT_HLL | NO_SRC , iPUSH }, /* 16 */
  79. { segop, none2, NOT_HLL | NO_SRC , iPOP }, /* 17 */
  80. { modrm, none2, B , iSBB }, /* 18 */
  81. { modrm, none2, NSP , iSBB }, /* 19 */
  82. { modrm, none2, TO_REG | B , iSBB }, /* 1A */
  83. { modrm, none2, TO_REG | NSP , iSBB }, /* 1B */
  84. { data1, axImp, B , iSBB }, /* 1C */
  85. { data2, axImp, 0 , iSBB }, /* 1D */
  86. { segop, none2, NO_SRC , iPUSH }, /* 1E */
  87. { segop, none2, NO_SRC , iPOP }, /* 1F */
  88. { modrm, none2, B , iAND }, /* 20 */
  89. { modrm, none2, NSP , iAND }, /* 21 */
  90. { modrm, none2, TO_REG | B , iAND }, /* 22 */
  91. { modrm, none2, TO_REG | NSP , iAND }, /* 23 */
  92. { data1, axImp, B , iAND }, /* 24 */
  93. { data2, axImp, 0 , iAND }, /* 25 */
  94. { prefix, none2, 0 , (IC)rES}, /* 26 */
  95. { none1, axImp, NOT_HLL | B|NO_SRC , iDAA }, /* 27 */
  96. { modrm, none2, B , iSUB }, /* 28 */
  97. { modrm, none2, 0 , iSUB }, /* 29 */
  98. { modrm, none2, TO_REG | B , iSUB }, /* 2A */
  99. { modrm, none2, TO_REG , iSUB }, /* 2B */
  100. { data1, axImp, B , iSUB }, /* 2C */
  101. { data2, axImp, 0 , iSUB }, /* 2D */
  102. { prefix, none2, 0 , (IC)rCS}, /* 2E */
  103. { none1, axImp, NOT_HLL | B|NO_SRC , iDAS }, /* 2F */
  104. { modrm, none2, B , iXOR }, /* 30 */
  105. { modrm, none2, NSP , iXOR }, /* 31 */
  106. { modrm, none2, TO_REG | B , iXOR }, /* 32 */
  107. { modrm, none2, TO_REG | NSP , iXOR }, /* 33 */
  108. { data1, axImp, B , iXOR }, /* 34 */
  109. { data2, axImp, 0 , iXOR }, /* 35 */
  110. { prefix, none2, 0 , (IC)rSS}, /* 36 */
  111. { none1, axImp, NOT_HLL | NO_SRC , iAAA }, /* 37 */
  112. { modrm, none2, B , iCMP }, /* 38 */
  113. { modrm, none2, NSP , iCMP }, /* 39 */
  114. { modrm, none2, TO_REG | B , iCMP }, /* 3A */
  115. { modrm, none2, TO_REG | NSP , iCMP }, /* 3B */
  116. { data1, axImp, B , iCMP }, /* 3C */
  117. { data2, axImp, 0 , iCMP }, /* 3D */
  118. { prefix, none2, 0 , (IC)rDS}, /* 3E */
  119. { none1, axImp, NOT_HLL | NO_SRC , iAAS }, /* 3F */
  120. { regop, none2, 0 , iINC }, /* 40 */
  121. { regop, none2, 0 , iINC }, /* 41 */
  122. { regop, none2, 0 , iINC }, /* 42 */
  123. { regop, none2, 0 , iINC }, /* 43 */
  124. { regop, none2, NOT_HLL , iINC }, /* 44 */
  125. { regop, none2, 0 , iINC }, /* 45 */
  126. { regop, none2, 0 , iINC }, /* 46 */
  127. { regop, none2, 0 , iINC }, /* 47 */
  128. { regop, none2, 0 , iDEC }, /* 48 */
  129. { regop, none2, 0 , iDEC }, /* 49 */
  130. { regop, none2, 0 , iDEC }, /* 4A */
  131. { regop, none2, 0 , iDEC }, /* 4B */
  132. { regop, none2, NOT_HLL , iDEC }, /* 4C */
  133. { regop, none2, 0 , iDEC }, /* 4D */
  134. { regop, none2, 0 , iDEC }, /* 4E */
  135. { regop, none2, 0 , iDEC }, /* 4F */
  136. { regop, none2, NO_SRC , iPUSH }, /* 50 */
  137. { regop, none2, NO_SRC , iPUSH }, /* 51 */
  138. { regop, none2, NO_SRC , iPUSH }, /* 52 */
  139. { regop, none2, NO_SRC , iPUSH }, /* 53 */
  140. { regop, none2, NOT_HLL | NO_SRC , iPUSH }, /* 54 */
  141. { regop, none2, NO_SRC , iPUSH }, /* 55 */
  142. { regop, none2, NO_SRC , iPUSH }, /* 56 */
  143. { regop, none2, NO_SRC , iPUSH }, /* 57 */
  144. { regop, none2, NO_SRC , iPOP }, /* 58 */
  145. { regop, none2, NO_SRC , iPOP }, /* 59 */
  146. { regop, none2, NO_SRC , iPOP }, /* 5A */
  147. { regop, none2, NO_SRC , iPOP }, /* 5B */
  148. { regop, none2, NOT_HLL | NO_SRC , iPOP }, /* 5C */
  149. { regop, none2, NO_SRC , iPOP }, /* 5D */
  150. { regop, none2, NO_SRC , iPOP }, /* 5E */
  151. { regop, none2, NO_SRC , iPOP }, /* 5F */
  152. { none1, none2, NOT_HLL | NO_OPS , iPUSHA}, /* 60 */
  153. { none1, none2, NOT_HLL | NO_OPS , iPOPA }, /* 61 */
  154. { memOnly, modrm, TO_REG | NSP , iBOUND}, /* 62 */
  155. { none1, none2, OP386 , iZERO }, /* 63 */
  156. { none1, none2, OP386 , iZERO }, /* 64 */
  157. { none1, none2, OP386 , iZERO }, /* 65 */
  158. { none1, none2, OP386 , iZERO }, /* 66 */
  159. { none1, none2, OP386 , iZERO }, /* 67 */
  160. { data2, none2, NO_SRC , iPUSH }, /* 68 */
  161. { modrm, data2, TO_REG | NSP , iIMUL }, /* 69 */
  162. { data1, none2, S_EXT | NO_SRC , iPUSH }, /* 6A */
  163. { modrm, data1, TO_REG | NSP | S_EXT , iIMUL }, /* 6B */
  164. { strop, memImp, NOT_HLL | B|IM_OPS , iINS }, /* 6C */
  165. { strop, memImp, NOT_HLL | IM_OPS , iINS }, /* 6D */
  166. { strop, memImp, NOT_HLL | B|IM_OPS , iOUTS }, /* 6E */
  167. { strop, memImp, NOT_HLL | IM_OPS , iOUTS }, /* 6F */
  168. { dispS, none2, NOT_HLL , iJO }, /* 70 */
  169. { dispS, none2, NOT_HLL , iJNO }, /* 71 */
  170. { dispS, none2, 0 , iJB }, /* 72 */
  171. { dispS, none2, 0 , iJAE }, /* 73 */
  172. { dispS, none2, 0 , iJE }, /* 74 */
  173. { dispS, none2, 0 , iJNE }, /* 75 */
  174. { dispS, none2, 0 , iJBE }, /* 76 */
  175. { dispS, none2, 0 , iJA }, /* 77 */
  176. { dispS, none2, 0 , iJS }, /* 78 */
  177. { dispS, none2, 0 , iJNS }, /* 79 */
  178. { dispS, none2, NOT_HLL , iJP }, /* 7A */
  179. { dispS, none2, NOT_HLL , iJNP }, /* 7B */
  180. { dispS, none2, 0 , iJL }, /* 7C */
  181. { dispS, none2, 0 , iJGE }, /* 7D */
  182. { dispS, none2, 0 , iJLE }, /* 7E */
  183. { dispS, none2, 0 , iJG }, /* 7F */
  184. { immed, data1, B , iZERO }, /* 80 */
  185. { immed, data2, NSP , iZERO }, /* 81 */
  186. { immed, data1, B , iZERO }, /* 82 */ /* ?? */
  187. { immed, data1, NSP | S_EXT , iZERO }, /* 83 */
  188. { modrm, none2, TO_REG | B , iTEST }, /* 84 */
  189. { modrm, none2, TO_REG | NSP , iTEST }, /* 85 */
  190. { modrm, none2, TO_REG | B , iXCHG }, /* 86 */
  191. { modrm, none2, TO_REG | NSP , iXCHG }, /* 87 */
  192. { modrm, none2, B , iMOV }, /* 88 */
  193. { modrm, none2, 0 , iMOV }, /* 89 */
  194. { modrm, none2, TO_REG | B , iMOV }, /* 8A */
  195. { modrm, none2, TO_REG , iMOV }, /* 8B */
  196. { segrm, none2, NSP , iMOV }, /* 8C */
  197. { memOnly, modrm, TO_REG | NSP , iLEA }, /* 8D */
  198. { segrm, none2, TO_REG | NSP , iMOV }, /* 8E */
  199. { memReg0, none2, NO_SRC , iPOP }, /* 8F */
  200. { none1, none2, NO_OPS , iNOP }, /* 90 */
  201. { regop, axImp, 0 , iXCHG }, /* 91 */
  202. { regop, axImp, 0 , iXCHG }, /* 92 */
  203. { regop, axImp, 0 , iXCHG }, /* 93 */
  204. { regop, axImp, NOT_HLL , iXCHG }, /* 94 */
  205. { regop, axImp, 0 , iXCHG }, /* 95 */
  206. { regop, axImp, 0 , iXCHG }, /* 96 */
  207. { regop, axImp, 0 , iXCHG }, /* 97 */
  208. { alImp, axImp, SRC_B | S_EXT , iSIGNEX}, /* 98 */
  209. {axSrcIm, axImp, IM_DST | S_EXT , iSIGNEX}, /* 99 */
  210. { dispF, none2, 0 , iCALLF }, /* 9A */
  211. { none1, none2, FLOAT_OP| NO_OPS , iWAIT }, /* 9B */
  212. { none1, none2, NOT_HLL | NO_OPS , iPUSHF}, /* 9C */
  213. { none1, none2, NOT_HLL | NO_OPS , iPOPF }, /* 9D */
  214. { none1, none2, NOT_HLL | NO_OPS , iSAHF }, /* 9E */
  215. { none1, none2, NOT_HLL | NO_OPS , iLAHF }, /* 9F */
  216. { dispM, axImp, B , iMOV }, /* A0 */
  217. { dispM, axImp, 0 , iMOV }, /* A1 */
  218. { dispM, axImp, TO_REG | B , iMOV }, /* A2 */
  219. { dispM, axImp, TO_REG , iMOV }, /* A3 */
  220. { strop, memImp, B | IM_OPS , iMOVS }, /* A4 */
  221. { strop, memImp, IM_OPS , iMOVS }, /* A5 */
  222. { strop, memImp, B | IM_OPS , iCMPS }, /* A6 */
  223. { strop, memImp, IM_OPS , iCMPS }, /* A7 */
  224. { data1, axImp, B , iTEST }, /* A8 */
  225. { data2, axImp, 0 , iTEST }, /* A9 */
  226. { strop, memImp, B | IM_OPS , iSTOS }, /* AA */
  227. { strop, memImp, IM_OPS , iSTOS }, /* AB */
  228. { strop, memImp, B | IM_OPS , iLODS }, /* AC */
  229. { strop, memImp, IM_OPS , iLODS }, /* AD */
  230. { strop, memImp, B | IM_OPS , iSCAS }, /* AE */
  231. { strop, memImp, IM_OPS , iSCAS }, /* AF */
  232. { regop, data1, B , iMOV }, /* B0 */
  233. { regop, data1, B , iMOV }, /* B1 */
  234. { regop, data1, B , iMOV }, /* B2 */
  235. { regop, data1, B , iMOV }, /* B3 */
  236. { regop, data1, B , iMOV }, /* B4 */
  237. { regop, data1, B , iMOV }, /* B5 */
  238. { regop, data1, B , iMOV }, /* B6 */
  239. { regop, data1, B , iMOV }, /* B7 */
  240. { regop, data2, 0 , iMOV }, /* B8 */
  241. { regop, data2, 0 , iMOV }, /* B9 */
  242. { regop, data2, 0 , iMOV }, /* BA */
  243. { regop, data2, 0 , iMOV }, /* BB */
  244. { regop, data2, NOT_HLL , iMOV }, /* BC */
  245. { regop, data2, 0 , iMOV }, /* BD */
  246. { regop, data2, 0 , iMOV }, /* BE */
  247. { regop, data2, 0 , iMOV }, /* BF */
  248. { shift, data1, B , iZERO }, /* C0 */
  249. { shift, data1, NSP | SRC_B , iZERO }, /* C1 */
  250. { data2, none2, 0 , iRET }, /* C2 */
  251. { none1, none2, NO_OPS , iRET }, /* C3 */
  252. { memOnly, modrm, TO_REG | NSP , iLES }, /* C4 */
  253. { memOnly, modrm, TO_REG | NSP , iLDS }, /* C5 */
  254. { memReg0, data1, B , iMOV }, /* C6 */
  255. { memReg0, data2, 0 , iMOV }, /* C7 */
  256. { data2, data1, 0 , iENTER}, /* C8 */
  257. { none1, none2, NO_OPS , iLEAVE}, /* C9 */
  258. { data2, none2, 0 , iRETF }, /* CA */
  259. { none1, none2, NO_OPS , iRETF }, /* CB */
  260. { const3, none2, NOT_HLL , iINT }, /* CC */
  261. { data1,checkInt, NOT_HLL , iINT }, /* CD */
  262. { none1, none2, NOT_HLL | NO_OPS , iINTO }, /* CE */
  263. { none1, none2, NOT_HLL | NO_OPS , iIRET }, /* Cf */
  264. { shift, const1, B , iZERO }, /* D0 */
  265. { shift, const1, SRC_B , iZERO }, /* D1 */
  266. { shift, none1, B , iZERO }, /* D2 */
  267. { shift, none1, SRC_B , iZERO }, /* D3 */
  268. { data1, axImp, NOT_HLL , iAAM }, /* D4 */
  269. { data1, axImp, NOT_HLL , iAAD }, /* D5 */
  270. { none1, none2, 0 , iZERO }, /* D6 */
  271. { memImp, axImp, NOT_HLL | B| IM_OPS , iXLAT }, /* D7 */
  272. { escop, none2, FLOAT_OP , iESC }, /* D8 */
  273. { escop, none2, FLOAT_OP , iESC }, /* D9 */
  274. { escop, none2, FLOAT_OP , iESC }, /* DA */
  275. { escop, none2, FLOAT_OP , iESC }, /* DB */
  276. { escop, none2, FLOAT_OP , iESC }, /* DC */
  277. { escop, none2, FLOAT_OP , iESC }, /* DD */
  278. { escop, none2, FLOAT_OP , iESC }, /* DE */
  279. { escop, none2, FLOAT_OP , iESC }, /* Df */
  280. { dispS, none2, 0 , iLOOPNE}, /* E0 */
  281. { dispS, none2, 0 , iLOOPE}, /* E1 */
  282. { dispS, none2, 0 , iLOOP }, /* E2 */
  283. { dispS, none2, 0 , iJCXZ }, /* E3 */
  284. { data1, axImp, NOT_HLL | B|NO_SRC , iIN }, /* E4 */
  285. { data1, axImp, NOT_HLL | NO_SRC , iIN }, /* E5 */
  286. { data1, axImp, NOT_HLL | B|NO_SRC , iOUT }, /* E6 */
  287. { data1, axImp, NOT_HLL | NO_SRC , iOUT }, /* E7 */
  288. { dispN, none2, 0 , iCALL }, /* E8 */
  289. { dispN, none2, 0 , iJMP }, /* E9 */
  290. { dispF, none2, 0 , iJMPF }, /* EA */
  291. { dispS, none2, 0 , iJMP }, /* EB */
  292. { none1, axImp, NOT_HLL | B|NO_SRC , iIN }, /* EC */
  293. { none1, axImp, NOT_HLL | NO_SRC , iIN }, /* ED */
  294. { none1, axImp, NOT_HLL | B|NO_SRC , iOUT }, /* EE */
  295. { none1, axImp, NOT_HLL | NO_SRC , iOUT }, /* EF */
  296. { none1, none2, NOT_HLL | NO_OPS , iLOCK }, /* F0 */
  297. { none1, none2, 0 , iZERO }, /* F1 */
  298. { prefix, none2, 0 , iREPNE}, /* F2 */
  299. { prefix, none2, 0 , iREPE }, /* F3 */
  300. { none1, none2, NOT_HLL | NO_OPS , iHLT }, /* F4 */
  301. { none1, none2, NO_OPS , iCMC }, /* F5 */
  302. { arith, none1, B , iZERO }, /* F6 */
  303. { arith, none1, NSP , iZERO }, /* F7 */
  304. { none1, none2, NO_OPS , iCLC }, /* F8 */
  305. { none1, none2, NO_OPS , iSTC }, /* F9 */
  306. { none1, none2, NOT_HLL | NO_OPS , iCLI }, /* FA */
  307. { none1, none2, NOT_HLL | NO_OPS , iSTI }, /* FB */
  308. { none1, none2, NO_OPS , iCLD }, /* FC */
  309. { none1, none2, NO_OPS , iSTD }, /* FD */
  310. { trans, none1, B , iZERO }, /* FE */
  311. { trans, none1, NSP , iZERO } /* FF */
  312. } ;
  313. static uint16_t SegPrefix, RepPrefix;
  314. static const uint8_t *pInst; /* Ptr. to current uint8_t of instruction */
  315. static ICODE * pIcode; /* Ptr to Icode record filled in by scan() */
  316. static void decodeBranchTgt(x86_insn_t &insn)
  317. {
  318. x86_op_t *tgt_op = insn.x86_get_branch_target();
  319. if(tgt_op->type==op_expression)
  320. return; // unhandled for now
  321. if(tgt_op->type==op_register)
  322. return; // unhandled for now
  323. int32_t addr = tgt_op->getAddress();
  324. if(tgt_op->is_relative())
  325. {
  326. addr += insn.addr+insn.size;
  327. }
  328. pIcode->ll()->replaceSrc((uint32_t)addr);
  329. pIcode->ll()->setFlags(I);
  330. // PROG &prog(Project::get()->prog);
  331. // long off = (short)getWord(); /* Signed displacement */
  332. // assert(addr==(uint32_t)(off + (unsigned)(pInst - prog.image())));
  333. }
  334. static void convertUsedFlags(x86_insn_t &from,ICODE &to)
  335. {
  336. to.ll()->flagDU.d=0;
  337. to.ll()->flagDU.u=0;
  338. if(from.containsFlag(insn_eflag_carry,from.flags_set))
  339. to.ll()->flagDU.d |= Cf;
  340. if(from.containsFlag(insn_eflag_sign,from.flags_set))
  341. to.ll()->flagDU.d |= Sf;
  342. if(from.containsFlag(insn_eflag_zero,from.flags_set))
  343. to.ll()->flagDU.d |= Zf;
  344. if(from.containsFlag(insn_eflag_direction,from.flags_set))
  345. to.ll()->flagDU.d |= Df;
  346. if(from.containsFlag(insn_eflag_carry,from.flags_tested))
  347. to.ll()->flagDU.u |= Cf;
  348. if(from.containsFlag(insn_eflag_sign,from.flags_tested))
  349. to.ll()->flagDU.u |= Sf;
  350. if(from.containsFlag(insn_eflag_zero,from.flags_tested))
  351. to.ll()->flagDU.u |= Zf;
  352. if(from.containsFlag(insn_eflag_direction,from.flags_tested))
  353. to.ll()->flagDU.u |= Df;
  354. }
  355. static void convertPrefix(x86_insn_prefix prefix,ICODE &to)
  356. {
  357. if(prefix ==insn_no_prefix)
  358. return;
  359. // insn_lock - no need to handle
  360. RepPrefix = (uint16_t)prefix & ~insn_lock;
  361. }
  362. /****************************************************************************
  363. Checks for int 34 to int 3B - if so, converts to ESC nn instruction
  364. ****************************************************************************/
  365. static void fixFloatEmulation(x86_insn_t &insn)
  366. {
  367. if(insn.operand_count==0)
  368. return;
  369. if(insn.group!=x86_insn_t::insn_interrupt)
  370. return;
  371. PROG &prog(Project::get()->prog);
  372. uint16_t wOp=insn.x86_get_imm()->data.word;
  373. if ((wOp < 0x34) || (wOp > 0x3B))
  374. return;
  375. uint8_t buf[16];
  376. /* This is a Borland/Microsoft floating point emulation instruction. Treat as if it is an ESC opcode */
  377. int actual_valid_bytes=std::min(16U,prog.cbImage-insn.offset);
  378. memcpy(buf,prog.image()+insn.offset,actual_valid_bytes);
  379. X86_Disasm ds(opt_16_bit);
  380. x86_insn_t patched_insn;
  381. //patch actual instruction into buffer;
  382. buf[1] = wOp-0x34+0xD8;
  383. ds.x86_disasm(buf,actual_valid_bytes,0,1,&patched_insn);
  384. patched_insn.addr = insn.addr; // actual address
  385. patched_insn.offset = insn.offset; // actual offset
  386. insn = patched_insn;
  387. insn.size += 1; // to account for emulator call INT
  388. }
  389. int disassembleOneLibDisasm(uint32_t ip,x86_insn_t &l)
  390. {
  391. PROG &prog(Project::get()->prog);
  392. X86_Disasm ds(opt_16_bit);
  393. int cnt=ds.x86_disasm(prog.image(),prog.cbImage,0,ip,&l);
  394. if(cnt && l.is_valid())
  395. {
  396. fixFloatEmulation(l); //can change 'l'
  397. }
  398. if(l.is_valid())
  399. return l.size;
  400. return 0;
  401. }
  402. eReg convertRegister(const x86_reg_t &reg)
  403. {
  404. if( (reg_pc==reg.type) || (0==reg.id))
  405. return rUNDEF;
  406. eReg regmap[]={ rUNDEF,
  407. rUNDEF,rUNDEF,rUNDEF,rUNDEF, //eax ecx ebx edx
  408. rSP,rUNDEF,rUNDEF,rDI, //esp ebp esi edi
  409. rAX,rCX,rDX,rBX,
  410. rSP,rBP,rSI,rDI,
  411. rAL,rCL,rDL,rBL,
  412. rAH,rCH,rDH,rBH
  413. };
  414. std::map<std::string,eReg> nameToEnum = {{"es",rES},{"ds",rDS},{"cs",rCS},{"ss",rSS}};
  415. if(nameToEnum.find(reg.name)!=nameToEnum.end())
  416. return nameToEnum[reg.name];
  417. assert(reg.id<sizeof(regmap)/sizeof(eReg));
  418. assert(regmap[reg.id]!=rUNDEF);
  419. return regmap[reg.id];
  420. }
  421. LLOperand convertExpression(const x86_ea_t &from)
  422. {
  423. // BASE + Scale*Index + Disp
  424. LLOperand res;
  425. res.seg = rDS;
  426. /*
  427. INDEX_BX_SI = 22, // "bx+si"
  428. INDEX_BX_DI, // "bx+di"
  429. INDEX_BP_SI, // "bp+si"
  430. INDEX_BP_DI, // "bp+di"
  431. INDEX_SI, // "si"
  432. INDEX_DI, // "di"
  433. INDEX_BP, // "bp"
  434. INDEX_BX, // "bx"
  435. */
  436. if(from.base.id)
  437. {
  438. eReg base_reg = convertRegister(from.base);
  439. eReg index_reg = convertRegister(from.index);
  440. // if(base_reg==rBX)
  441. switch(base_reg)
  442. {
  443. case rDI:
  444. res.regi = INDEX_DI; break;
  445. case rBP:
  446. res.seg=rSS;
  447. switch(index_reg)
  448. {
  449. case rDI:
  450. res.regi = INDEX_BP_DI; break;
  451. case rSI:
  452. res.regi = INDEX_BP_SI; break;
  453. case rUNDEF:
  454. res.regi = INDEX_BP; break;
  455. default:
  456. assert(false);
  457. }
  458. break;
  459. case rBX:
  460. switch(index_reg)
  461. {
  462. case rDI:
  463. res.regi = INDEX_BX_DI; break;
  464. case rSI:
  465. res.regi = INDEX_BX_SI; break;
  466. case rUNDEF:
  467. res.regi = INDEX_BX; break;
  468. default:
  469. assert(false);
  470. }
  471. break;
  472. default:
  473. assert(false);
  474. }
  475. assert(index_reg==rUNDEF);
  476. }
  477. assert(from.scale==0);
  478. if(from.index.id)
  479. {
  480. assert(false);
  481. }
  482. res.off = from.disp;
  483. return res;
  484. }
  485. LLOperand convertOperand(const x86_op_t &from)
  486. {
  487. LLOperand res;
  488. switch(from.type)
  489. {
  490. case op_unused:
  491. break;
  492. case op_register:
  493. res.regi = convertRegister(from.data.reg); break;
  494. case op_immediate:
  495. res.opz = from.data.sdword;
  496. case op_expression:
  497. res = convertExpression(from.data.expression); break;
  498. case op_offset:
  499. {
  500. LLOperand res;
  501. res.seg = rDS;
  502. res.off = from.data.offset;
  503. break;
  504. }
  505. default:
  506. fprintf(stderr,"convertOperand does not know how to convert %d\n",from.type);
  507. }
  508. if(res.isSet() && (res.seg == rUNDEF))
  509. {
  510. res.seg = rDS;
  511. }
  512. return res;
  513. }
  514. /*****************************************************************************
  515. Scans one machine instruction at offset ip in prog.Image and returns error.
  516. At the same time, fill in low-level icode details for the scanned inst.
  517. ****************************************************************************/
  518. eErrorId scan(uint32_t ip, ICODE &p)
  519. {
  520. PROG &prog(Project::get()->prog);
  521. int op;
  522. p = ICODE();
  523. p.type = LOW_LEVEL;
  524. p.ll()->label = ip; /* ip is absolute offset into image*/
  525. if (ip >= (uint32_t)prog.cbImage)
  526. {
  527. return (IP_OUT_OF_RANGE);
  528. }
  529. int cnt=disassembleOneLibDisasm(ip,p.insn);
  530. if(cnt)
  531. {
  532. convertUsedFlags(p.insn,p);
  533. convertPrefix(p.insn.prefix,p);
  534. }
  535. SegPrefix = RepPrefix = 0;
  536. pInst = prog.image() + ip;
  537. pIcode = &p;
  538. do
  539. {
  540. op = *pInst++; /* First state - trivial */
  541. /* Convert to Icode.opcode */
  542. p.ll()->set(stateTable[op].opcode,stateTable[op].flg & ICODEMASK);
  543. (*stateTable[op].state1)(op); /* Second state */
  544. (*stateTable[op].state2)(op); /* Third state */
  545. } while (stateTable[op].state1 == prefix); /* Loop if prefix */
  546. if(p.insn.group == x86_insn_t::insn_controlflow)
  547. {
  548. if(p.insn.x86_get_branch_target())
  549. decodeBranchTgt(p.insn);
  550. }
  551. // LLOperand conv = convertOperand(*p.insn.get_dest());
  552. // assert(conv==p.ll()->dst);
  553. if (p.ll()->getOpcode())
  554. {
  555. /* Save bytes of image used */
  556. p.ll()->numBytes = (uint8_t)((pInst - prog.image()) - ip);
  557. if(p.insn.is_valid())
  558. assert(p.ll()->numBytes == p.insn.size);
  559. p.ll()->numBytes = p.insn.size;
  560. return ((SegPrefix)? FUNNY_SEGOVR: /* Seg. Override invalid */
  561. (RepPrefix ? FUNNY_REP: NO_ERR));/* REP prefix invalid */
  562. }
  563. /* Else opcode error */
  564. return ((stateTable[op].flg & OP386)? INVALID_386OP: INVALID_OPCODE);
  565. }
  566. /***************************************************************************
  567. relocItem - returns true if uint16_t pointed at is in relocation table
  568. **************************************************************************/
  569. static bool relocItem(const uint8_t *p)
  570. {
  571. PROG &prog(Project::get()->prog);
  572. int i;
  573. uint32_t off = p - prog.image();
  574. for (i = 0; i < prog.cReloc; i++)
  575. if (prog.relocTable[i] == off)
  576. return true;
  577. return false;
  578. }
  579. /***************************************************************************
  580. getWord - returns next uint16_t from image
  581. **************************************************************************/
  582. static uint16_t getWord(void)
  583. {
  584. uint16_t w = LH(pInst);
  585. pInst += 2;
  586. return w;
  587. }
  588. /****************************************************************************
  589. signex - returns uint8_t sign extended to int
  590. ***************************************************************************/
  591. static int signex(uint8_t b)
  592. {
  593. long s = b;
  594. return ((b & 0x80)? (int)(0xFFFFFF00 | s): (int)s);
  595. }
  596. /****************************************************************************
  597. * setAddress - Updates the source or destination field for the current
  598. * icode, based on fdst and the TO_REG flag.
  599. * Note: fdst == true is for the r/m part of the field (dest, unless TO_REG)
  600. * fdst == false is for reg part of the field
  601. ***************************************************************************/
  602. static void setAddress(int i, bool fdst, uint16_t seg, int16_t reg, uint16_t off)
  603. {
  604. LLOperand *pm;
  605. /* If not to register (i.e. to r/m), and talking about r/m, then this is dest */
  606. pm = (!(stateTable[i].flg & TO_REG) == fdst) ?
  607. &pIcode->ll()->m_dst : &pIcode->ll()->src();
  608. /* Set segment. A later procedure (lookupAddr in proclist.c) will
  609. * provide the value of this segment in the field segValue. */
  610. if (seg) /* segment override */
  611. {
  612. pm->seg = pm->segOver = (eReg)seg;
  613. }
  614. else
  615. { /* no override, check indexed register */
  616. if ((reg >= INDEX_BX_SI) && (reg == INDEX_BP_SI || reg == INDEX_BP_DI || reg == INDEX_BP))
  617. {
  618. pm->seg = rSS; /* indexed on bp */
  619. }
  620. else
  621. {
  622. pm->seg = rDS; /* any other indexed reg */
  623. }
  624. }
  625. pm->regi = (eReg)reg;
  626. pm->off = (int16_t)off;
  627. if (reg && reg < INDEX_BX_SI && (stateTable[i].flg & B))
  628. {
  629. pm->regi = Machine_X86::subRegL(pm->regi);
  630. }
  631. if (seg) /* So we can catch invalid use of segment overrides */
  632. {
  633. SegPrefix = 0;
  634. }
  635. }
  636. /****************************************************************************
  637. rm - Decodes r/m part of modrm uint8_t for dst (unless TO_REG) part of icode
  638. ***************************************************************************/
  639. static void rm(int i)
  640. {
  641. uint8_t mod = *pInst >> 6;
  642. uint8_t rm = *pInst++ & 7;
  643. switch (mod) {
  644. case 0: /* No disp unless rm == 6 */
  645. if (rm == 6) {
  646. setAddress(i, true, SegPrefix, 0, getWord());
  647. pIcode->ll()->setFlags(WORD_OFF);
  648. }
  649. else
  650. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, 0);
  651. break;
  652. case 1: /* 1 uint8_t disp */
  653. setAddress(i, true, SegPrefix, rm+INDEX_BX_SI, (uint16_t)signex(*pInst++));
  654. break;
  655. case 2: /* 2 uint8_t disp */
  656. setAddress(i, true, SegPrefix, rm + INDEX_BX_SI, getWord());
  657. pIcode->ll()->setFlags(WORD_OFF);
  658. break;
  659. case 3: /* reg */
  660. setAddress(i, true, 0, rm + rAX, 0);
  661. break;
  662. }
  663. //pIcode->insn.get_dest()->
  664. if ((stateTable[i].flg & NSP) && (pIcode->ll()->src().getReg2()==rSP ||
  665. pIcode->ll()->m_dst.getReg2()==rSP))
  666. pIcode->ll()->setFlags(NOT_HLL);
  667. }
  668. /****************************************************************************
  669. modrm - Sets up src and dst from modrm uint8_t
  670. ***************************************************************************/
  671. static void modrm(int i)
  672. {
  673. setAddress(i, false, 0, REG(*pInst) + rAX, 0);
  674. rm(i);
  675. }
  676. /****************************************************************************
  677. segrm - seg encoded as reg of modrm
  678. ****************************************************************************/
  679. static void segrm(int i)
  680. {
  681. int reg = REG(*pInst) + rES;
  682. if (reg > rDS || (reg == rCS && (stateTable[i].flg & TO_REG)))
  683. pIcode->ll()->setOpcode((llIcode)0); // setCBW because it has that index
  684. else {
  685. setAddress(i, false, 0, (int16_t)reg, 0);
  686. rm(i);
  687. }
  688. }
  689. /****************************************************************************
  690. regop - src/dst reg encoded as low 3 bits of opcode
  691. ***************************************************************************/
  692. static void regop(int i)
  693. {
  694. setAddress(i, false, 0, ((int16_t)i & 7) + rAX, 0);
  695. pIcode->ll()->replaceDst(pIcode->ll()->src());
  696. }
  697. /*****************************************************************************
  698. segop - seg encoded in middle of opcode
  699. *****************************************************************************/
  700. static void segop(int i)
  701. {
  702. setAddress(i, true, 0, (((int16_t)i & 0x18) >> 3) + rES, 0);
  703. }
  704. /****************************************************************************
  705. axImp - Plugs an implied AX dst
  706. ***************************************************************************/
  707. static void axImp(int i)
  708. {
  709. setAddress(i, true, 0, rAX, 0);
  710. }
  711. /* Implied AX source */
  712. static void axSrcIm (int )
  713. {
  714. pIcode->ll()->replaceSrc(rAX);//src.regi = rAX;
  715. }
  716. /* Implied AL source */
  717. static void alImp (int )
  718. {
  719. pIcode->ll()->replaceSrc(rAL);//src.regi = rAL;
  720. }
  721. /*****************************************************************************
  722. memImp - Plugs implied src memory operand with any segment override
  723. ****************************************************************************/
  724. static void memImp(int i)
  725. {
  726. setAddress(i, false, SegPrefix, 0, 0);
  727. }
  728. /****************************************************************************
  729. memOnly - Instruction is not valid if modrm refers to register (i.e. mod == 3)
  730. ***************************************************************************/
  731. static void memOnly(int )
  732. {
  733. if ((*pInst & 0xC0) == 0xC0)
  734. pIcode->ll()->setOpcode((llIcode)0);
  735. }
  736. /****************************************************************************
  737. memReg0 - modrm for 'memOnly' and Reg field must also be 0
  738. ****************************************************************************/
  739. static void memReg0(int i)
  740. {
  741. if (REG(*pInst) || (*pInst & 0xC0) == 0xC0)
  742. pIcode->ll()->setOpcode((llIcode)0);
  743. else
  744. rm(i);
  745. }
  746. /***************************************************************************
  747. immed - Sets up dst and opcode from modrm uint8_t
  748. **************************************************************************/
  749. static void immed(int i)
  750. {
  751. static llIcode immedTable[8] = {iADD, iOR, iADC, iSBB, iAND, iSUB, iXOR, iCMP};
  752. pIcode->ll()->setOpcode(immedTable[REG(*pInst)]) ;
  753. rm(i);
  754. if (pIcode->ll()->getOpcode() == iADD || pIcode->ll()->getOpcode() == iSUB)
  755. pIcode->ll()->clrFlags(NOT_HLL); /* Allow ADD/SUB SP, immed */
  756. }
  757. /****************************************************************************
  758. shift - Sets up dst and opcode from modrm uint8_t
  759. ***************************************************************************/
  760. static void shift(int i)
  761. {
  762. static llIcode shiftTable[8] =
  763. {
  764. (llIcode)iROL, (llIcode)iROR, (llIcode)iRCL, (llIcode)iRCR,
  765. (llIcode)iSHL, (llIcode)iSHR, (llIcode)0, (llIcode)iSAR};
  766. pIcode->ll()->setOpcode(shiftTable[REG(*pInst)]);
  767. rm(i);
  768. pIcode->ll()->replaceSrc(rCL); //src.regi =
  769. }
  770. /****************************************************************************
  771. trans - Sets up dst and opcode from modrm uint8_t
  772. ***************************************************************************/
  773. static void trans(int i)
  774. {
  775. static llIcode transTable[8] =
  776. {
  777. (llIcode)iINC, (llIcode)iDEC, (llIcode)iCALL, (llIcode)iCALLF,
  778. (llIcode)iJMP, (llIcode)iJMPF,(llIcode)iPUSH, (llIcode)0
  779. };
  780. LLInst *ll = pIcode->ll();
  781. if ((uint8_t)REG(*pInst) < 2 || !(stateTable[i].flg & B)) { /* INC & DEC */
  782. ll->setOpcode(transTable[REG(*pInst)]); /* valid on bytes */
  783. rm(i);
  784. ll->replaceSrc( pIcode->ll()->m_dst );
  785. if (ll->match(iJMP) || ll->match(iCALL) || ll->match(iCALLF))
  786. ll->setFlags(NO_OPS);
  787. else if (ll->match(iINC) || ll->match(iPUSH) || ll->match(iDEC))
  788. ll->setFlags(NO_SRC);
  789. }
  790. }
  791. /****************************************************************************
  792. arith - Sets up dst and opcode from modrm uint8_t
  793. ****************************************************************************/
  794. static void arith(int i)
  795. {
  796. uint8_t opcode;
  797. static llIcode arithTable[8] =
  798. {
  799. iTEST, (llIcode)0, iNOT, iNEG,
  800. iMUL , iIMUL, iDIV, iIDIV
  801. };
  802. opcode = arithTable[REG(*pInst)];
  803. pIcode->ll()->setOpcode((llIcode)opcode);
  804. rm(i);
  805. if (opcode == iTEST)
  806. {
  807. if (stateTable[i].flg & B)
  808. data1(i);
  809. else
  810. data2(i);
  811. }
  812. else if (!(opcode == iNOT || opcode == iNEG))
  813. {
  814. pIcode->ll()->replaceSrc( pIcode->ll()->m_dst );
  815. setAddress(i, true, 0, rAX, 0); /* dst = AX */
  816. }
  817. else if (opcode == iNEG || opcode == iNOT)
  818. pIcode->ll()->setFlags(NO_SRC);
  819. if ((opcode == iDIV) || (opcode == iIDIV))
  820. {
  821. if ( not pIcode->ll()->testFlags(B) )
  822. pIcode->ll()->setFlags(IM_TMP_DST);
  823. }
  824. }
  825. /*****************************************************************************
  826. data1 - Sets up immed from 1 uint8_t data
  827. *****************************************************************************/
  828. static void data1(int i)
  829. {
  830. pIcode->ll()->replaceSrc(LLOperand::CreateImm2((stateTable[i].flg & S_EXT)? signex(*pInst++): *pInst++));
  831. pIcode->ll()->setFlags(I);
  832. }
  833. /*****************************************************************************
  834. data2 - Sets up immed from 2 uint8_t data
  835. ****************************************************************************/
  836. static void data2(int )
  837. {
  838. if (relocItem(pInst))
  839. pIcode->ll()->setFlags(SEG_IMMED);
  840. /* ENTER is a special case, it does not take a destination operand,
  841. * but this field is being used as the number of bytes to allocate
  842. * on the stack. The procedure level is stored in the immediate
  843. * field. There is no source operand; therefore, the flag flg is
  844. * set to NO_OPS. */
  845. if (pIcode->ll()->getOpcode() == iENTER)
  846. {
  847. pIcode->ll()->m_dst.off = getWord();
  848. pIcode->ll()->setFlags(NO_OPS);
  849. }
  850. else
  851. pIcode->ll()->replaceSrc(getWord());
  852. pIcode->ll()->setFlags(I);
  853. }
  854. /****************************************************************************
  855. dispM - 2 uint8_t offset without modrm (== mod 0, rm 6) (Note:TO_REG bits are
  856. reversed)
  857. ****************************************************************************/
  858. static void dispM(int i)
  859. {
  860. setAddress(i, false, SegPrefix, 0, getWord());
  861. }
  862. /****************************************************************************
  863. dispN - 2 uint8_t disp as immed relative to ip
  864. ****************************************************************************/
  865. static void dispN(int )
  866. {
  867. //PROG &prog(Project::get()->prog);
  868. /*long off = (short)*/getWord(); /* Signed displacement */
  869. /* Note: the result of the subtraction could be between 32k and 64k, and
  870. still be positive; it is an offset from prog.Image. So this must be
  871. treated as unsigned */
  872. // decodeBranchTgt();
  873. }
  874. /***************************************************************************
  875. dispS - 1 byte disp as immed relative to ip
  876. ***************************************************************************/
  877. static void dispS(int )
  878. {
  879. /*long off =*/ signex(*pInst++); /* Signed displacement */
  880. // decodeBranchTgt();
  881. }
  882. /****************************************************************************
  883. dispF - 4 byte disp as immed 20-bit target address
  884. ***************************************************************************/
  885. static void dispF(int )
  886. {
  887. /*off = */(unsigned)getWord();
  888. /*seg = */(unsigned)getWord();
  889. // decodeBranchTgt();
  890. }
  891. /****************************************************************************
  892. prefix - picks up prefix uint8_t for following instruction (LOCK is ignored
  893. on purpose)
  894. ****************************************************************************/
  895. static void prefix(int )
  896. {
  897. if (pIcode->ll()->getOpcode() == iREPE || pIcode->ll()->getOpcode() == iREPNE)
  898. RepPrefix = pIcode->ll()->getOpcode();
  899. else
  900. SegPrefix = pIcode->ll()->getOpcode();
  901. }
  902. inline void BumpOpcode(LLInst &ll)
  903. {
  904. llIcode ic((llIcode)ll.getOpcode());
  905. ic = (llIcode)(((int)ic)+1); // Bump this icode via the int type
  906. ll.setOpcode(ic);
  907. }
  908. /*****************************************************************************
  909. strop - checks RepPrefix and converts string instructions accordingly
  910. *****************************************************************************/
  911. static void strop(int )
  912. {
  913. if (RepPrefix)
  914. {
  915. if ( pIcode->ll()->match(iCMPS) || pIcode->ll()->match(iSCAS) )
  916. {
  917. if(pIcode->insn.prefix & insn_rep_zero)
  918. {
  919. BumpOpcode(*pIcode->ll()); // iCMPS -> iREPE_CMPS
  920. BumpOpcode(*pIcode->ll());
  921. }
  922. else if(pIcode->insn.prefix & insn_rep_notzero)
  923. BumpOpcode(*pIcode->ll()); // iX -> iREPNE_X
  924. }
  925. else
  926. if(pIcode->insn.prefix & insn_rep_zero)
  927. BumpOpcode(*pIcode->ll()); // iX -> iREPE_X
  928. if (pIcode->ll()->match(iREP_LODS) )
  929. pIcode->ll()->setFlags(NOT_HLL);
  930. RepPrefix = 0;
  931. }
  932. }
  933. /***************************************************************************
  934. escop - esc operands
  935. ***************************************************************************/
  936. static void escop(int i)
  937. {
  938. pIcode->ll()->replaceSrc(REG(*pInst) + (uint32_t)((i & 7) << 3));
  939. pIcode->ll()->setFlags(I);
  940. rm(i);
  941. }
  942. /****************************************************************************
  943. const1
  944. ****************************************************************************/
  945. static void const1(int )
  946. {
  947. pIcode->ll()->replaceSrc(1);
  948. pIcode->ll()->setFlags(I);
  949. }
  950. /*****************************************************************************
  951. const3
  952. ****************************************************************************/
  953. static void const3(int )
  954. {
  955. pIcode->ll()->replaceSrc(3);
  956. pIcode->ll()->setFlags(I);
  957. }
  958. /****************************************************************************
  959. none1
  960. ****************************************************************************/
  961. static void none1(int )
  962. {
  963. }
  964. /****************************************************************************
  965. none2 - Sets the NO_OPS flag if the operand is immediate
  966. ****************************************************************************/
  967. static void none2(int )
  968. {
  969. if ( pIcode->ll()->testFlags(I) )
  970. pIcode->ll()->setFlags(NO_OPS);
  971. }
  972. /****************************************************************************
  973. Checks for int 34 to int 3B - if so, converts to ESC nn instruction
  974. ****************************************************************************/
  975. static void checkInt(int )
  976. {
  977. uint16_t wOp = (uint16_t) pIcode->ll()->src().getImm2();
  978. if ((wOp >= 0x34) && (wOp <= 0x3B))
  979. {
  980. /* This is a Borland/Microsoft floating point emulation instruction.
  981. Treat as if it is an ESC opcode */
  982. pIcode->ll()->replaceSrc(wOp - 0x34);
  983. pIcode->ll()->set(iESC,FLOAT_OP);
  984. escop(wOp - 0x34 + 0xD8);
  985. }
  986. }