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@@ -0,0 +1,3206 @@
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+# IA32 OPCODE MAP
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+# Tab-delimited file of Intel Opcode Tables
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+
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+# Each table begins with the line
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+# ^TABLE $NAME\tindex $INDEX\ttype $TYPE\tshift $SHIFT\tmask $MASK\tminlim $MIN\tmaxlim $MAX\tname $NAME
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+# and ends with the line
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+# END TABLE
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+
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+# Each instruction is formed of the line
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+# ^INSN $TABLE\t$MFLAG\t$DFLAG\t$SFLAG\t$AFLAG\t$CPU
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+# \t$MNEM\t$DEST\t$SRC\t$AUX\t$EFLAGS\t$COMMENT
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+# Note that this is a single line: the newline in the above is for clarity.
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+# The fields are:
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+# TABLE : index of next lookup table if appropriate
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+# MFLAG : mnemonic (instruction) flags
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+# DFLAG : destination (1st) operand flags
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+# SFLAG : source (2nd) operand flags
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+# AFLAG : aux (3rd) operand flags
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+# CPU : minimum CPU version supporting this insn
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+# MNEM : ASCII mnemonic
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+# DEST : hard-coded destination operand
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+# SRC : hard-coded source operand
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+# AUX : hard-coded aux operand
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+# EFLAGS : cpu flags effected by instruction
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+# IMPLICIT: implicit operands
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+# CMT : comment : usually the byte or index in the table
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+
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+
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+# Obviously blank lines and lines beginning with '#' are ignored.
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+PREFIX ia32
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+
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+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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+#+++++++++++++++++++---------------------------------++++++++++++++++++++
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+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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+
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+TABLE tbl_Main tbl_opcode shift 0 mask 255 minlim 0 maxlim 255 "One-byte Opcodes"
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+#______________________________________________________________________________
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+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_ADD ADDRMETH_G | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_ADD ADDRMETH_G | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_ADD ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_ADD ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 0 0 0 0 33
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+INSN 0 INS_POP ADDRMETH_RS | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 0 0 0 0 33
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+INSN 0 INS_OR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_OR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_OR ADDRMETH_G | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_OR ADDRMETH_G | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_OR ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_OR ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 1 0 0 0 33
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+INSN idx_0F 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
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+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_ADD ADDRMETH_G | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_ADD ADDRMETH_G | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_ADD ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_ADD ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 2 0 0 0 33
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+INSN 0 INS_POP ADDRMETH_RS | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 2 0 0 0 33
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+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_SUB ADDRMETH_G | OPTYPE_b | OP_W | OP_SIGNED | OP_R ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_SUB ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_SUB ADDRMETH_RR | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_SUB ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
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+INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 3 0 0 0 33
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+INSN 0 INS_POP ADDRMETH_RS | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 3 0 0 0 33
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+INSN 0 INS_AND ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_AND ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_AND ADDRMETH_G | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_AND ADDRMETH_G | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_AND ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_AND ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_NOTE_PREFIX | PREFIX_ES ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
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+INSN 0 INS_BCDCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "daa" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_CARRY|INS_SET_PARITY|INS_TEST_CARRY 12
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+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_SUB ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_SUB ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_SUB ADDRMETH_RR | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_SUB ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_NOTE_PREFIX | PREFIX_CS | PREFIX_NOTTAKEN ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
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+INSN 0 INS_BCDCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "das" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_CARRY|INS_SET_PARITY|INS_TEST_CARRY 0
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+INSN 0 INS_XOR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_XOR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_XOR ADDRMETH_G | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_XOR ADDRMETH_G | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_XOR ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_XOR ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_NOTE_PREFIX | PREFIX_SS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
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+INSN 0 INS_BCDCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "aaa" 0 0 0 INS_SET_CARRY 1
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+INSN 0 INS_CMP ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_CMP ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_CMP ADDRMETH_G | OPTYPE_b | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_CMP ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_CMP ADDRMETH_RR | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_CMP ADDRMETH_RR | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0
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+INSN 0 INS_NOTE_PREFIX | PREFIX_DS | PREFIX_TAKEN ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
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+INSN 0 INS_BCDCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "aas" 0 0 0 INS_SET_CARRY 0
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+INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 1 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 2 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 3 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 4 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 5 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 6 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_INC ADDRMETH_RR | OPTYPE_v | OP_R | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 7 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 1 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 2 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 3 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 4 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 5 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 6 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_DEC ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 7 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
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+INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 0 0 0 0 33
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+INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 1 0 0 0 33
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+INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 2 0 0 0 33
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+INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 3 0 0 0 33
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+INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 4 0 0 0 33
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+INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 5 0 0 0 33
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+INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 6 0 0 0 33
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+INSN 0 INS_PUSH ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 7 0 0 0 33
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+INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 0 0 0 0 33
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+INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 1 0 0 0 33
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+INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 2 0 0 0 33
|
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+INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 3 0 0 0 33
|
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+INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 4 0 0 0 33
|
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+INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 5 0 0 0 33
|
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+INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 6 0 0 0 33
|
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+INSN 0 INS_POP ADDRMETH_RR | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 7 0 0 0 33
|
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+INSN 0 INS_PUSHREGS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "pushad" 0 0 0 0 36
|
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+INSN 0 INS_POPREGS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "popad" 0 0 0 0 34
|
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+INSN 0 INS_BOUNDS ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_M | OPTYPE_a | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "bound" 0 0 0 0 0
|
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+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_R ADDRMETH_G | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "arpl" 0 0 0 INS_SET_ZERO 0
|
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+INSN 0 INS_NOTE_PREFIX | PREFIX_FS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN 0 INS_NOTE_PREFIX | PREFIX_GS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN idx_66 INS_NOTE_PREFIX | PREFIX_OP_SIZE ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN 0 INS_NOTE_PREFIX | PREFIX_ADDR_SIZE ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN 0 INS_PUSH ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 0 0 0 0 33
|
|
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+INSN 0 INS_MUL ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R cpu_80386 | isa_GP "imul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 0
|
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+INSN 0 INS_PUSH ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 0 0 0 0 33
|
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+INSN 0 INS_MUL ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R cpu_80386 | isa_GP "imul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 0
|
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|
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+INSN 0 INS_IN ADDRMETH_Y | OPTYPE_b | OP_W ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "insb" 0 2 0 0 0
|
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|
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+INSN 0 INS_IN ADDRMETH_Y | OPTYPE_v | OP_W ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "insd" 0 2 0 0 0
|
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+INSN 0 INS_OUT ADDRMETH_RR | OPTYPE_b | OP_R ADDRMETH_X | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "outsb" 2 0 0 0 0
|
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+INSN 0 INS_OUT ADDRMETH_RR | OPTYPE_v | OP_R ADDRMETH_X | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "outsb" 2 0 0 0 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jo" 0 0 0 INS_TEST_OFLOW 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jno" 0 0 0 INS_TEST_NOFLOW 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jc" 0 0 0 INS_TEST_CARRY 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jnc" 0 0 0 INS_TEST_NCARRY 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jz" 0 0 0 INS_TEST_ZERO 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jnz" 0 0 0 INS_TEST_NZERO 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jbe" 0 0 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "ja" 0 0 0 INS_TEST_NCARRY|INS_TEST_NZERO 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "js" 0 0 0 INS_TEST_SIGN 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jns" 0 0 0 INS_TEST_NSIGN 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jpe" 0 0 0 INS_TEST_PARITY 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jpo" 0 0 0 INS_TEST_NPARITY 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jl" 0 0 0 INS_TEST_SFNEOF 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jge" 0 0 0 INS_TEST_SFEQOF 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jle" 0 0 0 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jg" 0 0 0 INS_TEST_NZERO|INS_TEST_SFEQOF 0
|
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+INSN idx_80 0 ADDRMETH_E | OPTYPE_b ADDRMETH_I | OPTYPE_b ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN idx_81 0 ADDRMETH_E | OPTYPE_v ADDRMETH_I | OPTYPE_v ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN idx_82 0 ADDRMETH_E | OPTYPE_b ADDRMETH_I | OPTYPE_b ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN idx_83 0 ADDRMETH_E | OPTYPE_v ADDRMETH_I | OPTYPE_b ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN 0 INS_TEST ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0
|
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+INSN 0 INS_TEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0
|
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+INSN 0 INS_XCHG ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 0 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_E | OPTYPE_b | OP_W ADDRMETH_G | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_E | OPTYPE_v | OP_W ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_b | OP_W ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_E | OPTYPE_w | OP_W ADDRMETH_S | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_m | OP_R ARG_NONE cpu_80386 | isa_GP "lea" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_S | OPTYPE_w | OP_W ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
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+INSN 0 INS_POP ADDRMETH_E | OPTYPE_v | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 0 0 0 0 33
|
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+INSN 0 INS_NOP ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "nop" 0 0 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 1 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 2 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 3 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 4 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 5 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 6 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ARG_NONE cpu_80386 | isa_GP "xchg" 0 7 0 0 0
|
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+INSN 0 INS_SZCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "cwde" 0 0 0 0 5
|
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+INSN 0 INS_SZCONV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "cdq" 0 0 0 0 11
|
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+INSN 0 INS_CALL ADDRMETH_A | OPTYPE_p | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "callf" 0 0 0 0 0
|
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+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "wait" 0 0 0 0 0
|
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+INSN 0 INS_PUSHFLAGS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "pushfd" 0 0 0 0 37
|
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+INSN 0 INS_POPFLAGS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "popfd" 0 0 0 0 35
|
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+INSN 0 INS_MOV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "sahf" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 43
|
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+INSN 0 INS_MOV ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "lahf" 0 0 0 0 24
|
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_O | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_O | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_O | OPTYPE_b | OP_W ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_O | OPTYPE_v | OP_W ADDRMETH_RR | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
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+INSN 0 INS_STRMOV ADDRMETH_Y | OPTYPE_b | OP_W ADDRMETH_X | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "movsb" 0 0 0 0 0
|
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+INSN 0 INS_STRMOV ADDRMETH_Y | OPTYPE_v | OP_W ADDRMETH_X | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "movsd" 0 0 0 0 0
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+INSN 0 INS_STRCMP ADDRMETH_Y | OPTYPE_b | OP_R ADDRMETH_X | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "cmpsb" 0 0 0 0 0
|
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+INSN 0 INS_STRCMP ADDRMETH_X | OPTYPE_v | OP_R ADDRMETH_Y | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "cmpsd" 0 0 0 0 0
|
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+INSN 0 INS_TEST ADDRMETH_RR | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0
|
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+INSN 0 INS_TEST ADDRMETH_RR | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0
|
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+INSN 0 INS_STRSTOR ADDRMETH_Y | OPTYPE_b | OP_W ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "stosb" 0 0 0 0 0
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+INSN 0 INS_STRSTOR ADDRMETH_Y | OPTYPE_v | OP_W ADDRMETH_RR | OPTYPE_v |OP_R ARG_NONE cpu_80386 | isa_GP "stosd" 0 0 0 0 0
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+INSN 0 INS_STRLOAD ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_X| OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "lodsb" 0 0 0 0 0
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+INSN 0 INS_STRLOAD ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_X| OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "lodsd" 0 0 0 0 0
|
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+INSN 0 INS_STRCMP ADDRMETH_RR | OPTYPE_b | OP_R ADDRMETH_Y | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "scasb" 0 0 0 0 0
|
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+INSN 0 INS_STRCMP ADDRMETH_RR | OPTYPE_v | OP_R ADDRMETH_Y | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "scasd" 0 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 1 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 2 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 3 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 4 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 5 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 6 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 7 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 1 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 2 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 3 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 4 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 5 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 6 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 7 0 0 0 0
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+INSN idx_C0 0 ADDRMETH_E | OPTYPE_b ADDRMETH_I | OPTYPE_b ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN idx_C1 0 ADDRMETH_E | OPTYPE_v ADDRMETH_I | OPTYPE_b ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN 0 INS_RET ADDRMETH_I | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "ret" 0 0 0 0 3
|
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+INSN 0 INS_RET ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "ret" 0 0 0 0 3
|
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_p | OP_R ARG_NONE cpu_80386 | isa_GP "les" 0 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_p | OP_R ARG_NONE cpu_80386 | isa_GP "lds" 0 0 0 0 0
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+INSN idx_C6 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
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+INSN idx_C7 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN 0 INS_ENTER ADDRMETH_I | OPTYPE_w | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "enter" 0 0 0 0 15
|
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+INSN 0 INS_LEAVE ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "leave" 0 0 0 0 26
|
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+INSN 0 INS_RET ADDRMETH_I | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "retf" 0 0 0 0 3
|
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+INSN 0 INS_RET ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "retf" 0 0 0 0 3
|
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+INSN 0 INS_DEBUG ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "int3" 0 0 0 0 0
|
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+INSN 0 INS_TRAP ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "int" 0 0 0 0 0
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+INSN 0 INS_OFLOW ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "into" 0 0 0 INS_TEST_OFLOW 0
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|
|
+INSN 0 INS_TRET ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "iret" 0 0 0 INS_SET_ALL|INS_SET_DIR 0
|
|
|
|
+INSN idx_D0 0 ADDRMETH_E | OPTYPE_b ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 1 0 0 0
|
|
|
|
+INSN idx_D1 0 ADDRMETH_E | OPTYPE_v ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 1 0 0 0
|
|
|
|
+INSN idx_D2 0 ADDRMETH_E | OPTYPE_b ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 1 0 0 0
|
|
|
|
+INSN idx_D3 0 ADDRMETH_E | OPTYPE_v ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 1 0 0 0
|
|
|
|
+INSN 0 INS_BCDCONV ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "aam" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
|
|
|
|
+INSN 0 INS_BCDCONV ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "aad" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 2
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_XLAT ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "xlat" 0 0 0 0 53
|
|
|
|
+INSN idx_D8 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_D9 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_DA 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_DB 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_DC 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_DD 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_DE 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_DF 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "loopnz" 0 0 0 INS_TEST_NZERO 31
|
|
|
|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "loopz" 0 0 0 INS_TEST_ZERO 31
|
|
|
|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "loop" 0 0 0 0 31
|
|
|
|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_b | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jcxz" 0 0 0 0 31
|
|
|
|
+INSN 0 INS_IN ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "in" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_IN ADDRMETH_RR | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "in" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OUT ADDRMETH_I | OPTYPE_b | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "out" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OUT ADDRMETH_I | OPTYPE_b | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "out" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_CALL ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "call" 0 0 0 0 3
|
|
|
|
+INSN 0 INS_BRANCH ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jmp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_BRANCH ADDRMETH_A | OPTYPE_p | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jmpf" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_BRANCH ADDRMETH_J | OPTYPE_b | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jmp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_IN ADDRMETH_RR | OPTYPE_b| OP_W ADDRMETH_RR | OPTYPE_w| OP_R ARG_NONE cpu_80386 | isa_GP "in" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_IN ADDRMETH_RR | OPTYPE_v | OP_W ADDRMETH_RR | OPTYPE_w| OP_R ARG_NONE cpu_80386 | isa_GP "in" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_OUT ADDRMETH_RR | OPTYPE_w| OP_R ADDRMETH_RR | OPTYPE_b| OP_R ARG_NONE cpu_80386 | isa_GP "out" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_OUT ADDRMETH_RR | OPTYPE_w| OP_R ADDRMETH_RR | OPTYPE_v| OP_R ARG_NONE cpu_80386 | isa_GP "out" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_NOTE_PREFIX | PREFIX_LOCK ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_F2 INS_NOTE_PREFIX | PREFIX_REPNZ ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_F3 INS_NOTE_PREFIX | PREFIX_REPZ ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_HALT ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "hlt" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_TOGCF ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "cmc" 0 0 0 INS_SET_CARRY 0
|
|
|
|
+INSN idx_F6 0 ADDRMETH_E | OPTYPE_b ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_F7 0 ADDRMETH_E | OPTYPE_v ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_CLEARCF ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "clc" 0 0 0 INS_SET_NCARRY 0
|
|
|
|
+INSN 0 INS_SETCF ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "stc" 0 0 0 INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "cli" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "sti" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_CLEARDF ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "cld" 0 0 0 INS_SET_NDIR 0
|
|
|
|
+INSN 0 INS_SETDF ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "std" 0 0 0 INS_SET_DIR 0
|
|
|
|
+INSN idx_FE 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_FF 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_66 tbl_prefix shift 0 mask 255 minlim 15 maxlim 15 "SIMD 66 one-byte Opcodes"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN idx_660F 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+# Table truncated
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_F2 tbl_prefix shift 0 mask 255 minlim 15 maxlim 15 "SIMD F2 one-byte Opcodes"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN idx_F20F 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+# Table truncated
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+# TODO
|
|
|
|
+# lookup: if ( >= minlin && <= maxlim ) idx -= minlim;
|
|
|
|
+# 0x90 == 1001 0000 ; val >> 4 ; 1000 - 1001
|
|
|
|
+TABLE tbl_F3 tbl_prefix shift 0 mask 255 minlim 15 maxlim 144 "SIMD F3 one-byte Opcodes"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN idx_F30F 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "pause" 0 0 0 0 0
|
|
|
|
+# Table truncated
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_0F tbl_opcode shift 0 mask 255 minlim 0 maxlim 255 "Two-byte Opcodes"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN idx_0F00 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_0F01 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "lar" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "lsl" 0 0 0 INS_SET_ZERO 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_CLTS ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "clts" 0 0 0 0 6
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80486 | isa_GP "invd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80486 | isa_GP "wbinvd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ARG_NONE ARG_NONE ARG_NONE cpu_PENTPRO | isa_GP "ud2" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "prefetchw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "femms" 0 0 0 0 0
|
|
|
|
+INSN idx_0F0F INS_NOTE_SUFFIX ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movups" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_W | OPTYPE_ps | OP_W ADDRMETH_V | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movups" 0 0 0 0 0
|
|
|
|
+INSN idx_0F12 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movlps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "unpcklps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "unpckhps" 0 0 0 0 0
|
|
|
|
+INSN idx_0F16 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_q | OP_W ADDRMETH_V | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movhps" 0 0 0 0 0
|
|
|
|
+INSN idx_0F18 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_R | OPTYPE_d | OP_W ADDRMETH_C | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_R | OPTYPE_d | OP_W ADDRMETH_D | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_C | OPTYPE_d | OP_W ADDRMETH_R | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_D | OPTYPE_d | OP_W ADDRMETH_R | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_R | OPTYPE_d | OP_W ADDRMETH_T | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_T | OPTYPE_d | OP_W ADDRMETH_R | OPTYPE_d | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movaps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_W | OPTYPE_ps | OP_W ADDRMETH_V | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movaps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "cvtpi2ps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_W | OPTYPE_ps | OP_W ADDRMETH_V | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movntps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "cvttps2pi" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "cvtps2pi" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ss | OP_W ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "ucomiss" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ss | OP_W ARG_NONE cpu_PENTIUM2 | isa_GP "comiss" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "wrmsr" 0 0 0 0 52
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "rdtsc" 0 0 0 0 40
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "rdmsr" 0 0 0 0 38
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTPRO | isa_GP "rdpmc" 0 0 0 0 39
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "sysenter" 0 0 0 0 50
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "sysexit" 0 0 0 0 51
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovo" 0 0 0 INS_TEST_OFLOW 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovno" 0 0 0 INS_TEST_NOFLOW 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovc" 0 0 0 INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovnc" 0 0 0 INS_TEST_NCARRY 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovz" 0 0 0 INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovnz" 0 0 0 INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovbe" 0 0 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmova" 0 0 0 INS_TEST_NZERO|INS_TEST_NCARRY 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovs" 0 0 0 INS_TEST_SIGN 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovns" 0 0 0 INS_TEST_NSIGN 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovp" 0 0 0 INS_TEST_PARITY 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovnp" 0 0 0 INS_TEST_NPARITY 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovl" 0 0 0 INS_TEST_SFNEOF 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovge" 0 0 0 INS_TEST_SFEQOF 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovle" 0 0 0 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_PENTPRO | isa_GP "cmovg" 0 0 0 INS_TEST_NZERO|INS_TEST_SFEQOF 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_d | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movmskps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ARITH ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "sqrtps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ARITH ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "rsqrtps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "rcpps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_AND ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "andps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_AND ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "andnps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OR ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "orps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_XOR ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "xorps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "addps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MUL ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "mulps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_pd ADDRMETH_W | OPTYPE_q ARG_NONE cpu_PENTIUM4 | isa_GP "cvtps2pd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtdq2ps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "subps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ARITH ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "minps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_DIV ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "divps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ARITH ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "maxps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpcklbw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpcklwd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpckldq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "packsswb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpgtb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpgtw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpgtd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "packuswb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpckhbw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpckhwd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "punpckhdq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "packssdw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_P | OPTYPE_d | OP_W ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "movd" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "movq" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM2 | isa_GP "pshufw" 0 0 0 0 0
|
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+INSN idx_0F71 0 ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "" 0 0 0 0 0
|
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+INSN idx_0F72 0 ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "" 0 0 0 0 0
|
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+INSN idx_0F73 0 ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpeqb" 0 0 0 0 0
|
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+INSN 0 INS_CMP ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpeqw" 0 0 0 0 0
|
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+INSN 0 INS_CMP ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pcmpeqd" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "emms" 0 0 0 0 0
|
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_E | OPTYPE_d | OP_W ADDRMETH_P | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "movd" 0 0 0 0 0
|
|
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+INSN 0 INS_MOV ADDRMETH_Q | OPTYPE_q | OP_W ADDRMETH_P | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "movq" 0 0 0 0 0
|
|
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|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jo" 0 0 0 INS_TEST_OFLOW 0
|
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jno" 0 0 0 INS_TEST_NOFLOW 0
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jc" 0 0 0 INS_TEST_CARRY 0
|
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jnc" 0 0 0 INS_TEST_NCARRY 0
|
|
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|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jz" 0 0 0 INS_TEST_ZERO 0
|
|
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|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jnz" 0 0 0 INS_TEST_NZERO 0
|
|
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jbe" 0 0 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "ja" 0 0 0 INS_TEST_NCARRY|INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "js" 0 0 0 INS_TEST_SIGN 0
|
|
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|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jns" 0 0 0 INS_TEST_NSIGN 0
|
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jpe" 0 0 0 INS_TEST_PARITY 0
|
|
|
|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jpo" 0 0 0 INS_TEST_NPARITY 0
|
|
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|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jl" 0 0 0 INS_TEST_SFNEOF 0
|
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jge" 0 0 0 INS_TEST_SFEQOF 0
|
|
|
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+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jle" 0 0 0 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 0
|
|
|
|
+INSN 0 INS_BRANCHCC ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED ARG_NONE ARG_NONE cpu_80386 | isa_GP "jg" 0 0 0 INS_TEST_NZERO|INS_TEST_SFEQOF 0
|
|
|
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+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "seto" 0 0 0 INS_TEST_OFLOW 0
|
|
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+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setno" 0 0 0 INS_TEST_OFLOW 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setc" 0 0 0 INS_TEST_CARRY 0
|
|
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|
+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setnc" 0 0 0 INS_TEST_NCARRY 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setz" 0 0 0 INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setnz" 0 0 0 INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setbe" 0 0 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
|
|
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+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "seta" 0 0 0 INS_TEST_NCARRY|INS_TEST_NZERO 0
|
|
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+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "sets" 0 0 0 INS_TEST_SIGN 0
|
|
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|
+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setns" 0 0 0 INS_TEST_NSIGN 0
|
|
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+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setpe" 0 0 0 INS_TEST_PARITY 0
|
|
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+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setpo" 0 0 0 INS_TEST_NPARITY 0
|
|
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|
+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setl" 0 0 0 INS_TEST_SFNEOF 0
|
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|
+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setge" 0 0 0 INS_TEST_SFEQOF 0
|
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+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setle" 0 0 0 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 0
|
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+INSN 0 INS_MOVCC ADDRMETH_E | OPTYPE_b | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "setg" 0 0 0 INS_TEST_NZERO|INS_TEST_SFEQOF 0
|
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+INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 4 0 0 0 33
|
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+INSN 0 INS_POP ADDRMETH_RS | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 4 0 0 0 33
|
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+INSN 0 INS_CPUID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "cpuid" 0 0 0 0 10
|
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+INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "bt" 0 0 0 INS_SET_CARRY 0
|
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+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_80386 | isa_GP "shld" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
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+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_I | OP_R | OPTYPE_b | ADDRMETH_RR cpu_80386 | isa_GP "shld" 0 0 1 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_PUSH ADDRMETH_RS | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 5 0 0 0 33
|
|
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|
+INSN 0 INS_POP ADDRMETH_RS | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "pop" 5 0 0 0 33
|
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+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "rsm" 0 0 0 INS_SET_ALL|INS_SET_DIR 42
|
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+INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "bts" 0 0 0 INS_SET_CARRY 0
|
|
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+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_80386 | isa_GP "shrd" 0 0 0 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
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+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_R ADDRMETH_RR | OP_R | OPTYPE_b cpu_80386 | isa_GP "shrd" 0 0 1 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
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+INSN idx_0FAE 0 ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "" 0 0 0 0 0
|
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+INSN 0 INS_MUL ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "imul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY
|
|
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+INSN 0 INS_XCHGCC ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_W ARG_NONE cpu_80486 | isa_GP "cmpxchg" 0 0 0 INS_SET_ALL 8
|
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+INSN 0 INS_XCHGCC ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_G | OPTYPE_v | OP_W ARG_NONE cpu_80486 | isa_GP "cmpxchg" 0 0 0 INS_SET_ALL 7
|
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_p | OP_W ARG_NONE cpu_80386 | isa_GP "lss" 0 0 0 0 0
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+INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "btr" 0 0 0 INS_SET_CARRY 0
|
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_p | OP_W ARG_NONE cpu_80386 | isa_GP "lfs" 0 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_M | OPTYPE_p | OP_W ARG_NONE cpu_80386 | isa_GP "lgs" 0 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "movzx" 0 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "movzx" 0 0 0 0 0
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_UNKNOWN ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "ud1" 0 0 0 0 0
|
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+INSN idx_0FBA 0 ARG_NONE ARG_NONE ARG_NONE cpu_80386 | isa_GP "" 0 0 0 0 0
|
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+INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_G | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "btc" 0 0 0 INS_SET_CARRY 0
|
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+INSN 0 INS_BITTEST ADDRMETH_G | OPTYPE_v | OP_R | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "bsf" 0 0 0 INS_SET_ZERO 0
|
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+INSN 0 INS_BITTEST ADDRMETH_G | OPTYPE_v | OP_R | OP_W ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "bsr" 0 0 0 INS_SET_ZERO 0
|
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "movsx" 0 0 0 0 0
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+INSN 0 INS_MOV ADDRMETH_G | OPTYPE_v | OP_W ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE cpu_80386 | isa_GP "movsx" 0 0 0 0 0
|
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+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_G | OPTYPE_b | OP_W ARG_NONE cpu_80486 | isa_GP "xadd" 0 0 0 INS_SET_ALL 0
|
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+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "xadd" 0 0 0 INS_SET_ALL 0
|
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+INSN 0 INS_CMP ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "cmpps" 0 0 0 0 0
|
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+INSN 0 INS_MOV ADDRMETH_M | OPTYPE_d | OP_W ADDRMETH_G | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movnti" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_E | OPTYPE_w | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM2 | isa_GP "pinsrw" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ADDRMETH_G | OPTYPE_d | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM2 | isa_GP "pextrw" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_ps | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM2 | isa_GP "shufps" 0 0 0 0 0
|
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+INSN 0 INS_XCHGCC ADDRMETH_M | OPTYPE_q | OP_R | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "cmpxchg8b" 0 0 0 0 9
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 0 0 0 0 0
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 1 0 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 2 0 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 3 0 0 0 0
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 4 0 0 0 0
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 5 0 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 6 0 0 0 0
|
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+INSN 0 INS_XCHG ADDRMETH_RR | OPTYPE_d | OP_W | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "bswap" 7 0 0 0 0
|
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlw" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrld" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlq" 0 0 0 0 0
|
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+INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_R | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddq" 0 0 0 0 0
|
|
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+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pmullw" 0 0 0 0 0
|
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+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ADDRMETH_G | OPTYPE_d | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pmovmskb" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubusb" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubusw" 0 0 0 0 0
|
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+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pminub" 0 0 0 0 0
|
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+INSN 0 INS_AND ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pand" 0 0 0 0 0
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+INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddusb" 0 0 0 0 0
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+INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddusw" 0 0 0 0 0
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|
|
+INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pmaxub" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_AND ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pandn" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pavgb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psraw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrad" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pavgw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MUL ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pmulhuw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MUL ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pmulhw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_W | OPTYPE_q | OP_W ADDRMETH_V | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movntq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubsb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubsw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pminsw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OR ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "por" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddsb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddsw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "pmaxsw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_XOR ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pxor" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pslld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MUL ADDRMETH_P | OPTYPE_q | OP_R | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmuludq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pmaddwd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "psadbw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_P | OPTYPE_pi | OP_W ADDRMETH_Q | OPTYPE_pi | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "maskmovq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psubd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_P | OPTYPE_q | OP_R | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "paddd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_660F tbl_prefix shift 0 mask 255 minlim 16 maxlim 255 "SIMD 66 Two-byte Opcodes"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movupd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_W | OPTYPE_pd | OP_R ADDRMETH_V | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movupd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_R ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movlpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_M | OPTYPE_q | OP_R ADDRMETH_V | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movlpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "unpcklpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "unpckhpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_R ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movhpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_M | OPTYPE_q | OP_R ADDRMETH_V | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movhpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movapd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_W | OPTYPE_pd | OP_R ADDRMETH_V | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movapd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtpi2pd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_M | OPTYPE_pd | OP_R ADDRMETH_V | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movntpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_P | OPTYPE_q | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvttpd2pi" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_P | OPTYPE_q | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtpd2pi" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "ucomisd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "comisd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movmskpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FSQRT ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "sqrtpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_AND ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "andpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_AND ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "andnpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OR ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "orpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_XOR ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "xorpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "addpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MUL ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "mulpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtpd2ps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtps2dq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "subpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "minpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "divpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "maxpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpcklbw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpcklwd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpckldq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "packsswb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpgtb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpgtw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpgtd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "packuswb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_Q | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpckhbw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_Q | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpckhwd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_Q | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpckhdq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_Q | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "packssdw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpcklqdq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "punpckhqdq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_d | OP_R ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movdqa" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "pshufd" 0 0 0 0 0
|
|
|
|
+INSN idx_660F71 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_660F72 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN idx_660F73 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpeqb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpeqw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pcmpeqd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "haddpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "hsubpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_E | OPTYPE_d | OP_R ADDRMETH_V | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_W | OPTYPE_dq | OP_R ADDRMETH_V | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movdqa" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "cmppd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_w | OP_R ADDRMETH_E | OPTYPE_w | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "pinsrw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_w | OP_R ADDRMETH_W | OPTYPE_w | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "pextrw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "shufpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "addsubpd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psrlw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psrld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psrlq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmullw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_W | OPTYPE_q | OP_R ADDRMETH_V | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmovmskb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubusb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubusw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pminub" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pand" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddusb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddusw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmaxub" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pandn" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pavgb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psraw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psrad" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pavgw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmulhuw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmulhw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvttpd2dq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_M | OPTYPE_dq | OP_R ADDRMETH_V | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movntdq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubsb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubsw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pminsw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "por" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddsb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddsw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmaxsw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pxor" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psllw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pslld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psllq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmuludq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "pmaddwd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psadbw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "maskmovdqu" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "psubq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddb" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "paddd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_F20F tbl_prefix shift 0 mask 255 minlim 16 maxlim 255 "SIMD F2 Two-byte Opcodes"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movsd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_W | OPTYPE_sd | OP_R ADDRMETH_V | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movsd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_q | OP_R ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movddup" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtsi2sd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvttsd2si" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtsd2si" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "sqrtsd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "addsd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "mulsd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtsd2ss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "subsd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "minsd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "divsd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "maxsd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "pshuflw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "haddps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "hsubps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_sd | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "cmpsd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "addsubps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_P | OPTYPE_q | OP_R ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movdq2q" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_pd | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtpd2dq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_M | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "lddqu" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_F30F tbl_prefix shift 0 mask 255 minlim 16 maxlim 255 "SIMD F3 Two-byte Opcodes"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_W | OPTYPE_ss | OP_R ADDRMETH_V | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movsldup" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ps | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movshdup" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtsi2ss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvttss2si" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_G | OPTYPE_d | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtss2si" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "sqrtss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "rsqrtss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "rcpss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "addss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "mulss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_sd | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtss2sd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvttps2dq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "subss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "minss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "divss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "maxss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movdqu" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_W | OPTYPE_dq | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "pshufhw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_q | OP_R ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_W | OPTYPE_dq | OP_R ADDRMETH_V | OPTYPE_dq | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movdqu" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_ss | OP_R ADDRMETH_W | OPTYPE_ss | OP_R ADDRMETH_I | OPTYPE_b | OP_R cpu_PENTIUM4 | isa_GP "cmpss" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_dq | OP_R ADDRMETH_Q | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movq2dq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_UNKNOWN ADDRMETH_V | OPTYPE_pd | OP_R ADDRMETH_W | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "cvtdq2pd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_0F00 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 6"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sldt" 0 0 0 0 46
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "str" 0 0 0 0 49
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lldt" 0 0 0 0 29
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "ltr" 0 0 0 0 32
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "verr" 0 0 0 INS_SET_ZERO 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "verw" 0 0 0 INS_SET_ZERO 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_0F01 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 7"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+# Mod 00
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sgdt" 0 0 0 0 44
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sidt" 0 0 0 0 45
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lgdt" 0 0 0 0 27
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lidt" 0 0 0 0 28
|
|
|
|
+INSN 0 INS_SMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "smsw" 0 0 0 0 47
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_LMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lmsw" 0 0 0 0 30
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "invlpg" 0 0 0 0 0
|
|
|
|
+# Mod 01
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sgdt" 0 0 0 0 44
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sidt" 0 0 0 0 45
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lgdt" 0 0 0 0 27
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lidt" 0 0 0 0 28
|
|
|
|
+INSN 0 INS_SMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "smsw" 0 0 0 0 47
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_LMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lmsw" 0 0 0 0 30
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "invlpg" 0 0 0 0 0
|
|
|
|
+# Mod 10
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sgdt" 0 0 0 0 44
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "sidt" 0 0 0 0 45
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lgdt" 0 0 0 0 27
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_s | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lidt" 0 0 0 0 28
|
|
|
|
+INSN 0 INS_SMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "smsw" 0 0 0 0 47
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_LMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lmsw" 0 0 0 0 30
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_80486 | isa_GP "invlpg" 0 0 0 0 0
|
|
|
|
+# Mod 11
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN idx_0F0111 0 ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "smsw" 0 0 0 0 47
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_LMSW ADDRMETH_E | OPTYPE_w | OP_W ARG_NONE ARG_NONE cpu_80386 | isa_GP "lmsw" 0 0 0 0 30
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+# This table is a weird one. In addition to the Reg field *and* the Mod field
|
|
|
|
+# of the ModR/M byte being used as an opcode extension, this insn uses the
|
|
|
|
+# R/M field as well.
|
|
|
|
+TABLE tbl_0F0111 tbl_ext_ext shift 0 mask 1 minlim 0 maxlim 1 "Monitor/MWait opcode"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "monitor" 0 0 0 0 54
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "mwait" 0 0 0 0 55
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+# TODO
|
|
|
|
+TABLE tbl_0F12 tbl_extension shift 6 mask 3 minlim 0 maxlim 3 "Movlps Opcode"
|
|
|
|
+# A semi-weird table. This insn mnemonic changes when the Mod field of the
|
|
|
|
+# ModR/M byte denotes a register.
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movlps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movlps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movlps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_R | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movhlps" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+# TODO
|
|
|
|
+TABLE tbl_0F16 tbl_extension shift 6 mask 3 minlim 0 maxlim 3 "Movhps Opcode"
|
|
|
|
+# Insn mnemonic changes when the Mod field denotes a register.
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movhps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movhps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_V | OPTYPE_q | OP_W ADDRMETH_M | OPTYPE_q | OP_R ARG_NONE cpu_PENTIUM2 | isa_GP "movhps" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_V | OPTYPE_ps | OP_R | OP_W ADDRMETH_W | OPTYPE_ps | OP_R ARG_NONE cpu_PENTIUM4 | isa_GP "movlhps" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_0F18 tbl_extension shift 3 mask 31 minlim 0 maxlim 19 "Group 16"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+# Mod 00
|
|
|
|
+INSN 0 INS_SYSTEM OP_W | OPTYPE_b | ADDRMETH_M ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetchnta" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht0" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht1" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht2" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 10
|
|
|
|
+INSN 0 INS_SYSTEM OP_W | OPTYPE_b | ADDRMETH_M ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetchnta" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht0" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht1" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht2" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 01
|
|
|
|
+INSN 0 INS_SYSTEM OP_W | OPTYPE_b | ADDRMETH_M ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetchnta" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht0" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht1" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_RT | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 | isa_GP "prefetcht2" 2 0 0 0 0
|
|
|
|
+# table truncated
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_0F71 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 12"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+# Mod 00
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 01
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 10
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 11
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psraw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_660F71 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 12 SSE"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+# Mod 00
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 01
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 10
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 11
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psraw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_0F72 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 13"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+# Mod 00
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 01
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 10
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 11
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrad" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pslld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+TABLE tbl_660F72 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 13 SSE"
|
|
|
|
+# Mod 00
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 01
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 10
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 11
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrad" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pslld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_0F73 tbl_extension shift 0 mask 0 minlim 0 maxlim 0 "Group 14"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+# Mod 00
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 01
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 10
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 11
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_P | OPTYPE_q | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+# TODO: last 2 opcodes
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+TABLE tbl_660F73 tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 14 SSE"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+# Mod 00
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 01
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 10
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 11
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrlq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psrldq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "psllq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_OTHER ADDRMETH_W | OPTYPE_dq | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_PENTIUM | isa_MMX "pslldq" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+#TODO: fill in opcodes
|
|
|
|
+TABLE tbl_0FAE tbl_extension shift 3 mask 31 minlim 0 maxlim 31 "Group 15"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+# Mod 00
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxsave" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_R ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxrstor" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE ARG_NONE cpu_PENTIUM2 "ldmxcsr" 0 0 0 0 25
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 "stmxcsr" 0 0 0 0 48
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "clflush" 0 0 0 0 0
|
|
|
|
+# Mod 01
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxsave" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_R ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxrstor" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE ARG_NONE cpu_PENTIUM2 "ldmxcsr" 0 0 0 0 25
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 "stmxcsr" 0 0 0 0 48
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "clflush" 0 0 0 0 0
|
|
|
|
+# Mod 10
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxsave" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_E | OPTYPE_fx | OP_R ARG_NONE ARG_NONE cpu_PENTIUM | isa_MMX "fxrstor" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_R ARG_NONE ARG_NONE cpu_PENTIUM2 "ldmxcsr" 0 0 0 0 25
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_E | OPTYPE_d | OP_W ARG_NONE ARG_NONE cpu_PENTIUM2 "stmxcsr" 0 0 0 0 48
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ADDRMETH_M | OPTYPE_b | OP_R ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "clflush" 0 0 0 0 0
|
|
|
|
+# Mod 11
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE 0 "lfence" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE 0 "mfence" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE 0 "sfence" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_0FBA tbl_extension shift 3 mask 7 minlim 4 maxlim 7 "Group 8"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "bt" 0 0 0 INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "bts" 0 0 0 INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "btr" 0 0 0 INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_BITTEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "btc" 0 0 0 INS_SET_CARRY 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_0FC7 tbl_extension shift 3 mask 31 minlim 0 maxlim 17 "Group 9"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+# Mod 00
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_XCHGCC ADDRMETH_M | OPTYPE_q | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "cmpxch8b" 0 0 0 0 9
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 01
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_XCHGCC ADDRMETH_M | OPTYPE_q | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "cmpxch8b" 0 0 0 0 9
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+# Mod 10
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE 0 "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_XCHGCC ADDRMETH_M | OPTYPE_q | OP_W ARG_NONE ARG_NONE cpu_PENTIUM | isa_GP "cmpxch8b" 0 0 0 0 9
|
|
|
|
+# Table truncated
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_0FB9 tbl_extension shift 3 mask 7 minlim 0 maxlim 0 "Group 10"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_SYSTEM ARG_NONE ARG_NONE ARG_NONE 0 "fxsave" 0 0 0 0 0
|
|
|
|
+# Table truncated
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_C6 tbl_extension shift 3 mask 7 minlim 0 maxlim 0 "Group 11a"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_E | OPTYPE_b | OP_W ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
|
|
|
+# Table truncated
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_C7 tbl_extension shift 3 mask 7 minlim 0 maxlim 0 "Group 11b"
|
|
|
|
+INSN 0 INS_MOV ADDRMETH_E | OPTYPE_v | OP_W ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mov" 0 0 0 0 0
|
|
|
|
+# Table truncated
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_80 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 1a"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_OR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_AND ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_XOR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_CMP ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_81 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 1b"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_OR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_AND ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_XOR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_CMP ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_82 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 1c"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_OR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_AND ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_XOR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_CMP ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_83 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 1d"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "add" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_OR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "or" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "adc" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sbb" 0 0 0 INS_SET_ALL|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_AND ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "and" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "sub" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_XOR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "xor" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_CMP ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "cmp" 0 0 0 INS_SET_ALL 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_C0 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2a"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 0 0 INS_SET_ALL 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_C1 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2b"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 0 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_I | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 0 0 INS_SET_ALL 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_D0 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2c"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_II | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 1 0 INS_SET_ALL 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_D1 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2d"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_II | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 1 0 INS_SET_ALL 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_D2 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2e"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_b | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 1 0 INS_SET_ALL 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_D3 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 2f"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rol" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "ror" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW 0
|
|
|
|
+INSN 0 INS_ROL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcl" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_ROR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "rcr" 0 1 0 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shl" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "shr" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHL ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sal" 0 1 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_SHR ADDRMETH_E | OPTYPE_v | OP_W | OP_R ADDRMETH_RR | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "sar" 0 1 0 INS_SET_ALL 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_F6 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 3a"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_TEST ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_TEST ADDRMETH_E | OPTYPE_b | OP_R ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_NOT ADDRMETH_E | OPTYPE_b | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "not" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_NEG ADDRMETH_E | OPTYPE_b | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "neg" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_MUL OPTYPE_b | ADDRMETH_RR | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "mul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 22
|
|
|
|
+INSN 0 INS_MUL OPTYPE_b | ADDRMETH_RR | OP_W | OP_SIGNED | OP_R ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "imul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 22
|
|
|
|
+INSN 0 INS_DIV ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "div" 0 0 0 0 13
|
|
|
|
+INSN 0 INS_DIV ADDRMETH_RR | OPTYPE_b | OP_W | OP_R ADDRMETH_E | OPTYPE_b | OP_R ARG_NONE cpu_80386 | isa_GP "idiv" 0 0 0 0 13
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_F7 tbl_extension shift 3 mask 7 minlim 0 maxlim 7 "Group 3b"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_TEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_TEST ADDRMETH_E | OPTYPE_v | OP_R ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "test" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_NOT ADDRMETH_E | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "not" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_NEG ADDRMETH_E | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "neg" 0 0 0 INS_SET_ALL 0
|
|
|
|
+INSN 0 INS_MUL ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "mul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 23
|
|
|
|
+INSN 0 INS_MUL ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R ARG_NONE cpu_80386 | isa_GP "imul" 0 0 0 INS_SET_OFLOW|INS_SET_CARRY 23
|
|
|
|
+INSN 0 INS_DIV ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "div" 0 0 0 0 14
|
|
|
|
+INSN 0 INS_DIV ADDRMETH_RR | OPTYPE_v | OP_W | OP_R ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE cpu_80386 | isa_GP "idiv" 0 0 0 0 14
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_FE tbl_extension shift 3 mask 7 minlim 0 maxlim 1 "Group 4"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_INC ADDRMETH_E | OPTYPE_b | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
|
|
|
|
+INSN 0 INS_DEC ADDRMETH_E | OPTYPE_b | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_FF tbl_extension shift 3 mask 7 minlim 0 maxlim 6 "Group 5"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_INC ADDRMETH_E | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "inc" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
|
|
|
|
+INSN 0 INS_DEC ADDRMETH_E | OPTYPE_v | OP_W | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "dec" 0 0 0 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 0
|
|
|
|
+INSN 0 INS_CALL ADDRMETH_E | OPTYPE_v | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "call" 0 0 0 0 3
|
|
|
|
+INSN 0 INS_CALL ADDRMETH_E | OPTYPE_p | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "callf" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_BRANCH ADDRMETH_E | OPTYPE_v | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jmp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_BRANCH ADDRMETH_E | OPTYPE_p | OP_X ARG_NONE ARG_NONE cpu_80386 | isa_GP "jmpf" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_PUSH ADDRMETH_E | OPTYPE_v | OP_R ARG_NONE ARG_NONE cpu_80386 | isa_GP "push" 0 0 0 0 33
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_D8 tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU D8"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fadd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fmul" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcom" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsub" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_D8C0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU D8 C0"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 1 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 3 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 4 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 5 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 6 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 7 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 1 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 3 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 4 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 5 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 6 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 7 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 1 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 2 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 3 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 4 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 5 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 6 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcom" 0 7 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 1 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 2 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 3 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 4 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 5 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 6 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 7 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 1 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 3 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 4 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 5 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 6 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 7 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 1 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 3 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 4 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 5 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 6 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 7 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 1 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 3 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 4 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 5 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 6 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 7 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 1 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 3 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 4 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 5 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 6 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 7 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_D9 tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU D9"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fs|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fv|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldenv" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldcw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fv|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnstenv" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnstcw" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_D9C0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU D9 C0"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 1 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 3 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 4 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 5 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 6 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fld" 0 7 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 1 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 3 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 4 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 5 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 6 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fxch" 0 7 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnop" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fchs" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fabs" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ftst" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fxam" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fld1" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldl2t" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldl2e" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldpi" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldlg2" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldln2" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fldz" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "f2xm1" 0 0 0 0 16
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fyl2x" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fptan" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fpatan" 0 0 0 0 18
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fxtract" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fprem1" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fdecstp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fincstp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fprem" 0 0 0 0 19
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fyl2xp1" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsqrt" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsincos" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "frndint" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fscale" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsin" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcos" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DA tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DA"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fiadd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fimul" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ficom" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ficomp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fisub" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fisubr" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fidiv" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fidivr" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DAC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DA C0"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 0 0 INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 1 0 INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 2 0 INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 3 0 INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 4 0 INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 5 0 INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 6 0 INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovb" 0 7 0 INS_TEST_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 0 0 INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 1 0 INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 2 0 INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 3 0 INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 4 0 INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 5 0 INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 6 0 INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmove" 0 7 0 INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 0 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 1 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 2 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 3 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 4 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 5 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 6 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovbe" 0 7 0 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 0 0 INS_TEST_PARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 1 0 INS_TEST_PARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 2 0 INS_TEST_PARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 3 0 INS_TEST_PARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 4 0 INS_TEST_PARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 5 0 INS_TEST_PARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 6 0 INS_TEST_PARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcmovu" 0 7 0 INS_TEST_PARITY 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fucompp" 0 0 0 0 21
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DB tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DB"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fild" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "fisttp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fist" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_d|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fistp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fe|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fe|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DBC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DB C0"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 0 0 INS_TEST_NCARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 1 0 INS_TEST_NCARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 2 0 INS_TEST_NCARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 3 0 INS_TEST_NCARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 4 0 INS_TEST_NCARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 5 0 INS_TEST_NCARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 6 0 INS_TEST_NCARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnb" 0 7 0 INS_TEST_NCARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 0 0 INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 1 0 INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 2 0 INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 3 0 INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 4 0 INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 5 0 INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 6 0 INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovne" 0 7 0 INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 0 0 INS_TEST_NCARRY|INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 1 0 INS_TEST_NCARRY|INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 2 0 INS_TEST_NCARRY|INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 3 0 INS_TEST_NCARRY|INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 4 0 INS_TEST_NCARRY|INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 5 0 INS_TEST_NCARRY|INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 6 0 INS_TEST_NCARRY|INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnbe" 0 7 0 INS_TEST_NCARRY|INS_TEST_NZERO 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 0 0 INS_TEST_NPARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 1 0 INS_TEST_NPARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 2 0 INS_TEST_NPARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 3 0 INS_TEST_NPARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 4 0 INS_TEST_NPARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 5 0 INS_TEST_NPARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 6 0 INS_TEST_NPARITY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcmovnu" 0 7 0 INS_TEST_NPARITY 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnclex" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fninit" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 1 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 3 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 4 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 5 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 6 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomi" 0 7 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 1 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 2 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 3 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 4 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 5 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 6 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_PENTPRO | isa_GP "fcomi" 0 7 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DC tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DC"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fadd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fmul" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcom" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 17
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcomp" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsub" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DCC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DC C0"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fadd" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmul" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubr" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsub" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivr" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdiv" 7 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DD tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DD"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_q|OP_W ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "fisttp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fd|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_ft|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "frstor" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_ft|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnsave" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnstsw" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DDC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DD C0"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ffree" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fst" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fstp" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucom" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomp" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DE tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DE"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fiadd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fimul" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ficom" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "ficomp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fisub" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fisubr" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fidiv" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fidivr" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DEC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DE C0"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 0 0 0 0 20
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 1 0 0 0 20
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 2 0 0 0 20
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 3 0 0 0 20
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 4 0 0 0 20
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 5 0 0 0 20
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 6 0 0 0 20
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "faddp" 7 0 0 0 20
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fmulp" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fcompp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubrp" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fsubp" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivrp" 7 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 1 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 2 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 3 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 4 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 5 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 6 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fdivp" 7 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DF tbl_fpu shift 3 mask 7 minlim 0 maxlim 191 "FPU DF"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fild" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_PENTIUM4 | isa_GP "fisttp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fist" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_w|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fistp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fb|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fbld" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_q|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fild" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_fb|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fbstp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_M|OPTYPE_q|OP_W ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fistp" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_DFC0 tbl_fpu_ext shift 0 mask 255 minlim 192 maxlim 255 "FPU DF C0"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RR | OPTYPE_w | OP_R ARG_NONE ARG_NONE cpu_80387 | isa_FPU "fnstsw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 1 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 2 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 3 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 4 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 5 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 6 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fucomip" 0 7 0 0 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 0 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 1 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 2 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 3 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 4 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 5 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 6 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_FPU ADDRMETH_RF | OPTYPE_fp | OP_W ADDRMETH_RF | OPTYPE_fp | OP_R ARG_NONE cpu_80387 | isa_FPU "fcomip" 0 7 0 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_80387 | isa_FPU "" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
|
|
|
|
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
|
+
|
|
|
|
+TABLE tbl_0F0F tbl_suffix shift 0 mask 255 minlim 0 maxlim 191 "3D Now! 0F Suffix"
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 00 */
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_CONV ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pi2fd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 10 */
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_CONV ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pf2id" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 20 */
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 30 */
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 40 */
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 50 */
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 60 */
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 70 */
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0 /* 80 */
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_CMP ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfcmpge" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MIN ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfmin" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfrcp" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfrsqrt" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfsub" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfadd" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_CMP ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfcmpgt" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MAX ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfmax" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfrcpit1" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfrsqit1" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_SUB ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfsubr" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ADD ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfacc" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_CMP ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfcmpeq" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MUL ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfmul" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_ARITH ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pfrcpit2" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_MUL ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pmulhrw" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_INVALID ARG_NONE ARG_NONE ARG_NONE cpu_K6 | isa_3DNOW "" 0 0 0 0 0
|
|
|
|
+INSN 0 INS_AVG ADDRMETH_P | OPTYPE_pi | OP_R | OP_W ADDRMETH_Q | OPTYPE_q |OP_R ARG_NONE cpu_K6 | isa_3DNOW "pavgusb" 0 0 0 0 0
|
|
|
|
+#______________________________________________________________________________
|
|
|
|
+END TABLE
|
|
|
|
+
|
|
|
|
+
|
|
|
|
+
|
|
|
|
+#=======================================================================
|
|
|
|
+# TODO:
|
|
|
|
+# + Support only three flags types: set, clear, and toggle. Move specific flag
|
|
|
|
+# into flags set.
|
|
|
|
+# + Finish typing 'unknown' instructions, esp ps and pd instructions.
|
|
|
|
+#=======================================================================
|
|
|
|
+# CPU Ver:
|
|
|
|
+#mmx: (data xfer) movd, movq, (conversion) packsswb, packssdw, packuswb,
|
|
|
|
+#punpckhbw, punpckhwd, punpckhdq, punpcklbw, punpcklwd, punpckldq,
|
|
|
|
+#(arith) paddb, paddw, paddd, paddsb, paddsw, paddusb, paddusw,
|
|
|
|
+#psubb, psubw, psubd, psubsb, psubsw, psubusb, psubusw, pmulhw, pmullw, pmaddwd,
|
|
|
|
+#(cmp) PCMPEQB PCMPEQW PCMPEQD PCMPGTB PCMPGTW PCMPGTD,
|
|
|
|
+#(logic) PAND PANDN POR PXOR, (shift/rot) PSLLW PSLLD PSLLQ PSRLW PSRLD
|
|
|
|
+#PSRLQ PSRAW PSRAD, (sys) emms
|
|
|
|
+
|
|
|
|
+#sse: (data xfer) MOVAPS MOVUPS MOVHPS, MOVHLPS MOVLPS MOVLHPS MOVMSKPS MOVSS,
|
|
|
|
+#(arith) ADDPS ADDSS SUBPS SUBSS MULPS MULSS DIVPS DIVSS RCPPS RCPSS SQRTPS
|
|
|
|
+#SQRTSS RSQRTPS RSQRTSS MAXPS MAXSS MINPS MINSS, (cmp) CMPPS CMPSS COMISS
|
|
|
|
+#UCOMISS, (logic) ANDPS ANDNPS ORPS XORPS, (misc) SHUFPS UNPCKHPS UNPCKLPS,
|
|
|
|
+#(convert) CVTPI2PS CVTSI2SS CVTPS2PI CVTTPS2PI CVTSS2SI CVTTSS2SI,
|
|
|
|
+#(sys) LDMXCSR STMXCSR, (misc) PAVGB PAVGW PEXTRW PINSRW PMAXUB PMAXSW PMINUB
|
|
|
|
+#PMINSW, PMOVMSKB PMULHUW PSADBW PSHUFW, (sys) MASKMOVQ MOVNTQ MOVNTPS
|
|
|
|
+# PREFETCHh SFENCE
|
|
|
|
+
|
|
|
|
+#sse2: (data xfer) MOVAPD MOVUPD MOVHPD MOVLPD MOVMSKPD MOVSD (arith)
|
|
|
|
+#ADDPD ADDSD SUBPD SUBSD MULPD MULSD, DIVPD DIVSD SQRTPD SQRTSD MAXPD ,
|
|
|
|
+#MAXSD MINPD MINSD (logic) ANDPD ANDNPD ORPD XORPD, (cmp) CMPPD CMPSD COMISD
|
|
|
|
+#UCOMISD, (misc) SHUFPD UNPCKHPD UNPCKLPD, (c0nvert) CVTPD2PI CVTTPD2PI
|
|
|
|
+#CVTPI2PD CVTPD2DQ CVTTPD2DQ CVTDQ2PD CVTPS2PD CVTPD2PS CVTSS2SD CVTSD2SS
|
|
|
|
+#CVTSD2SI CVTTSD2SI CVTSI2SD (fp) CVTDQ2PS CVTPS2DQ CVTTPS2DQ, (...)
|
|
|
|
+#MOVDQA MOVDQU MOVQ2DQ MOVDQ2Q PMULUDQ PADDQ PSUBQ PSHUFLW PSHUFHW PSHUFD
|
|
|
|
+#PSLLDQ PSRLDQ PUNPCKHQDQ PUNPCKLQDQ, (sys) CLFLUSH LFENCE MFENCE PAUSE
|
|
|
|
+#MASKMOVDQU MOVNTPD MOVNTDQ MOVNTI
|
|
|
|
+
|
|
|
|
+#sse3: (convert) FISTTP, (data xfer) LDDQU, (arith) ADDSUBPS ADDSUBPD,
|
|
|
|
+#HADDPS HSUBPS HADDPD HSUBPD, (data xfer) MOVSHDUP MOVSLDUP MOVDDUP,
|
|
|
|
+#(sys) MONITOR MWAIT
|
|
|
|
+#sys/ring0: LGDT SGDT LLDT SLDT LTR STR LIDT SIDT MOV LMSW
|
|
|
|
+#SMSW CLTS ARPL LAR LSL VERR VERW MOV INVD WBINVD INVLPG LOCK HLT RSM RDMSR
|
|
|
|
+#WRMSR RDPMC RDTSC SYSENTER SYSEXIT
|
|
|
|
+
|
|
|
|
+#386: lss, lfs, lgs, long disp jcc, single-bit insn, bit scan insns,
|
|
|
|
+#double shift, byte set on cond, mov w/ sign ext, generalized multiply,
|
|
|
|
+#mov to/from control reg, move to/from test reg, mov to/from debug reg,
|
|
|
|
+#rsm
|
|
|
|
+
|
|
|
|
+# exceptions : bitmask them, return exception name?
|
|
|
|
+#TABLE tbl_DA tbl_fpu shift 3 mask 15 minlim 0 maxlim 15 "FPU DA"
|
|
|
|
+#TABLE tbl_DAC0 tbl_fpu_ext shift 0 mask 31 minlim 0 maxlim 31 "FPU DA C0"
|