Browse Source

Working towards gui integration with exetoc_qt

nemerle 9 years ago
parent
commit
36b063c183

+ 68 - 0
3rd_party/libdisasm/INTEL_BUGS

@@ -0,0 +1,68 @@
+PMOVMSKB
+Gd, Pq1H
+PMOVMSKB
+(66)
+Gd, Vdq1H
+
+should be 
+
+PMOVMSKB
+Gd, Qq1H
+PMOVMSKB
+(66)
+Gd, Wdq1H
+
+The instruction represented by this opcode expression does not support any 
+operand to be a memory location.
+
+MASKMOVQ
+Pq, Pq1H
+MASKMOVDQU
+(66)
+Vdq, Vdq1H
+
+should be
+
+MASKMOVQ
+Pq, Pq1H
+MASKMOVDQU
+(66)
+Vdq, Wdq1H
+
+MOVMSKPS
+Gd, Vps1H
+MOVMSKPD
+(66)
+Gd, Vpd1H
+
+should be
+
+MOVMSKPS
+Gd, Wps1H
+MOVMSKPD
+(66)
+Gd, Wpd1H
+
+The opcode table entries for LFS, LGS, and LSS
+
+L[FGS]S
+Mp
+
+should be
+
+L[FGS]S
+Gv,Mp
+
+MOVHLPS 
+Vps, Vps
+
+MOVLHPS
+Vps, Vps
+
+should be
+
+MOVHLPS 
+Vps, Wps
+
+MOVLHPS
+Vps, Wps

+ 137 - 0
3rd_party/libdisasm/LICENSE

@@ -0,0 +1,137 @@
+
+
+
+
+			 The "Clarified Artistic License"
+
+				Preamble
+
+The intent of this document is to state the conditions under which a
+Package may be copied, such that the Copyright Holder maintains some
+semblance of artistic control over the development of the package,
+while giving the users of the package the right to use and distribute
+the Package in a more-or-less customary fashion, plus the right to make
+reasonable modifications.
+
+Definitions:
+
+	"Package" refers to the collection of files distributed by the
+	Copyright Holder, and derivatives of that collection of files
+	created through textual modification.
+
+	"Standard Version" refers to such a Package if it has not been
+	modified, or has been modified in accordance with the wishes
+	of the Copyright Holder as specified below.
+
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+	copyrights for the package.
+
+	"You" is you, if you're thinking about copying or distributing
+	this Package.
+
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+	Package to another party.
+
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+	the item, though there may be fees involved in handling the item.
+
+1. You may make and give away verbatim copies of the source form of the
+Standard Version of this Package without restriction, provided that you
+duplicate all of the original copyright notices and associated disclaimers.
+
+2. You may apply bug fixes, portability fixes and other modifications
+derived from the Public Domain, or those made Freely Available, or from
+the Copyright Holder.  A Package modified in such a way shall still be
+considered the Standard Version.
+
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+following:
+
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+    Freely Available, such as by posting said modifications to Usenet or
+    an equivalent medium, or placing the modifications on a major archive
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+    documents how it differs from the Standard Version.
+
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+
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+    permission to make your modifications Freely Available in some specific
+    way.
+
+4. You may distribute the programs of this Package in object code or
+executable form, provided that you do at least ONE of the following:
+
+    a) distribute a Standard Version of the executables and library files,
+    together with instructions (in the manual page or equivalent) on where
+    to get the Standard Version.
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+    b) accompany the distribution with the machine-readable source of
+    the Package with your modifications.
+
+    c) give non-standard executables non-standard names, and clearly
+    document the differences in manual pages (or equivalent), together
+    with instructions on where to get the Standard Version.
+
+    d) make other distribution arrangements with the Copyright Holder.
+
+    e) offer the machine-readable source of the Package, with your
+    modifications, by mail order.
+
+5. You may charge a distribution fee for any distribution of this Package.
+If you offer support for this Package, you may charge any fee you choose
+for that support.  You may not charge a license fee for the right to use
+this Package itself.  You may distribute this Package in aggregate with
+other (possibly commercial and possibly nonfree) programs as part of a
+larger (possibly commercial and possibly nonfree) software distribution,
+and charge license fees for other parts of that software distribution,
+provided that you do not advertise this Package as a product of your own.
+If the Package includes an interpreter, You may embed this Package's
+interpreter within an executable of yours (by linking); this shall be
+construed as a mere form of aggregation, provided that the complete
+Standard Version of the interpreter is so embedded.
+
+6. The scripts and library files supplied as input to or produced as
+output from the programs of this Package do not automatically fall
+under the copyright of this Package, but belong to whoever generated
+them, and may be sold commercially, and may be aggregated with this
+Package.  If such scripts or library files are aggregated with this
+Package via the so-called "undump" or "unexec" methods of producing a
+binary executable image, then distribution of such an image shall
+neither be construed as a distribution of this Package nor shall it
+fall under the restrictions of Paragraphs 3 and 4, provided that you do
+not represent such an executable image as a Standard Version of this
+Package.
+
+7. C subroutines (or comparably compiled subroutines in other
+languages) supplied by you and linked into this Package in order to
+emulate subroutines and variables of the language defined by this
+Package shall not be considered part of this Package, but are the
+equivalent of input as in Paragraph 6, provided these subroutines do
+not change the language in any way that would cause it to fail the
+regression tests for the language.
+
+8. Aggregation of the Standard Version of the Package with a commercial
+distribution is always permitted provided that the use of this Package is
+embedded; that is, when no overt attempt is made to make this Package's
+interfaces visible to the end user of the commercial distribution.
+Such use shall not be construed as a distribution of this Package.
+
+9. The name of the Copyright Holder may not be used to endorse or promote
+products derived from this software without specific prior written permission.
+
+10. THIS PACKAGE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+
+				The End

+ 12 - 0
3rd_party/libdisasm/NAMESPACE.TXT

@@ -0,0 +1,12 @@
+
+The rewritten libdisasm code uses the following namespaces:
+
+
+	Prefix		Namespace
+----------------------------------------------------
+	x86_		Global 'libdisasm' namespace
+	ia32_		Internal IA32 ISA namespace
+	ia64_		Internal IA64 ISA namespace
+	ix64_		Internal X86-64 ISA namespace
+
+Note that the 64-bit ISAs are not yet supported/written.

+ 2 - 0
3rd_party/libdisasm/README

@@ -0,0 +1,2 @@
+This is a cut-up version of libdisasm originally from the bastard project http://bastard.sourceforge.net/
+

+ 43 - 0
3rd_party/libdisasm/TODO

@@ -0,0 +1,43 @@
+x86_format.c
+------------
+intel: jmpf -> jmp, callf -> call
+att: jmpf -> ljmp, callf -> lcall
+
+opcode table
+------------
+finish typing instructions
+fix flag clear/set/toggle types
+
+ix64 stuff
+----------
+document output file formats in web page
+features doc: register aliases, implicit operands, stack mods,
+ring0 flags, eflags, cpu model/isa
+
+ia32_handle_* implementation
+
+fix operand 0F C2
+CMPPS
+
+* sysenter, sysexit as CALL types -- preceded by MSR writes
+* SYSENTER/SYSEXIT stack : overwrites SS, ESP
+* stos, cmps, scas, movs, ins, outs, lods -> OP_PTR
+* OP_SIZE in implicit operands
+* use OP_SIZE to choose reg sizes!
+
+DONE?? :
+implicit operands: provide action ?
+e.g. add/inc for stach, write, etc 
+replace table numbers in opcodes.dat with
+#defines for table names
+
+replace 0  with INSN_INVALID   [or maybe FF for imnvalid and 00 for Not Applicable */
+no wait that is only for prefix tables -- n/p
+
+if ( prefx) only use if insn != invalid
+
+these should cover all the wacky disasm exceptions 
+
+for the rep one we can chet, match only a 0x90
+
+todo: privilege | ring

+ 36 - 0
3rd_party/libdisasm/ia32_fixup.cpp

@@ -0,0 +1,36 @@
+#include <stdio.h>
+
+static const char * mem_fixup[256] = {
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 00 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 08 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 10 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 18 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 20 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 28 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 30 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 38 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 40 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 48 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 50 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 58 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 60 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 68 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 70 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 78 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 80 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 88 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 90 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 98 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* A0 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* A8 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* B0 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* B8 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* C0 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* C8 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* D0 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* D8 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* E0 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* E8 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* F0 */
+	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL /* F8 */
+};

+ 3206 - 0
3rd_party/libdisasm/ia32_opcode.dat

@@ -0,0 +1,3206 @@
+# IA32 OPCODE MAP
+# Tab-delimited file of Intel Opcode Tables
+
+# Each table begins with the line
+# ^TABLE $NAME\tindex $INDEX\ttype $TYPE\tshift $SHIFT\tmask $MASK\tminlim $MIN\tmaxlim $MAX\tname $NAME
+# and ends with the line
+# END TABLE
+
+# Each instruction is formed of the line
+# ^INSN $TABLE\t$MFLAG\t$DFLAG\t$SFLAG\t$AFLAG\t$CPU
+#  \t$MNEM\t$DEST\t$SRC\t$AUX\t$EFLAGS\t$COMMENT
+# Note that this is a single line: the newline in the above is for clarity.
+# The fields are:
+#	TABLE	:	index of next lookup table if appropriate
+#	MFLAG	:	mnemonic (instruction) flags
+#	DFLAG	:	destination (1st) operand flags
+#	SFLAG	:	source (2nd) operand flags
+#	AFLAG	:	aux (3rd) operand flags
+#	CPU	:	minimum CPU version supporting this insn
+#	MNEM	:	ASCII mnemonic
+#	DEST	:	hard-coded destination operand
+#	SRC	:	hard-coded source operand
+#	AUX	:	hard-coded aux operand
+#	EFLAGS	:	cpu flags effected by instruction
+#	IMPLICIT:	implicit operands
+#	CMT	:	comment : usually the byte or index in the table
+
+
+# Obviously blank lines and lines beginning with '#' are ignored.
+PREFIX ia32
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_Main	tbl_opcode	shift 0	mask 255	minlim 0	maxlim 255	"One-byte Opcodes"
+#______________________________________________________________________________
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_G | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "add"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "add"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_ADD	  ADDRMETH_G | OPTYPE_b | OP_W | OP_R	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "add"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_ADD	  ADDRMETH_G | OPTYPE_v | OP_W | OP_R	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "add"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_ADD	  ADDRMETH_RR | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "add"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_ADD	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "add"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_PUSH	  ADDRMETH_RS | OPTYPE_w | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  0	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RS | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  0	  0	  0	 0 	33
+INSN 0	  INS_OR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_G | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "or"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_OR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "or"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_OR	  ADDRMETH_G | OPTYPE_b | OP_W | OP_R	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "or"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_OR	  ADDRMETH_G | OPTYPE_v | OP_W | OP_R	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "or"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_OR	  ADDRMETH_RR | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "or"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_OR	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "or"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_PUSH	  ADDRMETH_RS | OPTYPE_w | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  1	  0	  0	 0 	33
+INSN idx_0F	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_G | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "adc"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "adc"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_ADD	  ADDRMETH_G | OPTYPE_b | OP_W | OP_R	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "adc"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_ADD	  ADDRMETH_G | OPTYPE_v | OP_W | OP_R	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "adc"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_ADD	  ADDRMETH_RR | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "adc"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_ADD	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "adc"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_PUSH	  ADDRMETH_RS | OPTYPE_w | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  2	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RS | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  2	  0	  0	 0 	33
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R	  ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sbb"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sbb"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_SUB	  ADDRMETH_G | OPTYPE_b | OP_W | OP_SIGNED | OP_R	  ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sbb"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_SUB	  ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_W | OP_R	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sbb"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_SUB	  ADDRMETH_RR | OPTYPE_b | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sbb"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_SUB	  ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sbb"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_PUSH	  ADDRMETH_RS | OPTYPE_w | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  3	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RS | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  3	  0	  0	 0 	33
+INSN 0	  INS_AND	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_G | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "and"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_AND	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "and"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_AND	  ADDRMETH_G | OPTYPE_b | OP_W | OP_R	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "and"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_AND	  ADDRMETH_G | OPTYPE_v | OP_W | OP_R	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "and"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_AND	  ADDRMETH_RR | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "and"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_AND	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "and"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_NOTE_PREFIX | PREFIX_ES	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_BCDCONV	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "daa"	  0	  0	  0	 INS_SET_SIGN|INS_SET_ZERO|INS_SET_CARRY|INS_SET_PARITY|INS_TEST_CARRY 	12
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R	  ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sub"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sub"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SUB	  ADDRMETH_G | OPTYPE_b | OP_SIGNED | OP_W | OP_R	  ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sub"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SUB	  ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_W | OP_R	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sub"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SUB	  ADDRMETH_RR | OPTYPE_b | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sub"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SUB	  ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sub"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_NOTE_PREFIX | PREFIX_CS | PREFIX_NOTTAKEN	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_BCDCONV	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "das"	  0	  0	  0	 INS_SET_SIGN|INS_SET_ZERO|INS_SET_CARRY|INS_SET_PARITY|INS_TEST_CARRY 	0
+INSN 0	  INS_XOR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_G | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xor"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_XOR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xor"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_XOR	  ADDRMETH_G | OPTYPE_b | OP_W | OP_R	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xor"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_XOR	  ADDRMETH_G | OPTYPE_v | OP_W | OP_R	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xor"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_XOR	  ADDRMETH_RR | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xor"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_XOR	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xor"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_NOTE_PREFIX | PREFIX_SS	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_BCDCONV	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "aaa"	  0	  0	  0	 INS_SET_CARRY 	1
+INSN 0	  INS_CMP	  ADDRMETH_E | OPTYPE_b | OP_R	  ADDRMETH_G | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmp"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_CMP	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmp"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_CMP	  ADDRMETH_G | OPTYPE_b | OP_R	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmp"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_CMP	  ADDRMETH_G | OPTYPE_v | OP_R	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmp"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_CMP	  ADDRMETH_RR | OPTYPE_b | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmp"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_CMP	  ADDRMETH_RR | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmp"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_NOTE_PREFIX | PREFIX_DS | PREFIX_TAKEN	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_BCDCONV	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "aas"	  0	  0	  0	 INS_SET_CARRY 	0
+INSN 0	  INS_INC	  ADDRMETH_RR | OPTYPE_v | OP_R | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "inc"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_INC	  ADDRMETH_RR | OPTYPE_v | OP_R | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "inc"	  1	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_INC	  ADDRMETH_RR | OPTYPE_v | OP_R | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "inc"	  2	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_INC	  ADDRMETH_RR | OPTYPE_v | OP_R | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "inc"	  3	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_INC	  ADDRMETH_RR | OPTYPE_v | OP_R | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "inc"	  4	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_INC	  ADDRMETH_RR | OPTYPE_v | OP_R | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "inc"	  5	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_INC	  ADDRMETH_RR | OPTYPE_v | OP_R | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "inc"	  6	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_INC	  ADDRMETH_RR | OPTYPE_v | OP_R | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "inc"	  7	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_DEC	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "dec"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_DEC	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "dec"	  1	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_DEC	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "dec"	  2	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_DEC	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "dec"	  3	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_DEC	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "dec"	  4	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_DEC	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "dec"	  5	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_DEC	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "dec"	  6	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_DEC	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "dec"	  7	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_PUSH	  ADDRMETH_RR | OPTYPE_v | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  0	  0	  0	 0 	33
+INSN 0	  INS_PUSH	  ADDRMETH_RR | OPTYPE_v | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  1	  0	  0	 0 	33
+INSN 0	  INS_PUSH	  ADDRMETH_RR | OPTYPE_v | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  2	  0	  0	 0 	33
+INSN 0	  INS_PUSH	  ADDRMETH_RR | OPTYPE_v | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  3	  0	  0	 0 	33
+INSN 0	  INS_PUSH	  ADDRMETH_RR | OPTYPE_v | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  4	  0	  0	 0 	33
+INSN 0	  INS_PUSH	  ADDRMETH_RR | OPTYPE_v | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  5	  0	  0	 0 	33
+INSN 0	  INS_PUSH	  ADDRMETH_RR | OPTYPE_v | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  6	  0	  0	 0 	33
+INSN 0	  INS_PUSH	  ADDRMETH_RR | OPTYPE_v | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  7	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RR | OPTYPE_v | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  0	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RR | OPTYPE_v | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  1	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RR | OPTYPE_v | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  2	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RR | OPTYPE_v | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  3	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RR | OPTYPE_v | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  4	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RR | OPTYPE_v | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  5	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RR | OPTYPE_v | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  6	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RR | OPTYPE_v | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  7	  0	  0	 0 	33
+INSN 0	  INS_PUSHREGS	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pushad"	  0	  0	  0	 0 	36
+INSN 0	  INS_POPREGS	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "popad"	  0	  0	  0	 0 	34
+INSN 0	  INS_BOUNDS	  ADDRMETH_G | OPTYPE_v | OP_R	  ADDRMETH_M | OPTYPE_a | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "bound"	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_E | OPTYPE_w | OP_R	  ADDRMETH_G | OPTYPE_w | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "arpl"	  0	  0	  0	 INS_SET_ZERO 	0
+INSN 0	  INS_NOTE_PREFIX | PREFIX_FS	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_NOTE_PREFIX | PREFIX_GS	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_66	  INS_NOTE_PREFIX | PREFIX_OP_SIZE	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_NOTE_PREFIX | PREFIX_ADDR_SIZE	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_PUSH	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  0	  0	  0	 0 	33
+INSN 0	  INS_MUL	  ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  cpu_80386 | isa_GP	  "imul"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_CARRY 	0
+INSN 0	  INS_PUSH	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  0	  0	  0	 0 	33
+INSN 0	  INS_MUL	  ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R	  ADDRMETH_I |  OPTYPE_b | OP_SIGNED | OP_R	  cpu_80386 | isa_GP	  "imul"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_CARRY 	0
+INSN 0	  INS_IN	   ADDRMETH_Y | OPTYPE_b | OP_W	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "insb"	  0	  2	  0	 0 	0
+INSN 0	  INS_IN	   ADDRMETH_Y | OPTYPE_v | OP_W	  ADDRMETH_RR | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "insd"	  0	  2	  0	 0 	0
+INSN 0	  INS_OUT	   ADDRMETH_RR | OPTYPE_b | OP_R	  ADDRMETH_X | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "outsb"	  2	  0	  0	 0 	0
+INSN 0	  INS_OUT	   ADDRMETH_RR | OPTYPE_v | OP_R	  ADDRMETH_X | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "outsb"	  2	  0	  0	 0 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jo"	  0	  0	  0	 INS_TEST_OFLOW 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jno"	  0	  0	  0	 INS_TEST_NOFLOW 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jc"	  0	  0	  0	 INS_TEST_CARRY 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jnc"	  0	  0	  0	 INS_TEST_NCARRY 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jz"	  0	  0	  0	 INS_TEST_ZERO 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jnz"	  0	  0	  0	 INS_TEST_NZERO 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jbe"	  0	  0	  0	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "ja"	  0	  0	  0	 INS_TEST_NCARRY|INS_TEST_NZERO 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "js"	  0	  0	  0	 INS_TEST_SIGN 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jns"	  0	  0	  0	 INS_TEST_NSIGN 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jpe"	  0	  0	  0	 INS_TEST_PARITY 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jpo"	  0	  0	  0	 INS_TEST_NPARITY 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jl"	  0	  0	  0	 INS_TEST_SFNEOF 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jge"	  0	  0	  0	 INS_TEST_SFEQOF 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jle"	  0	  0	  0	 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jg"	  0	  0	  0	 INS_TEST_NZERO|INS_TEST_SFEQOF 	0
+INSN idx_80	  0	  ADDRMETH_E | OPTYPE_b	  ADDRMETH_I | OPTYPE_b	  ARG_NONE	 cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_81	  0	  ADDRMETH_E | OPTYPE_v	  ADDRMETH_I | OPTYPE_v	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_82	  0	  ADDRMETH_E | OPTYPE_b	  ADDRMETH_I | OPTYPE_b	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_83	  0	   ADDRMETH_E | OPTYPE_v	  ADDRMETH_I | OPTYPE_b	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_TEST	  ADDRMETH_E | OPTYPE_b | OP_R	  ADDRMETH_G | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "test"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_TEST	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "test"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_XCHG	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_G | OPTYPE_b | OP_W | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xchg"	  0	  0	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xchg"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_E | OPTYPE_b | OP_W	  ADDRMETH_G | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_E | OPTYPE_v | OP_W	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_b | OP_W	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_E | OPTYPE_w | OP_W	  ADDRMETH_S | OPTYPE_w | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_M | OPTYPE_m | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "lea"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_S | OPTYPE_w | OP_W	  ADDRMETH_E | OPTYPE_w | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_POP	  ADDRMETH_E | OPTYPE_v | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  0	  0	  0	 0 	33
+INSN 0	  INS_NOP	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "nop"	  0	  0	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xchg"	  0	  1	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xchg"	  0	  2	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xchg"	  0	  3	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xchg"	  0	  4	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xchg"	  0	  5	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xchg"	  0	  6	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xchg"	  0	  7	  0	 0 	0
+INSN 0	  INS_SZCONV	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "cwde"	  0	  0	  0	 0 	5
+INSN 0	  INS_SZCONV	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "cdq"	  0	  0	  0	 0 	11
+INSN 0	  INS_CALL	  ADDRMETH_A | OPTYPE_p | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "callf"	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "wait"	  0	  0	  0	 0 	0
+INSN 0	  INS_PUSHFLAGS	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pushfd"	  0	  0	  0	 0 	37
+INSN 0	  INS_POPFLAGS	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "popfd"	  0	  0	  0	 0 	35
+INSN 0	  INS_MOV	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "sahf"	  0	  0	  0	 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	43
+INSN 0	  INS_MOV	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lahf"	  0	  0	  0	 0 	24
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_O | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_v | OP_W	  ADDRMETH_O | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_O | OPTYPE_b | OP_W	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_O | OPTYPE_v | OP_W	  ADDRMETH_RR | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_STRMOV	  ADDRMETH_Y | OPTYPE_b | OP_W	  ADDRMETH_X | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "movsb"	  0	  0	  0	 0 	0
+INSN 0	  INS_STRMOV	  ADDRMETH_Y | OPTYPE_v | OP_W	  ADDRMETH_X | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "movsd"	  0	  0	  0	 0 	0
+INSN 0	  INS_STRCMP	  ADDRMETH_Y | OPTYPE_b | OP_R	  ADDRMETH_X | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmpsb"	  0	  0	  0	 0 	0
+INSN 0	  INS_STRCMP	  ADDRMETH_X | OPTYPE_v | OP_R	  ADDRMETH_Y | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmpsd"	  0	  0	  0	 0 	0
+INSN 0	  INS_TEST	  ADDRMETH_RR | OPTYPE_b | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "test"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_TEST	  ADDRMETH_RR | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "test"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_STRSTOR	  ADDRMETH_Y | OPTYPE_b | OP_W	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "stosb"	  0	  0	  0	 0 	0
+INSN 0	  INS_STRSTOR	  ADDRMETH_Y | OPTYPE_v | OP_W	  ADDRMETH_RR | OPTYPE_v |OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "stosd"	  0	  0	  0	 0 	0
+INSN 0	  INS_STRLOAD	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_X| OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "lodsb"	  0	  0	  0	 0 	0
+INSN 0	  INS_STRLOAD	  ADDRMETH_RR | OPTYPE_v | OP_W	  ADDRMETH_X| OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "lodsd"	  0	  0	  0	 0 	0
+INSN 0	  INS_STRCMP	  ADDRMETH_RR | OPTYPE_b | OP_R	  ADDRMETH_Y | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "scasb"	  0	  0	  0	 0 	0
+INSN 0	  INS_STRCMP	  ADDRMETH_RR | OPTYPE_v | OP_R	  ADDRMETH_Y | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "scasd"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  1	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  2	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  3	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  4	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  5	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  6	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  7	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_v | OP_W	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_v | OP_W	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  1	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_v | OP_W	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  2	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_v | OP_W	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  3	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_v | OP_W	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  4	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_v | OP_W	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  5	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_v | OP_W	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  6	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_RR | OPTYPE_v | OP_W	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  7	  0	  0	 0 	0
+INSN idx_C0	  0	   ADDRMETH_E | OPTYPE_b	  ADDRMETH_I | OPTYPE_b	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_C1	  0	   ADDRMETH_E | OPTYPE_v	  ADDRMETH_I | OPTYPE_b	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_RET	  ADDRMETH_I | OPTYPE_w | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "ret"	  0	  0	  0	 0 	3
+INSN 0	  INS_RET	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "ret"	  0	  0	  0	 0 	3
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_M | OPTYPE_p | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "les"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_M | OPTYPE_p | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "lds"	  0	  0	  0	 0 	0
+INSN idx_C6	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_C7	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_ENTER	  ADDRMETH_I | OPTYPE_w | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "enter"	  0	  0	  0	 0 	15
+INSN 0	  INS_LEAVE	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "leave"	  0	  0	  0	 0 	26
+INSN 0	  INS_RET	  ADDRMETH_I | OPTYPE_w | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "retf"	  0	  0	  0	 0 	3
+INSN 0	  INS_RET	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "retf"	  0	  0	  0	 0 	3
+INSN 0	  INS_DEBUG	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "int3"	  0	  0	  0	 0 	0
+INSN 0	  INS_TRAP	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "int"	  0	  0	  0	 0 	0
+INSN 0	  INS_OFLOW	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "into"	  0	  0	  0	 INS_TEST_OFLOW 	0
+INSN 0	  INS_TRET	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "iret"	  0	  0	  0	 INS_SET_ALL|INS_SET_DIR 	0
+INSN idx_D0	  0	   ADDRMETH_E | OPTYPE_b	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  1	  0	 0 	0
+INSN idx_D1	  0	  ADDRMETH_E | OPTYPE_v	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  1	  0	 0 	0
+INSN idx_D2	  0	  ADDRMETH_E | OPTYPE_b	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  1	  0	 0 	0
+INSN idx_D3	  0	  ADDRMETH_E | OPTYPE_v	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  1	  0	 0 	0
+INSN 0	  INS_BCDCONV	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "aam"	  0	  0	  0	 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_BCDCONV	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "aad"	  0	  0	  0	 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	2
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_XLAT	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "xlat"	  0	  0	  0	 0 	53
+INSN idx_D8	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_D9	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_DA	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_DB	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_DC	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_DD	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_DE	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_DF	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "loopnz"	  0	  0	  0	 INS_TEST_NZERO 	31
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "loopz"	  0	  0	  0	 INS_TEST_ZERO 	31
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "loop"	  0	  0	  0	 0 	31
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_b | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jcxz"	  0	  0	  0	 0 	31
+INSN 0	  INS_IN	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "in"	  0	  0	  0	 0 	0
+INSN 0	  INS_IN	  ADDRMETH_RR | OPTYPE_b | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "in"	  0	  0	  0	 0 	0
+INSN 0	  INS_OUT	  ADDRMETH_I | OPTYPE_b | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "out"	  0	  0	  0	 0 	0
+INSN 0	  INS_OUT	  ADDRMETH_I | OPTYPE_b | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "out"	  0	  0	  0	 0 	0
+INSN 0	  INS_CALL	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "call"	  0	  0	  0	 0 	3
+INSN 0	  INS_BRANCH	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jmp"	  0	  0	  0	 0 	0
+INSN 0	  INS_BRANCH	  ADDRMETH_A | OPTYPE_p | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jmpf"	  0	  0	  0	 0 	0
+INSN 0	  INS_BRANCH	  ADDRMETH_J | OPTYPE_b | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jmp"	  0	  0	  0	 0 	0
+INSN 0	  INS_IN	  ADDRMETH_RR | OPTYPE_b| OP_W	  ADDRMETH_RR | OPTYPE_w| OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "in"	  0	  2	  0	 0 	0
+INSN 0	  INS_IN	  ADDRMETH_RR | OPTYPE_v | OP_W	  ADDRMETH_RR | OPTYPE_w| OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "in"	  0	  2	  0	 0 	0
+INSN 0	  INS_OUT	  ADDRMETH_RR | OPTYPE_w| OP_R	  ADDRMETH_RR | OPTYPE_b| OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "out"	  2	  0	  0	 0 	0
+INSN 0	  INS_OUT	  ADDRMETH_RR | OPTYPE_w| OP_R	  ADDRMETH_RR | OPTYPE_v| OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "out"	  2	  0	  0	 0 	0
+INSN 0	  INS_NOTE_PREFIX | PREFIX_LOCK	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_F2	  INS_NOTE_PREFIX | PREFIX_REPNZ	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_F3	  INS_NOTE_PREFIX | PREFIX_REPZ	ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_HALT	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "hlt"	  0	  0	  0	 0 	0
+INSN 0	  INS_TOGCF	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "cmc"	  0	  0	  0	 INS_SET_CARRY 	0
+INSN idx_F6	  0	   ADDRMETH_E | OPTYPE_b	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_F7	  0	  ADDRMETH_E | OPTYPE_v	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_CLEARCF	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "clc"	  0	  0	  0	 INS_SET_NCARRY 	0
+INSN 0	  INS_SETCF	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "stc"	  0	  0	  0	 INS_SET_CARRY 	0
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "cli"	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "sti"	  0	  0	  0	 0 	0
+INSN 0	  INS_CLEARDF	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "cld"	  0	  0	  0	 INS_SET_NDIR 	0
+INSN 0	  INS_SETDF	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "std"	  0	  0	  0	 INS_SET_DIR 	0
+INSN idx_FE	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_FF	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_66	tbl_prefix	shift 0	mask 255	minlim 15	maxlim 15	"SIMD 66 one-byte Opcodes"
+#______________________________________________________________________________
+INSN idx_660F	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+# Table truncated
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_F2	tbl_prefix	shift 0	mask 255	minlim 15	maxlim 15	"SIMD F2 one-byte Opcodes"
+#______________________________________________________________________________
+INSN idx_F20F	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+# Table truncated
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+# TODO
+# lookup: if ( >= minlin && <= maxlim ) idx -= minlim;
+# 0x90 == 1001 0000 ; val >> 4 ; 1000 - 1001
+TABLE tbl_F3	tbl_prefix	shift 0	mask 255	minlim 15	maxlim 144	"SIMD F3 one-byte Opcodes"
+#______________________________________________________________________________
+INSN idx_F30F	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_SYSTEM	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pause"	0	0	0	0	0
+# Table truncated
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_0F	tbl_opcode	shift 0	mask 255	minlim 0	maxlim 255	"Two-byte Opcodes"
+#______________________________________________________________________________
+INSN idx_0F00	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN idx_0F01	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_w | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "lar"	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_w | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "lsl"	  0	  0	  0	 INS_SET_ZERO 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_CLTS	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "clts"	  0	  0	  0	 0 	6
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "invd"	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "wbinvd"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_UNKNOWN	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "ud2"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_SYSTEM	ADDRMETH_M | OPTYPE_b | OP_R	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	"prefetchw"	0	0	0	0	0
+INSN 0	INS_SYSTEM	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	"femms"	0	0	0	0	0
+INSN idx_0F0F	INS_NOTE_SUFFIX	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	  INS_MOV	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movups"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_W | OPTYPE_ps | OP_W	  ADDRMETH_V | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movups"	  0	  0	  0	 0 	0
+INSN idx_0F12	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_V | OPTYPE_q | OP_W	  ADDRMETH_W | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movlps"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "unpcklps"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "unpckhps"	  0	  0	  0	 0 	0
+INSN idx_0F16	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_W | OPTYPE_q | OP_W	  ADDRMETH_V | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movhps"	  0	  0	  0	 0 	0
+INSN idx_0F18	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_R | OPTYPE_d | OP_W	  ADDRMETH_C | OPTYPE_d | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_R | OPTYPE_d | OP_W	  ADDRMETH_D | OPTYPE_d | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_C | OPTYPE_d | OP_W	  ADDRMETH_R | OPTYPE_d | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_D | OPTYPE_d | OP_W	  ADDRMETH_R | OPTYPE_d | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_R | OPTYPE_d | OP_W	  ADDRMETH_T | OPTYPE_d | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_T | OPTYPE_d | OP_W	  ADDRMETH_R | OPTYPE_d | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movaps"	  0	  0	  0	 0 	0
+INSN 0	INS_MOV	ADDRMETH_W | OPTYPE_ps | OP_W	  ADDRMETH_V | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movaps"	  0	  0	  0	 0 	0
+INSN 0	INS_MOV	ADDRMETH_V | OPTYPE_ps | OP_W	ADDRMETH_Q | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM2 | isa_GP	"cvtpi2ps"	0	0	0	0	0
+INSN 0	  INS_MOV	  ADDRMETH_W | OPTYPE_ps | OP_W	  ADDRMETH_V | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movntps"	  0	  0	  0	 0 	0
+INSN 0	INS_MOV	ADDRMETH_P | OPTYPE_q | OP_W	ADDRMETH_W | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM2 | isa_GP	"cvttps2pi"	0	0	0	0	0
+INSN 0	INS_MOV	ADDRMETH_P | OPTYPE_q | OP_W 	ADDRMETH_W | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM2 | isa_GP	"cvtps2pi"	0	0	0	0	0
+INSN 0	  INS_OTHER	  ADDRMETH_V | OPTYPE_ss | OP_W	  ADDRMETH_W | OPTYPE_ss | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "ucomiss"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_OTHER	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ss | OP_W	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "comiss"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_GP	  "wrmsr"	  0	  0	  0	 0 	52
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_GP	  "rdtsc"	  0	  0	  0	 0 	40
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_GP	  "rdmsr"	  0	  0	  0	 0 	38
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "rdpmc"	  0	  0	  0	 0 	39
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "sysenter"	  0	  0	  0	 0 	50
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "sysexit"	  0	  0	  0	 0 	51
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovo"	  0	  0	  0	 INS_TEST_OFLOW 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovno"	  0	  0	  0	 INS_TEST_NOFLOW 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovc"	  0	  0	  0	 INS_TEST_CARRY 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovnc"	  0	  0	  0	 INS_TEST_NCARRY 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovz"	  0	  0	  0	 INS_TEST_ZERO 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovnz"	  0	  0	  0	 INS_TEST_NZERO 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovbe"	  0	  0	  0	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmova"	  0	  0	  0	 INS_TEST_NZERO|INS_TEST_NCARRY 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovs"	  0	  0	  0	 INS_TEST_SIGN 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovns"	  0	  0	  0	 INS_TEST_NSIGN 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovp"	  0	  0	  0	 INS_TEST_PARITY 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovnp"	  0	  0	  0	 INS_TEST_NPARITY 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovl"	  0	  0	  0	 INS_TEST_SFNEOF 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovge"	  0	  0	  0	 INS_TEST_SFEQOF 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovle"	  0	  0	  0	 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_PENTPRO | isa_GP	  "cmovg"	  0	  0	  0	 INS_TEST_NZERO|INS_TEST_SFEQOF 	0
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_d | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movmskps"	  0	  0	  0	 0 	0
+INSN 0	  INS_ARITH	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "sqrtps"	  0	  0	  0	 0 	0
+INSN 0	  INS_ARITH	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "rsqrtps"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "rcpps"	  0	  0	  0	 0 	0
+INSN 0	  INS_AND	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "andps"	  0	  0	  0	 0 	0
+INSN 0	  INS_AND	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "andnps"	  0	  0	  0	 0 	0
+INSN 0	  INS_OR	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "orps"	  0	  0	  0	 0 	0
+INSN 0	  INS_XOR	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "xorps"	  0	  0	  0	 0 	0
+INSN 0	  INS_ADD	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "addps"	  0	  0	  0	 0 	0
+INSN 0	  INS_MUL	  ADDRMETH_V | OPTYPE_ps | OP_R	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "mulps"	  0	  0	  0	 0 	0
+INSN 0	INS_MOV	ADDRMETH_V | OPTYPE_pd	ADDRMETH_W | OPTYPE_q	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtps2pd"	0	0	0	0	0
+INSN 0	INS_MOV	ADDRMETH_V | OPTYPE_ps | OP_W	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtdq2ps"	0	0	0	0	0
+INSN 0	  INS_SUB	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "subps"	  0	  0	  0	 0 	0
+INSN 0	  INS_ARITH	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "minps"	  0	  0	  0	 0 	0
+INSN 0	  INS_DIV	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "divps"	  0	  0	  0	 0 	0
+INSN 0	  INS_ARITH	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "maxps"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "punpcklbw"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "punpcklwd"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "punpckldq"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "packsswb"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pcmpgtb"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pcmpgtw"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pcmpgtd"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "packuswb"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "punpckhbw"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "punpckhwd"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "punpckhdq"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "packssdw"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_P | OPTYPE_d | OP_W	  ADDRMETH_E | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "movd"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "movq"	  0	  0	  0	 0 	0
+INSN 0	INS_MOV	ADDRMETH_P | OPTYPE_q | OP_W	ADDRMETH_Q | OPTYPE_q | OP_R	ADDRMETH_I | OPTYPE_b | OP_R	cpu_PENTIUM2 | isa_GP	"pshufw"	0	0	0	0	0
+INSN idx_0F71	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  ""	  0	  0	  0	 0 	0
+INSN idx_0F72	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  ""	  0	  0	  0	 0 	0
+INSN idx_0F73	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pcmpeqb"	  0	  0	  0	 0 	0
+INSN 0	  INS_CMP	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pcmpeqw"	  0	  0	  0	 0 	0
+INSN 0	  INS_CMP	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pcmpeqd"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "emms"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_E | OPTYPE_d | OP_W	  ADDRMETH_P | OPTYPE_d | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "movd"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_Q | OPTYPE_q | OP_W	  ADDRMETH_P | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "movq"	  0	  0	  0	 0 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jo"	  0	  0	  0	 INS_TEST_OFLOW 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jno"	  0	  0	  0	 INS_TEST_NOFLOW 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jc"	  0	  0	  0	 INS_TEST_CARRY 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jnc"	  0	  0	  0	 INS_TEST_NCARRY 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jz"	  0	  0	  0	 INS_TEST_ZERO 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jnz"	  0	  0	  0	 INS_TEST_NZERO 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jbe"	  0	  0	  0	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "ja"	  0	  0	  0	 INS_TEST_NCARRY|INS_TEST_NZERO 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "js"	  0	  0	  0	 INS_TEST_SIGN 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jns"	  0	  0	  0	 INS_TEST_NSIGN 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jpe"	  0	  0	  0	 INS_TEST_PARITY 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jpo"	  0	  0	  0	 INS_TEST_NPARITY 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jl"	  0	  0	  0	 INS_TEST_SFNEOF 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jge"	  0	  0	  0	 INS_TEST_SFEQOF 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jle"	  0	  0	  0	 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 	0
+INSN 0	  INS_BRANCHCC	  ADDRMETH_J | OPTYPE_v | OP_X | OP_SIGNED	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jg"	  0	  0	  0	 INS_TEST_NZERO|INS_TEST_SFEQOF 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "seto"	  0	  0	  0	 INS_TEST_OFLOW 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setno"	  0	  0	  0	 INS_TEST_OFLOW 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setc"	  0	  0	  0	 INS_TEST_CARRY 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setnc"	  0	  0	  0	 INS_TEST_NCARRY 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setz"	  0	  0	  0	 INS_TEST_ZERO 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setnz"	  0	  0	  0	 INS_TEST_NZERO 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setbe"	  0	  0	  0	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "seta"	  0	  0	  0	 INS_TEST_NCARRY|INS_TEST_NZERO 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "sets"	  0	  0	  0	 INS_TEST_SIGN 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setns"	  0	  0	  0	 INS_TEST_NSIGN 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setpe"	  0	  0	  0	 INS_TEST_PARITY 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setpo"	  0	  0	  0	 INS_TEST_NPARITY 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setl"	  0	  0	  0	 INS_TEST_SFNEOF 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setge"	  0	  0	  0	 INS_TEST_SFEQOF 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setle"	  0	  0	  0	 INS_TEST_ZERO|INS_TEST_OR|INS_TEST_SFNEOF 	0
+INSN 0	  INS_MOVCC	  ADDRMETH_E | OPTYPE_b | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "setg"	  0	  0	  0	 INS_TEST_NZERO|INS_TEST_SFEQOF 	0
+INSN 0	  INS_PUSH	  ADDRMETH_RS | OPTYPE_w | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  4	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RS | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  4	  0	  0	 0 	33
+INSN 0	  INS_CPUID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_GP	  "cpuid"	  0	  0	  0	 0 	10
+INSN 0	  INS_BITTEST	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "bt"	  0	  0	  0	 INS_SET_CARRY 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  cpu_80386 | isa_GP	  "shld"	  0	  0	  0	 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ADDRMETH_I | OP_R | OPTYPE_b | ADDRMETH_RR	  cpu_80386 | isa_GP	  "shld"	  0	  0	  1	 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_PUSH	  ADDRMETH_RS | OPTYPE_w | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  5	  0	  0	 0 	33
+INSN 0	  INS_POP	  ADDRMETH_RS | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "pop"	  5	  0	  0	 0 	33
+INSN 0	  INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "rsm"	  0	  0	  0	 INS_SET_ALL|INS_SET_DIR 	42
+INSN 0	  INS_BITTEST	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "bts"	  0	  0	  0	 INS_SET_CARRY 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  cpu_80386 | isa_GP	  "shrd"	  0	  0	  0	 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ADDRMETH_RR | OP_R | OPTYPE_b 	  cpu_80386 | isa_GP	  "shrd"	  0	  0	  1	 INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN idx_0FAE	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_MUL	  ADDRMETH_G | OPTYPE_v | OP_SIGNED | OP_R | OP_W	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "imul"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_CARRY 	
+INSN 0	  INS_XCHGCC	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_G | OPTYPE_b | OP_W	  ARG_NONE	  cpu_80486 | isa_GP	  "cmpxchg"	  0	  0	  0	 INS_SET_ALL 	8
+INSN 0	  INS_XCHGCC	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_G | OPTYPE_v | OP_W	  ARG_NONE	  cpu_80486 | isa_GP	  "cmpxchg"	  0	  0	  0	 INS_SET_ALL 	7
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_v | OP_W	ADDRMETH_M | OPTYPE_p | OP_W	  ARG_NONE	  cpu_80386 | isa_GP	  "lss"	  0	  0	  0	 0 	0
+INSN 0	  INS_BITTEST	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "btr"	  0	  0	  0	 INS_SET_CARRY 	0
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_v | OP_W	ADDRMETH_M | OPTYPE_p | OP_W	  ARG_NONE	  cpu_80386 | isa_GP	  "lfs"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_v | OP_W	ADDRMETH_M | OPTYPE_p | OP_W	  ARG_NONE	  cpu_80386 | isa_GP	  "lgs"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "movzx"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_w | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "movzx"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_UNKNOWN	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "ud1"	  0	  0	  0	 0 	0
+INSN idx_0FBA	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_BITTEST	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_G | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "btc"	  0	  0	  0	 INS_SET_CARRY 	0
+INSN 0	  INS_BITTEST	  ADDRMETH_G | OPTYPE_v | OP_R | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "bsf"	  0	  0	  0	 INS_SET_ZERO 	0
+INSN 0	  INS_BITTEST	  ADDRMETH_G | OPTYPE_v | OP_R | OP_W	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "bsr"	  0	  0	  0	 INS_SET_ZERO 	0
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "movsx"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_G | OPTYPE_v | OP_W	  ADDRMETH_E | OPTYPE_w | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "movsx"	  0	  0	  0	 0 	0
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_G | OPTYPE_b | OP_W	  ARG_NONE	  cpu_80486 | isa_GP	  "xadd"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "xadd"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	INS_CMP	ADDRMETH_V | OPTYPE_ps | OP_R	ADDRMETH_W | OPTYPE_ps | OP_R	ADDRMETH_I | OPTYPE_b | OP_R	cpu_PENTIUM4 | isa_GP	"cmpps"	0	0	0	0	0
+INSN 0	INS_MOV	ADDRMETH_M | OPTYPE_d | OP_W	ADDRMETH_G | OPTYPE_d | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movnti"	0	0	0	0	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_E | OPTYPE_w | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  cpu_PENTIUM2 | isa_GP	  "pinsrw"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_G | OPTYPE_d | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  cpu_PENTIUM2 | isa_GP	  "pextrw"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_V | OPTYPE_ps | OP_W	  ADDRMETH_W | OPTYPE_ps | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  cpu_PENTIUM2 | isa_GP	  "shufps"	  0	  0	  0	 0 	0
+INSN 0	INS_XCHGCC	ADDRMETH_M | OPTYPE_q | OP_R | OP_W	ARG_NONE	ARG_NONE	cpu_PENTIUM | isa_GP	"cmpxchg8b"	0	0	0	0	9
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_d | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "bswap"	  0	  0	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_d | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "bswap"	  1	  0	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_d | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "bswap"	  2	  0	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_d | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "bswap"	  3	  0	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_d | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "bswap"	  4	  0	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_d | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "bswap"	  5	  0	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_d | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "bswap"	  6	  0	  0	 0 	0
+INSN 0	  INS_XCHG	  ADDRMETH_RR | OPTYPE_d | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "bswap"	  7	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrlw"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrld"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrlq"	  0	  0	  0	 0 	0
+INSN 0	INS_ADD	ADDRMETH_P | OPTYPE_q | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"paddq"	0	0	0	0	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pmullw"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_G | OPTYPE_d | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "pmovmskb"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psubusb"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psubusw"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "pminub"	  0	  0	  0	 0 	0
+INSN 0	  INS_AND	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pand"	  0	  0	  0	 0 	0
+INSN 0	  INS_ADD	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "paddusb"	  0	  0	  0	 0 	0
+INSN 0	  INS_ADD	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "paddusw"	  0	  0	  0	 0 	0
+INSN 0	  INS_ARITH	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "pmaxub"	  0	  0	  0	 0 	0
+INSN 0	  INS_AND	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pandn"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "pavgb"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psraw"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrad"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "pavgw"	  0	  0	  0	 0 	0
+INSN 0	  INS_MUL	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "pmulhuw"	  0	  0	  0	 0 	0
+INSN 0	  INS_MUL	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pmulhw"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_W | OPTYPE_q | OP_W	  ADDRMETH_V | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movntq"	  0	  0	  0	 0 	0
+INSN 0	  INS_SUB	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psubsb"	  0	  0	  0	 0 	0
+INSN 0	  INS_SUB	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psubsw"	  0	  0	  0	 0 	0
+INSN 0	  INS_ARITH	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "pminsw"	  0	  0	  0	 0 	0
+INSN 0	  INS_OR	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "por"	  0	  0	  0	 0 	0
+INSN 0	  INS_ADD	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "paddsb"	  0	  0	  0	 0 	0
+INSN 0	  INS_ADD	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "paddsw"	  0	  0	  0	 0 	0
+INSN 0	  INS_ARITH	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "pmaxsw"	  0	  0	  0	 0 	0
+INSN 0	  INS_XOR	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pxor"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psllw"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pslld"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psllq"	  0	  0	  0	 0 	0
+INSN 0	INS_MUL	ADDRMETH_P | OPTYPE_q | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pmuludq"	0	0	0	0	0
+INSN 0	  INS_ADD	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pmaddwd"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "psadbw"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_P | OPTYPE_pi | OP_W	  ADDRMETH_Q | OPTYPE_pi | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "maskmovq"	  0	  0	  0	 0 	0
+INSN 0	  INS_SUB	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psubb"	  0	  0	  0	 0 	0
+INSN 0	  INS_SUB	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psubw"	  0	  0	  0	 0 	0
+INSN 0	  INS_SUB	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psubd"	  0	  0	  0	 0 	0
+INSN 0	INS_SUB	ADDRMETH_P | OPTYPE_q | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psubq"	0	0	0	0	0
+INSN 0	  INS_ADD	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "paddb"	  0	  0	  0	 0 	0
+INSN 0	  INS_ADD	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "paddw"	  0	  0	  0	 0 	0
+INSN 0	  INS_ADD	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_Q | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "paddd"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_660F	tbl_prefix	shift 0	mask 255	minlim 16	maxlim 255	"SIMD 66 Two-byte Opcodes"
+#______________________________________________________________________________
+INSN 0	INS_MOV	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movupd"	0	0	0	0	0
+INSN 0	INS_MOV	ADDRMETH_W | OPTYPE_pd | OP_R	ADDRMETH_V | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movupd"	0	0	0	0	0
+INSN 0	INS_MOV	ADDRMETH_V | OPTYPE_q | OP_R	ADDRMETH_M | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movlpd"	0	0	0	0	0
+INSN 0	INS_MOV	ADDRMETH_M | OPTYPE_q | OP_R	ADDRMETH_V | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movlpd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"unpcklpd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"unpckhpd"	0	0	0	0	0
+INSN 0	INS_MOV	ADDRMETH_V | OPTYPE_q | OP_R	ADDRMETH_M | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movhpd"	0	0	0	0	0
+INSN 0	INS_MOV	ADDRMETH_M | OPTYPE_q | OP_R	ADDRMETH_V | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movhpd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_MOV	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movapd"	0	0	0	0	0
+INSN 0	INS_MOV	ADDRMETH_W | OPTYPE_pd | OP_R	ADDRMETH_V | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movapd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_Q | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtpi2pd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_M | OPTYPE_pd | OP_R	ADDRMETH_V | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movntpd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_P | OPTYPE_q | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvttpd2pi"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_P | OPTYPE_q | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtpd2pi"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"ucomisd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"comisd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_G | OPTYPE_d | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movmskpd"	0	0	0	0	0
+INSN 0	INS_FSQRT	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"sqrtpd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_AND	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"andpd"	0	0	0	0	0
+INSN 0	INS_AND	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"andnpd"	0	0	0	0	0
+INSN 0	INS_OR	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"orpd"	0	0	0	0	0
+INSN 0	INS_XOR	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"xorpd"	0	0	0	0	0
+INSN 0	INS_ADD	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"addpd"	0	0	0	0	0
+INSN 0	INS_MUL	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"mulpd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ps | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtpd2ps"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_ps | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtps2dq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"subpd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"minpd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"divpd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"maxpd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"punpcklbw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"punpcklwd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"punpckldq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"packsswb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pcmpgtb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pcmpgtw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pcmpgtd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"packuswb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_Q | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"punpckhbw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_Q | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"punpckhwd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_Q | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"punpckhdq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_Q | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"packssdw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"punpcklqdq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"punpckhqdq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_d | OP_R	ADDRMETH_E | OPTYPE_d | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movdqa"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ADDRMETH_I | OPTYPE_b | OP_R	cpu_PENTIUM4 | isa_GP	"pshufd"	0	0	0	0	0
+INSN idx_660F71	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN idx_660F72	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN idx_660F73	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pcmpeqb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pcmpeqw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pcmpeqd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"haddpd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"hsubpd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_E | OPTYPE_d | OP_R	ADDRMETH_V | OPTYPE_d | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_W | OPTYPE_dq | OP_R	ADDRMETH_V | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movdqa"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ADDRMETH_I | OPTYPE_b | OP_R	cpu_PENTIUM4 | isa_GP	"cmppd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_w | OP_R	ADDRMETH_E | OPTYPE_w | OP_R	ADDRMETH_I | OPTYPE_b | OP_R	cpu_PENTIUM4 | isa_GP	"pinsrw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_G | OPTYPE_w | OP_R	ADDRMETH_W | OPTYPE_w | OP_R	ADDRMETH_I | OPTYPE_b | OP_R	cpu_PENTIUM4 | isa_GP	"pextrw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ADDRMETH_I | OPTYPE_b | OP_R	cpu_PENTIUM4 | isa_GP	"shufpd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"addsubpd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psrlw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psrld"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psrlq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"paddq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pmullw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_W | OPTYPE_q | OP_R	ADDRMETH_V | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_G | OPTYPE_d | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pmovmskb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psubusb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psubusw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pminub"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pand"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"paddusb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"paddusw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pmaxub"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pandn"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pavgb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psraw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psrad"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pavgw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pmulhuw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pmulhw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvttpd2dq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_M | OPTYPE_dq | OP_R	ADDRMETH_V | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movntdq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psubsb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psubsw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pminsw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"por"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"paddsb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"paddsw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pmaxsw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pxor"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psllw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pslld"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psllq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pmuludq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"pmaddwd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psadbw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"maskmovdqu"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psubb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psubw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psubd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"psubq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"paddb"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"paddw"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"paddd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_F20F	tbl_prefix	shift 0	mask 255	minlim 16	maxlim 255	"SIMD F2 Two-byte Opcodes"
+#______________________________________________________________________________
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movsd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_W | OPTYPE_sd | OP_R	ADDRMETH_V | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movsd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_q | OP_R	ADDRMETH_W | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movddup"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_E | OPTYPE_d | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtsi2sd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_G | OPTYPE_d | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvttsd2si"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_G | OPTYPE_d | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtsd2si"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"sqrtsd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"addsd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"mulsd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtsd2ss"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"subsd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"minsd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"divsd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"maxsd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ADDRMETH_I | OPTYPE_b | OP_R	cpu_PENTIUM4 | isa_GP	"pshuflw"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ps | OP_R	ADDRMETH_W | OPTYPE_ps | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"haddps"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ps | OP_R	ADDRMETH_W | OPTYPE_ps | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"hsubps"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_sd | OP_R	ADDRMETH_I | OPTYPE_b | OP_R	cpu_PENTIUM4 | isa_GP	"cmpsd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ps | OP_R	ADDRMETH_W | OPTYPE_ps | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"addsubps"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_P | OPTYPE_q | OP_R	ADDRMETH_W | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movdq2q"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_pd | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtpd2dq"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_M | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"lddqu"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_F30F	tbl_prefix	shift 0	mask 255	minlim 16	maxlim 255	"SIMD F3 Two-byte Opcodes"
+#______________________________________________________________________________
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movss"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_W | OPTYPE_ss | OP_R	ADDRMETH_V | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movss"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ps | OP_R	ADDRMETH_W | OPTYPE_ps | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movsldup"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ps | OP_R	ADDRMETH_W | OPTYPE_ps | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movshdup"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_E | OPTYPE_d | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtsi2ss"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_G | OPTYPE_d | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvttss2si"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_G | OPTYPE_d | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtss2si"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"sqrtss"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"rsqrtss"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"rcpss"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"addss"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"mulss"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_sd | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtss2sd"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_ps | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvttps2dq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"subss"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"minss"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"divss"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"maxss"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movdqu"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_W | OPTYPE_dq | OP_R	ADDRMETH_I | OPTYPE_b | OP_R	cpu_PENTIUM4 | isa_GP	"pshufhw"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_q | OP_R	ADDRMETH_W | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movq"	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_W | OPTYPE_dq | OP_R	ADDRMETH_V | OPTYPE_dq | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movdqu"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_ss | OP_R	ADDRMETH_W | OPTYPE_ss | OP_R	ADDRMETH_I | OPTYPE_b | OP_R	cpu_PENTIUM4 | isa_GP	"cmpss"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_dq | OP_R	ADDRMETH_Q | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movq2dq"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_UNKNOWN	ADDRMETH_V | OPTYPE_pd | OP_R	ADDRMETH_W | OPTYPE_q | OP_R	ARG_NONE	cpu_PENTIUM4 | isa_GP	"cvtdq2pd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	""	0	0	0	0	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_0F00	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 6"
+#______________________________________________________________________________
+INSN 0	  INS_SYSTEM	  ADDRMETH_E | OPTYPE_w | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "sldt"	  0	  0	  0	 0 	46
+INSN 0	  INS_SYSTEM	  ADDRMETH_E | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "str"	  0	  0	  0	 0 	49
+INSN 0	  INS_SYSTEM	  ADDRMETH_E | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lldt"	  0	  0	  0	 0 	29
+INSN 0	  INS_SYSTEM	  ADDRMETH_E | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "ltr"	  0	  0	  0	 0 	32
+INSN 0	  INS_SYSTEM	  ADDRMETH_E | OPTYPE_w | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "verr"	  0	  0	  0	 INS_SET_ZERO 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_E | OPTYPE_w | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "verw"	  0	  0	  0	 INS_SET_ZERO 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_0F01	tbl_extension	shift 3	mask 31	minlim 0	maxlim 31	"Group 7"
+#______________________________________________________________________________
+# Mod 00
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "sgdt"	  0	  0	  0	 0 	44
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "sidt"	  0	  0	  0	 0 	45
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lgdt"	  0	  0	  0	 0 	27
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lidt"	  0	  0	  0	 0 	28
+INSN 0	  INS_SMSW	  ADDRMETH_E | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "smsw"	  0	  0	  0	 0 	47
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_LMSW	  ADDRMETH_E | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lmsw"	  0	  0	  0	 0 	30
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_b | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "invlpg"	  0	  0	  0	 0 	0
+# Mod 01
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "sgdt"	  0	  0	  0	 0 	44
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "sidt"	  0	  0	  0	 0 	45
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lgdt"	  0	  0	  0	 0 	27
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lidt"	  0	  0	  0	 0 	28
+INSN 0	  INS_SMSW	  ADDRMETH_E | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "smsw"	  0	  0	  0	 0 	47
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_LMSW	  ADDRMETH_E | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lmsw"	  0	  0	  0	 0 	30
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_b | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "invlpg"	  0	  0	  0	 0 	0
+# Mod 10
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "sgdt"	  0	  0	  0	 0 	44
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "sidt"	  0	  0	  0	 0 	45
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lgdt"	  0	  0	  0	 0 	27
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_s | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lidt"	  0	  0	  0	 0 	28
+INSN 0	  INS_SMSW	  ADDRMETH_E | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "smsw"	  0	  0	  0	 0 	47
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_LMSW	  ADDRMETH_E | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lmsw"	  0	  0	  0	 0 	30
+INSN 0	  INS_SYSTEM	  ADDRMETH_M | OPTYPE_b | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80486 | isa_GP	  "invlpg"	  0	  0	  0	 0 	0
+# Mod 11
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN idx_0F0111	  0	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_SMSW	  ADDRMETH_E | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "smsw"	  0	  0	  0	 0 	47
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_LMSW	  ADDRMETH_E | OPTYPE_w | OP_W	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "lmsw"	  0	  0	  0	 0 	30
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+# This table is a weird one. In addition to the Reg field *and* the Mod field
+# of the ModR/M byte being used as an opcode extension, this insn uses the
+# R/M field as well.
+TABLE tbl_0F0111	tbl_ext_ext	shift 0	mask 1	minlim 0	maxlim 1	"Monitor/MWait opcode"
+#______________________________________________________________________________
+INSN 0	INS_SYSTEM	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	"monitor"	0	0	0	0	54
+INSN 0	INS_SYSTEM	ARG_NONE	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	"mwait"	0	0	0	0	55
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+# TODO
+TABLE tbl_0F12	tbl_extension	shift 6	mask 3	minlim 0	maxlim 3	"Movlps Opcode"
+# A semi-weird table. This insn mnemonic changes when the Mod field of the
+# ModR/M byte denotes a register.
+#______________________________________________________________________________
+INSN 0	  INS_MOV	  ADDRMETH_V | OPTYPE_q | OP_W	  ADDRMETH_M | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movlps"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_V | OPTYPE_q | OP_W	  ADDRMETH_M | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movlps"	  0	  0	  0	 0 	0
+INSN 0	  INS_MOV	  ADDRMETH_V | OPTYPE_q | OP_W	  ADDRMETH_M | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movlps"	  0	  0	  0	 0 	0
+INSN 0	INS_MOV	ADDRMETH_V | OPTYPE_ps | OP_R | OP_W	ADDRMETH_W | OPTYPE_ps | OP_R 	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movhlps"	0	0	0	0	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+# TODO
+TABLE tbl_0F16	tbl_extension	shift 6	mask 3	minlim 0	maxlim 3	"Movhps Opcode"
+# Insn mnemonic changes when the Mod field denotes a register.
+#______________________________________________________________________________
+INSN 0	  INS_OTHER	  ADDRMETH_V | OPTYPE_q | OP_W	  ADDRMETH_M | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movhps"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_V | OPTYPE_q | OP_W	  ADDRMETH_M | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movhps"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_V | OPTYPE_q | OP_W	  ADDRMETH_M | OPTYPE_q | OP_R	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "movhps"	  0	  0	  0	 0 	0
+INSN 0	INS_MOV	ADDRMETH_V | OPTYPE_ps | OP_R | OP_W	ADDRMETH_W | OPTYPE_ps | OP_R 	ARG_NONE	cpu_PENTIUM4 | isa_GP	"movlhps"	0	0	0	0	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_0F18	tbl_extension	shift 3	mask 31	minlim 0	maxlim 19	"Group 16"
+#______________________________________________________________________________
+# Mod 00
+INSN 0	  INS_SYSTEM	   OP_W | OPTYPE_b | ADDRMETH_M	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetchnta"	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_RT | OPTYPE_d | OP_W	ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetcht0"	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_RT | OPTYPE_d | OP_W	ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetcht1"	  1	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_RT | OPTYPE_d | OP_W	ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetcht2"	  2	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 10
+INSN 0	  INS_SYSTEM	   OP_W | OPTYPE_b | ADDRMETH_M	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetchnta"	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_RT | OPTYPE_d | OP_W	ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetcht0"	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_RT | OPTYPE_d | OP_W	ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetcht1"	  1	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_RT | OPTYPE_d | OP_W	ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetcht2"	  2	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 01
+INSN 0	  INS_SYSTEM	   OP_W | OPTYPE_b | ADDRMETH_M	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetchnta"	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_RT | OPTYPE_d | OP_W	ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetcht0"	  0	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_RT | OPTYPE_d | OP_W	ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetcht1"	  1	  0	  0	 0 	0
+INSN 0	  INS_SYSTEM	  ADDRMETH_RT | OPTYPE_d | OP_W	ARG_NONE	  ARG_NONE	  cpu_PENTIUM2 | isa_GP	  "prefetcht2"	  2	  0	  0	 0 	0
+# table truncated
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_0F71	tbl_extension	shift 3	mask 31	minlim 0	maxlim 31	"Group 12"
+#______________________________________________________________________________
+# Mod 00
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 01
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 10
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 11
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrlw"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psraw"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psllw"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_660F71	tbl_extension	shift 3	mask 31	minlim 0	maxlim 31	"Group 12 SSE"
+#______________________________________________________________________________
+# Mod 00
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 01
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 10
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 11
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_dq | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrlw"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_dq | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psraw"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_dq | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psllw"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_0F72	tbl_extension	shift 3	mask 31	minlim 0	maxlim 31	"Group 13"
+#______________________________________________________________________________
+# Mod 00
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 01
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 10
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 11
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrld"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrad"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pslld"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+#______________________________________________________________________________
+TABLE tbl_660F72	tbl_extension	shift 3	mask 31	minlim 0	maxlim 31	"Group 13 SSE"
+# Mod 00
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 01
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 10
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 11
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_W | OPTYPE_dq | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrld"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_W | OPTYPE_dq | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrad"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_W | OPTYPE_dq | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pslld"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_0F73	tbl_extension	shift 0	mask 0	minlim 0	maxlim 0	"Group 14"
+#______________________________________________________________________________
+# Mod 00
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 01
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 10
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 11
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrlq"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_P | OPTYPE_q | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psllq"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+# TODO: last 2 opcodes
+#______________________________________________________________________________
+TABLE tbl_660F73	tbl_extension	shift 3	mask 31	minlim 0	maxlim 31	"Group 14 SSE"
+#______________________________________________________________________________
+# Mod 00
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 01
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 10
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 11
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_W | OPTYPE_dq | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrlq"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_W | OPTYPE_dq | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psrldq"	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_W | OPTYPE_dq | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "psllq"	  0	  0	  0	 0 	0
+INSN 0	  INS_OTHER	  ADDRMETH_W | OPTYPE_dq | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "pslldq"	  0	  0	  0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+#TODO: fill in opcodes
+TABLE tbl_0FAE	tbl_extension	shift 3	mask 31	minlim 0	maxlim 31	"Group 15"
+#______________________________________________________________________________
+# Mod 00
+INSN 0	INS_FPU	  ADDRMETH_E | OPTYPE_fx | OP_W	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "fxsave"	  0	  0	  0	 0 	0
+INSN 0	INS_FPU	  ADDRMETH_E | OPTYPE_fx | OP_R	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "fxrstor"	  0	  0	  0	 0 	0
+INSN 0	INS_SYSTEM	  ADDRMETH_E | OPTYPE_d | OP_R	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2	  "ldmxcsr"	  0	  0	  0	 0 	25
+INSN 0	INS_SYSTEM	  ADDRMETH_E | OPTYPE_d | OP_W	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2	  "stmxcsr"	  0	  0	  0 	 0	48
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_SYSTEM	ADDRMETH_M | OPTYPE_b | OP_R	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	"clflush"	0	0	0	0	0
+# Mod 01
+INSN 0	INS_FPU	  ADDRMETH_E | OPTYPE_fx | OP_W	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "fxsave"	  0	  0	  0	 0 	0
+INSN 0	INS_FPU	  ADDRMETH_E | OPTYPE_fx | OP_R	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "fxrstor"	  0	  0	  0	 0 	0
+INSN 0	INS_SYSTEM	  ADDRMETH_E | OPTYPE_d | OP_R	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2	  "ldmxcsr"	  0	  0	  0	 0 	25
+INSN 0	INS_SYSTEM	  ADDRMETH_E | OPTYPE_d | OP_W	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2	  "stmxcsr"	  0	  0	  0 	 0	48
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_SYSTEM	ADDRMETH_M | OPTYPE_b | OP_R	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	"clflush"	0	0	0	0	0
+# Mod 10
+INSN 0	INS_FPU	  ADDRMETH_E | OPTYPE_fx | OP_W	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "fxsave"	  0	  0	  0	 0 	0
+INSN 0	INS_FPU	  ADDRMETH_E | OPTYPE_fx | OP_R	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_MMX	  "fxrstor"	  0	  0	  0	 0 	0
+INSN 0	INS_SYSTEM	  ADDRMETH_E | OPTYPE_d | OP_R	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2	  "ldmxcsr"	  0	  0	  0	 0 	25
+INSN 0	INS_SYSTEM	  ADDRMETH_E | OPTYPE_d | OP_W	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM2	  "stmxcsr"	  0	  0	  0 	 0	48
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_SYSTEM	ADDRMETH_M | OPTYPE_b | OP_R	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	"clflush"	0	0	0	0	0
+# Mod 11
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  "lfence"	  0	  0	  0	 0 	0
+INSN 0	INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  "mfence"	  0	  0	  0	 0 	0
+INSN 0	INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  "sfence"	  0	  0	  0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_0FBA	tbl_extension	shift 3	mask 7	minlim 4	maxlim 7	"Group 8"
+#______________________________________________________________________________
+INSN 0	  INS_BITTEST	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "bt"	  0	  0	  0	 INS_SET_CARRY 	0
+INSN 0	  INS_BITTEST	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "bts"	  0	  0	  0	 INS_SET_CARRY 	0
+INSN 0	  INS_BITTEST	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "btr"	  0	  0	  0	 INS_SET_CARRY 	0
+INSN 0	  INS_BITTEST	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "btc"	  0	  0	  0   	 INS_SET_CARRY 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_0FC7	tbl_extension	shift 3	mask 31	minlim 0	maxlim 17	"Group 9"
+#______________________________________________________________________________
+# Mod 00
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_XCHGCC	  ADDRMETH_M | OPTYPE_q | OP_W	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_GP	  "cmpxch8b"	  0	  0	  0   	 0 	9
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 01
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_XCHGCC	  ADDRMETH_M | OPTYPE_q | OP_W	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_GP	  "cmpxch8b"	  0	  0	  0   	 0 	9
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+# Mod 10
+INSN 0	INS_INVALID	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  ""	  0	  0	  0	 0 	0
+INSN 0	  INS_XCHGCC	  ADDRMETH_M | OPTYPE_q | OP_W	  ARG_NONE	  ARG_NONE	  cpu_PENTIUM | isa_GP	  "cmpxch8b"	  0	  0	  0   	 0 	9
+# Table truncated
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_0FB9	tbl_extension	shift 3	mask 7	minlim 0	maxlim 0	"Group 10"
+#______________________________________________________________________________
+INSN 0	INS_SYSTEM	  ARG_NONE	  ARG_NONE	  ARG_NONE	  0	  "fxsave"	  0	  0	  0	 0 	0
+# Table truncated
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_C6	tbl_extension	shift 3	mask 7	minlim 0	maxlim 0	"Group 11a"
+#______________________________________________________________________________
+INSN 0	  INS_MOV	  ADDRMETH_E | OPTYPE_b | OP_W	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+# Table truncated
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_C7	tbl_extension	shift 3	mask 7	minlim 0	maxlim 0	"Group 11b"
+INSN 0	  INS_MOV	  ADDRMETH_E | OPTYPE_v | OP_W	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mov"	  0	  0	  0	 0 	0
+# Table truncated
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_80	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 1a"
+#______________________________________________________________________________
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "add"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_OR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "or"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "adc"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sbb"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_AND	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "and"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sub"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_XOR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xor"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_CMP	  ADDRMETH_E | OPTYPE_b | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmp"	  0	  0	  0   	 INS_SET_ALL 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_81	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 1b"
+#______________________________________________________________________________
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "add"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_OR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "or"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "adc"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sbb"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_AND	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "and"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sub"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_XOR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xor"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_CMP	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmp"	  0	  0	  0   	 INS_SET_ALL 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_82	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 1c"
+#______________________________________________________________________________
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "add"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_OR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "or"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "adc"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sbb"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_AND	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "and"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sub"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_XOR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xor"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_CMP	  ADDRMETH_E | OPTYPE_b | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmp"	  0	  0	  0   	 INS_SET_ALL 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_83	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 1d"
+#______________________________________________________________________________
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "add"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_OR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "or"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_ADD	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "adc"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sbb"	  0	  0	  0	 INS_SET_ALL|INS_TEST_CARRY 	0
+INSN 0	  INS_AND	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "and"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SUB	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sub"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_XOR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "xor"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_CMP	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "cmp"	  0	  0	  0   	 INS_SET_ALL 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_C0	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 2a"
+#______________________________________________________________________________
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rol"	  0	  0	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "ror"	  0	  0	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcl"	  0	  0	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcr"	  0	  0	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shl"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shr"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sal"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sar"	  0	  0	  0   	 INS_SET_ALL 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_C1	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 2b"
+#______________________________________________________________________________
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rol"	  0	  0	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "ror"	  0	  0	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcl"	  0	  0	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcr"	  0	  0	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shl"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shr"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sal"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_I | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sar"	  0	  0	  0   	 INS_SET_ALL 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_D0	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 2c"
+#______________________________________________________________________________
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_II | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rol"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_II | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "ror"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_II | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcl"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_II | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcr"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_II | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shl"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_II | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shr"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_II | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sal"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_II | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sar"	  0	  1	  0   	 INS_SET_ALL 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_D1	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 2d"
+#______________________________________________________________________________
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_II | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rol"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_II | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "ror"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_II | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcl"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_II | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcr"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_II | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shl"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_II | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shr"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_II | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sal"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_II | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sar"	  0	  1	  0   	 INS_SET_ALL 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_D2	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 2e"
+#______________________________________________________________________________
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rol"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "ror"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcl"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcr"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shl"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shr"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sal"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sar"	  0	  1	  0   	 INS_SET_ALL 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_D3	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 2f"
+#______________________________________________________________________________
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rol"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "ror"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW 	0
+INSN 0	  INS_ROL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcl"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_ROR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "rcr"	  0	  1	  0	 INS_SET_CARRY|INS_SET_OFLOW|INS_TEST_CARRY 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shl"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "shr"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHL	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sal"	  0	  1	  0	 INS_SET_ALL 	0
+INSN 0	  INS_SHR	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ADDRMETH_RR | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "sar"	  0	  1	  0   	 INS_SET_ALL 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_F6	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 3a"
+#______________________________________________________________________________
+INSN 0	  INS_TEST	  ADDRMETH_E | OPTYPE_b | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "test"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_TEST	  ADDRMETH_E | OPTYPE_b | OP_R	  ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "test"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_NOT	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "not"	  0	  0	  0	 0 	0
+INSN 0	  INS_NEG	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "neg"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_MUL	  OPTYPE_b | ADDRMETH_RR | OP_W | OP_R	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mul"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_CARRY 	22
+INSN 0	  INS_MUL	  OPTYPE_b | ADDRMETH_RR | OP_W | OP_SIGNED | OP_R	  ADDRMETH_E | OPTYPE_b | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "imul"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_CARRY 	22
+INSN 0	  INS_DIV	  ADDRMETH_RR | OPTYPE_b | OP_W | OP_R	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "div"	  0	  0	  0	 0 	13
+INSN 0	  INS_DIV	  ADDRMETH_RR | OPTYPE_b | OP_W | OP_R	  ADDRMETH_E | OPTYPE_b | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "idiv"	  0	  0	  0   	 0 	13
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_F7	tbl_extension	shift 3	mask 7	minlim 0	maxlim 7	"Group 3b"
+#______________________________________________________________________________
+INSN 0	  INS_TEST	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "test"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_TEST	  ADDRMETH_E | OPTYPE_v | OP_R	  ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "test"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_NOT	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "not"	  0	  0	  0	 0 	0
+INSN 0	  INS_NEG	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "neg"	  0	  0	  0	 INS_SET_ALL 	0
+INSN 0	  INS_MUL	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "mul"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_CARRY 	23
+INSN 0	  INS_MUL	  ADDRMETH_RR | OPTYPE_v | OP_SIGNED | OP_W | OP_R	  ADDRMETH_E | OPTYPE_v | OP_SIGNED | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "imul"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_CARRY 	23
+INSN 0	  INS_DIV	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "div"	  0	  0	  0	 0 	14
+INSN 0	  INS_DIV	  ADDRMETH_RR | OPTYPE_v | OP_W | OP_R	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  cpu_80386 | isa_GP	  "idiv"	  0	  0	  0	 0 	14
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_FE	tbl_extension	shift 3	mask 7	minlim 0	maxlim 1	"Group 4"
+#______________________________________________________________________________
+INSN 0	  INS_INC	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "inc"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_DEC	  ADDRMETH_E | OPTYPE_b | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "dec"	  0	  0	  0   	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_FF	tbl_extension	shift 3	mask 7	minlim 0	maxlim 6	"Group 5"
+#______________________________________________________________________________
+INSN 0	  INS_INC	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "inc"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_DEC	  ADDRMETH_E | OPTYPE_v | OP_W | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "dec"	  0	  0	  0	 INS_SET_OFLOW|INS_SET_SIGN|INS_SET_ZERO|INS_SET_PARITY 	0
+INSN 0	  INS_CALL	  ADDRMETH_E | OPTYPE_v | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "call"	  0	  0	  0	 0 	3
+INSN 0	  INS_CALL	  ADDRMETH_E | OPTYPE_p | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "callf"	  0	  0	  0	 0 	0
+INSN 0	  INS_BRANCH	  ADDRMETH_E | OPTYPE_v | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jmp"	  0	  0	  0	 0 	0
+INSN 0	  INS_BRANCH	  ADDRMETH_E | OPTYPE_p | OP_X	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "jmpf"	  0	  0	  0	 0 	0
+INSN 0	  INS_PUSH	  ADDRMETH_E | OPTYPE_v | OP_R	  ARG_NONE	  ARG_NONE	  cpu_80386 | isa_GP	  "push"	  0	  0	  0	 0 	33
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_D8	tbl_fpu	shift 3	mask 7	minlim 0	maxlim 191	"FPU D8"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fs|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fs|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fs|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcom"	 0	 0	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	17
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fs|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomp"	 0	 0	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fs|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fs|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fs|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fs|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 0	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_D8C0	tbl_fpu_ext	shift 0	mask 255	minlim 192	maxlim 255	"FPU D8 C0"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 0	 1	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 0	 2	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 0	 3	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 0	 4	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 0	 5	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 0	 6	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 0	 7	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 0	 1	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 0	 2	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 0	 3	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 0	 4	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 0	 5	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 0	 6	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 0	 7	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcom"	 0	 0	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	17
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcom"	 0	 1	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	17
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcom"	 0	 2	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	17
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcom"	 0	 3	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	17
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcom"	 0	 4	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	17
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcom"	 0	 5	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	17
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcom"	 0	 6	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	17
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcom"	 0	 7	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	17
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomp"	 0	 0	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomp"	 0	 1	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomp"	 0	 2	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomp"	 0	 3	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomp"	 0	 4	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomp"	 0	 5	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomp"	 0	 6	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomp"	 0	 7	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 0	 1	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 0	 2	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 0	 3	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 0	 4	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 0	 5	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 0	 6	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 0	 7	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 0	 1	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 0	 2	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 0	 3	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 0	 4	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 0	 5	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 0	 6	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 0	 7	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 0	 1	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 0	 2	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 0	 3	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 0	 4	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 0	 5	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 0	 6	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 0	 7	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 0	 1	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 0	 2	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 0	 3	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 0	 4	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 0	 5	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 0	 6	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 0	 7	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_D9	tbl_fpu	shift 3	mask 7	minlim 0	maxlim 191	"FPU D9"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fs|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld"	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fs|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fst"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fs|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fstp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fv|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fldenv"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fldcw"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fv|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fnstenv"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fnstcw"	 0	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_D9C0	tbl_fpu_ext	shift 0	mask 255	minlim 192	maxlim 255	"FPU D9 C0"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld"	 0	 1	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld"	 0	 2	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld"	 0	 3	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld"	 0	 4	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld"	 0	 5	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld"	 0	 6	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld"	 0	 7	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fxch"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fxch"	 0	 1	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fxch"	 0	 2	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fxch"	 0	 3	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fxch"	 0	 4	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fxch"	 0	 5	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fxch"	 0	 6	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fxch"	 0	 7	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fnop"	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fchs"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fabs"	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ftst"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fxam"	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld1"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fldl2t"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fldl2e"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fldpi"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fldlg2"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fldln2"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fldz"	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "f2xm1"	 0	 0	 0 	 0 	16
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fyl2x"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fptan"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fpatan"	 0	 0	 0 	 0 	18
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fxtract"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fprem1"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdecstp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fincstp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fprem"	 0	 0	 0 	 0 	19
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fyl2xp1"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsqrt"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsincos"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "frndint"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fscale"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsin"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcos"	 0	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_DA	tbl_fpu	shift 3	mask 7	minlim 0	maxlim 191	"FPU DA"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_d|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fiadd"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_d|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fimul"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_d|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ficom"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_d|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ficomp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_d|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fisub"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_d|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fisubr"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_d|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fidiv"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_d|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fidivr"	 0	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_DAC0	tbl_fpu_ext	shift 0	mask 255	minlim 192	maxlim 255	"FPU DA C0"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovb"	 0	 0	 0 	 INS_TEST_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovb"	 0	 1	 0 	 INS_TEST_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovb"	 0	 2	 0 	 INS_TEST_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovb"	 0	 3	 0 	 INS_TEST_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovb"	 0	 4	 0 	 INS_TEST_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovb"	 0	 5	 0 	 INS_TEST_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovb"	 0	 6	 0 	 INS_TEST_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovb"	 0	 7	 0 	 INS_TEST_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmove"	 0	 0	 0 	 INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmove"	 0	 1	 0 	 INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmove"	 0	 2	 0 	 INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmove"	 0	 3	 0 	 INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmove"	 0	 4	 0 	 INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmove"	 0	 5	 0 	 INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmove"	 0	 6	 0 	 INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmove"	 0	 7	 0 	 INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovbe"	 0	 0	 0 	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovbe"	 0	 1	 0 	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovbe"	 0	 2	 0 	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovbe"	 0	 3	 0 	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovbe"	 0	 4	 0 	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovbe"	 0	 5	 0 	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovbe"	 0	 6	 0 	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovbe"	 0	 7	 0 	 INS_TEST_CARRY|INS_TEST_OR|INS_TEST_ZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovu"	 0	 0	 0 	 INS_TEST_PARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovu"	 0	 1	 0 	 INS_TEST_PARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovu"	 0	 2	 0 	 INS_TEST_PARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovu"	 0	 3	 0 	 INS_TEST_PARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovu"	 0	 4	 0 	 INS_TEST_PARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovu"	 0	 5	 0 	 INS_TEST_PARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovu"	 0	 6	 0 	 INS_TEST_PARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcmovu"	 0	 7	 0 	 INS_TEST_PARITY 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucompp"	 0	 0	 0 	 0 	21
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_DB	tbl_fpu	shift 3	mask 7	minlim 0	maxlim 191	"FPU DB"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_d|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fild"	 0	 0	 0 	 0 	0
+INSN 0	INS_FPU	ADDRMETH_M|OPTYPE_d|OP_W	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	"fisttp"	0	0	0	0	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_d|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fist"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_d|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fistp"	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fe|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld"	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fe|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fstp"	 0	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_DBC0	tbl_fpu_ext	shift 0	mask 255	minlim 192	maxlim 255	"FPU DB C0"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnb"	 0	 0	 0 	 INS_TEST_NCARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnb"	 0	 1	 0 	 INS_TEST_NCARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnb"	 0	 2	 0 	 INS_TEST_NCARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnb"	 0	 3	 0 	 INS_TEST_NCARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnb"	 0	 4	 0 	 INS_TEST_NCARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnb"	 0	 5	 0 	 INS_TEST_NCARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnb"	 0	 6	 0 	 INS_TEST_NCARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnb"	 0	 7	 0 	 INS_TEST_NCARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovne"	 0	 0	 0 	 INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovne"	 0	 1	 0 	 INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovne"	 0	 2	 0 	 INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovne"	 0	 3	 0 	 INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovne"	 0	 4	 0 	 INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovne"	 0	 5	 0 	 INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovne"	 0	 6	 0 	 INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovne"	 0	 7	 0 	 INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnbe"	 0	 0	 0 	 INS_TEST_NCARRY|INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnbe"	 0	 1	 0 	 INS_TEST_NCARRY|INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnbe"	 0	 2	 0 	 INS_TEST_NCARRY|INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnbe"	 0	 3	 0 	 INS_TEST_NCARRY|INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnbe"	 0	 4	 0 	 INS_TEST_NCARRY|INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnbe"	 0	 5	 0 	 INS_TEST_NCARRY|INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnbe"	 0	 6	 0 	 INS_TEST_NCARRY|INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnbe"	 0	 7	 0 	 INS_TEST_NCARRY|INS_TEST_NZERO 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnu"	 0	 0	 0 	 INS_TEST_NPARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnu"	 0	 1	 0 	 INS_TEST_NPARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnu"	 0	 2	 0 	 INS_TEST_NPARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnu"	 0	 3	 0 	 INS_TEST_NPARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnu"	 0	 4	 0 	 INS_TEST_NPARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnu"	 0	 5	 0 	 INS_TEST_NPARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnu"	 0	 6	 0 	 INS_TEST_NPARITY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcmovnu"	 0	 7	 0 	 INS_TEST_NPARITY 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fnclex"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fninit"	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomi"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomi"	 0	 1	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomi"	 0	 2	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomi"	 0	 3	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomi"	 0	 4	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomi"	 0	 5	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomi"	 0	 6	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomi"	 0	 7	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcomi"	 0	 0	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcomi"	 0	 1	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcomi"	 0	 2	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcomi"	 0	 3	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcomi"	 0	 4	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcomi"	 0	 5	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcomi"	 0	 6	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_PENTPRO | isa_GP	 "fcomi"	 0	 7	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ 
+TABLE tbl_DC	tbl_fpu	shift 3	mask 7	minlim 0	maxlim 191	"FPU DC"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fd|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fd|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fd|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcom"	 0	 0	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	17
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fd|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomp"	 0	 0	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fd|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fd|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fd|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fd|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 0	 0	 0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_DCC0	tbl_fpu_ext	shift 0	mask 255	minlim 192	maxlim 255	"FPU DC C0"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fadd"	 7	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmul"	 7	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubr"	 7	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsub"	 7	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivr"	 7	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdiv"	 7	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_DD	tbl_fpu	shift 3	mask 7	minlim 0	maxlim 191	"FPU DD"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fd|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fld"	 0	 0	 0 	 0 	0
+INSN 0	INS_FPU	ADDRMETH_M|OPTYPE_q|OP_W	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	"fisttp"	0	0	0	0	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fd|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fst"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fd|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fstp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_ft|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "frstor"	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_ft|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fnsave"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fnstsw"	 0	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_DDC0	tbl_fpu_ext	shift 0	mask 255	minlim 192	maxlim 255	"FPU DD C0"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ffree"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ffree"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ffree"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ffree"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ffree"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ffree"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ffree"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ffree"	 7	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fst"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fst"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fst"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fst"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fst"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fst"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fst"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fst"	 7	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fstp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fstp"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fstp"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fstp"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fstp"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fstp"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fstp"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fstp"	 7	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucom"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucom"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucom"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucom"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucom"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucom"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucom"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucom"	 7	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomp"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomp"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomp"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomp"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomp"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomp"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomp"	 7	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_DE	tbl_fpu	shift 3	mask 7	minlim 0	maxlim 191	"FPU DE"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fiadd"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fimul"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ficom"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "ficomp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fisub"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fisubr"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fidiv"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fidivr"	 0	 0	 0	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_DEC0	tbl_fpu_ext	shift 0	mask 255	minlim 192	maxlim 255	"FPU DE C0"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "faddp"	 0	 0	 0 	 0 	20
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "faddp"	 1	 0	 0 	 0 	20
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "faddp"	 2	 0	 0 	 0 	20
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "faddp"	 3	 0	 0 	 0 	20
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "faddp"	 4	 0	 0 	 0 	20
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "faddp"	 5	 0	 0 	 0 	20
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "faddp"	 6	 0	 0 	 0 	20
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "faddp"	 7	 0	 0 	 0 	20
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmulp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmulp"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmulp"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmulp"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmulp"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmulp"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmulp"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fmulp"	 7	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcompp"	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubrp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubrp"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubrp"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubrp"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubrp"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubrp"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubrp"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubrp"	 7	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubp"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubp"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubp"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubp"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubp"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubp"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fsubp"	 7	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivrp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivrp"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivrp"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivrp"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivrp"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivrp"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivrp"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivrp"	 7	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivp"	 1	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivp"	 2	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivp"	 3	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivp"	 4	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivp"	 5	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivp"	 6	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fdivp"	 7	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_DF	tbl_fpu	shift 3	mask 7	minlim 0	maxlim 191	"FPU DF"
+#______________________________________________________________________________
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fild"	 0	 0	 0 	 0 	0
+INSN 0	INS_FPU	ADDRMETH_M|OPTYPE_w|OP_W	ARG_NONE	ARG_NONE	cpu_PENTIUM4 | isa_GP	"fisttp"	0	0	0	0	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fist"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_w|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fistp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fb|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fbld"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_q|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fild"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_fb|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fbstp"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_M|OPTYPE_q|OP_W	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fistp"	 0	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_DFC0	tbl_fpu_ext	shift 0	mask 255	minlim 192	maxlim 255	"FPU DF C0"
+#______________________________________________________________________________
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RR | OPTYPE_w | OP_R	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 "fnstsw"	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomip"	 0	 0	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomip"	 0	 1	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomip"	 0	 2	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomip"	 0	 3	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomip"	 0	 4	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomip"	 0	 5	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomip"	 0	 6	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fucomip"	 0	 7	 0 	 0 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomip"	 0	 0	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomip"	 0	 1	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomip"	 0	 2	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomip"	 0	 3	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomip"	 0	 4	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomip"	 0	 5	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomip"	 0	 6	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	 INS_FPU	 ADDRMETH_RF | OPTYPE_fp | OP_W	 ADDRMETH_RF | OPTYPE_fp | OP_R	 ARG_NONE	 cpu_80387 | isa_FPU	 "fcomip"	 0	 7	 0 	 INS_SET_ZERO|INS_SET_PARITY|INS_SET_CARRY 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+INSN 0	INS_INVALID	 ARG_NONE	 ARG_NONE	 ARG_NONE	 cpu_80387 | isa_FPU	 ""	 0	 0	 0 	 0 	0
+#______________________________________________________________________________
+END TABLE
+
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+#+++++++++++++++++++---------------------------------++++++++++++++++++++
+#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+TABLE tbl_0F0F	tbl_suffix	shift 0	mask 255	minlim 0	maxlim 191	"3D Now! 0F Suffix"
+#______________________________________________________________________________
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0	/* 00 */
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_CONV	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pi2fd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0	/* 10 */
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_CONV	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pf2id"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0	/* 20 */
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0	/* 30 */
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0	/* 40 */
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0	/* 50 */
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0	/* 60 */
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0	/* 70 */
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0	/* 80 */
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_CMP	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfcmpge"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_MIN	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfmin"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_ARITH	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfrcp"	0	0	0	0	0
+INSN 0	INS_ARITH	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfrsqrt"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_SUB	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfsub"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_ADD	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfadd"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_CMP	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfcmpgt"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_MAX	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfmax"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_ARITH	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfrcpit1"	0	0	0	0	0
+INSN 0	INS_ARITH	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfrsqit1"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_SUB	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfsubr"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_ADD	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfacc"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_CMP	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfcmpeq"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_MUL	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfmul"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_ARITH	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pfrcpit2"	0	0	0	0	0
+INSN 0	INS_MUL	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pmulhrw"	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_INVALID	ARG_NONE	ARG_NONE	ARG_NONE	cpu_K6 | isa_3DNOW	""	0	0	0	0	0
+INSN 0	INS_AVG	ADDRMETH_P | OPTYPE_pi | OP_R | OP_W	ADDRMETH_Q | OPTYPE_q |OP_R	ARG_NONE	cpu_K6 | isa_3DNOW	"pavgusb"	0	0	0	0	0
+#______________________________________________________________________________
+END TABLE
+
+
+
+#=======================================================================
+# TODO:
+#  + Support only three flags types: set, clear, and toggle. Move specific flag
+#    into flags set.
+#  + Finish typing 'unknown' instructions, esp ps and pd instructions.
+#=======================================================================
+# CPU Ver:
+#mmx: (data xfer) movd, movq, (conversion) packsswb, packssdw, packuswb, 
+#punpckhbw, punpckhwd, punpckhdq, punpcklbw, punpcklwd, punpckldq,
+#(arith) paddb, paddw, paddd, paddsb, paddsw, paddusb, paddusw,
+#psubb, psubw, psubd, psubsb, psubsw, psubusb, psubusw, pmulhw, pmullw, pmaddwd,
+#(cmp) PCMPEQB PCMPEQW PCMPEQD PCMPGTB PCMPGTW PCMPGTD,
+#(logic) PAND PANDN POR PXOR, (shift/rot) PSLLW PSLLD PSLLQ PSRLW PSRLD 
+#PSRLQ PSRAW PSRAD, (sys) emms
+
+#sse: (data xfer) MOVAPS MOVUPS MOVHPS, MOVHLPS MOVLPS MOVLHPS MOVMSKPS MOVSS,
+#(arith) ADDPS ADDSS SUBPS SUBSS MULPS MULSS DIVPS DIVSS RCPPS RCPSS SQRTPS 
+#SQRTSS RSQRTPS RSQRTSS MAXPS MAXSS MINPS MINSS, (cmp) CMPPS CMPSS COMISS 
+#UCOMISS, (logic) ANDPS ANDNPS ORPS XORPS, (misc) SHUFPS UNPCKHPS UNPCKLPS,
+#(convert) CVTPI2PS CVTSI2SS CVTPS2PI CVTTPS2PI CVTSS2SI CVTTSS2SI,
+#(sys) LDMXCSR STMXCSR, (misc) PAVGB PAVGW PEXTRW PINSRW PMAXUB PMAXSW PMINUB 
+#PMINSW, PMOVMSKB PMULHUW PSADBW PSHUFW, (sys) MASKMOVQ MOVNTQ MOVNTPS 
+# PREFETCHh SFENCE
+
+#sse2: (data xfer) MOVAPD MOVUPD MOVHPD MOVLPD MOVMSKPD MOVSD (arith)
+#ADDPD ADDSD SUBPD SUBSD MULPD MULSD, DIVPD DIVSD SQRTPD SQRTSD MAXPD ,
+#MAXSD MINPD MINSD (logic) ANDPD ANDNPD ORPD XORPD, (cmp) CMPPD CMPSD COMISD 
+#UCOMISD, (misc) SHUFPD UNPCKHPD UNPCKLPD, (c0nvert) CVTPD2PI CVTTPD2PI 
+#CVTPI2PD CVTPD2DQ CVTTPD2DQ CVTDQ2PD CVTPS2PD CVTPD2PS CVTSS2SD CVTSD2SS 
+#CVTSD2SI CVTTSD2SI CVTSI2SD (fp) CVTDQ2PS CVTPS2DQ CVTTPS2DQ,  (...)
+#MOVDQA MOVDQU MOVQ2DQ MOVDQ2Q PMULUDQ PADDQ PSUBQ PSHUFLW PSHUFHW PSHUFD 
+#PSLLDQ PSRLDQ PUNPCKHQDQ PUNPCKLQDQ, (sys) CLFLUSH LFENCE MFENCE PAUSE 
+#MASKMOVDQU MOVNTPD MOVNTDQ MOVNTI
+
+#sse3: (convert) FISTTP, (data xfer) LDDQU, (arith) ADDSUBPS ADDSUBPD,
+#HADDPS HSUBPS HADDPD HSUBPD, (data xfer) MOVSHDUP MOVSLDUP MOVDDUP,
+#(sys) MONITOR MWAIT
+#sys/ring0: LGDT SGDT LLDT SLDT LTR STR LIDT SIDT MOV LMSW
+#SMSW CLTS ARPL LAR LSL VERR VERW MOV INVD WBINVD INVLPG LOCK HLT RSM RDMSR 
+#WRMSR RDPMC RDTSC SYSENTER SYSEXIT
+
+#386: lss, lfs, lgs, long disp jcc, single-bit insn, bit scan insns, 
+#double shift, byte set on cond, mov w/ sign ext, generalized multiply,
+#mov to/from control reg, move to/from test reg, mov to/from debug reg,
+#rsm
+
+# exceptions : bitmask them, return exception name?
+#TABLE tbl_DA	tbl_fpu	shift 3	mask 15	minlim 0	maxlim 15	"FPU DA"
+#TABLE tbl_DAC0	tbl_fpu_ext	shift 0	mask 31	minlim 0	maxlim 31	"FPU DA C0"

+ 49 - 0
3rd_party/libdisasm/libdisasm.def

@@ -0,0 +1,49 @@
+;libdisasm.def : Declares the module parameters
+
+LIBRARY "libdisasm.dll"
+DESCRIPTION "libdisasm exported functions"
+EXPORTS
+	 x86_addr_size  		@1
+	 x86_cleanup		@2
+	 x86_disasm		@3
+	 x86_disasm_forward	@4
+	 x86_disasm_range		@5	
+	 x86_endian		@6
+	 x86_format_header		@7
+	 x86_format_insn		@8
+	 x86_format_mnemonic	@9
+	 x86_format_operand	@10
+	 x86_fp_reg		@11
+	 x86_get_branch_target	@12
+	 x86_get_imm		@13
+	 x86_get_options		@14
+	 x86_get_raw_imm		@15
+	 x86_get_rel_offset		@16
+	 x86_imm_signsized		@17
+	 x86_imm_sized		@18
+	 x86_init			@19
+	 x86_insn_is_tagged		@20
+	 x86_insn_is_valid		@21
+	 x86_invariant_disasm	@22	
+	 x86_ip_reg		@23
+	 x86_max_insn_size		@24
+	 x86_op_size		@25
+	 x86_operand_1st		@26
+	 x86_operand_2nd		@27
+	 x86_operand_3rd		@28
+	 x86_operand_count	@29
+	 x86_operand_foreach	@30
+	 x86_operand_new		@31
+	 x86_operand_size		@32
+	 x86_oplist_free		@33
+	 x86_reg_from_id		@34
+	 x86_report_error		@35
+	 x86_set_insn_addr		@36
+	 x86_set_insn_block	@37
+	 x86_set_insn_function	@38
+	 x86_set_insn_offset	@39
+	 x86_set_options		@40
+	 x86_set_reporter		@41
+	 x86_size_disasm		@42
+	 x86_sp_reg		@43
+	 x86_tag_insn		@44

+ 7 - 2
CMakeLists.txt

@@ -12,7 +12,7 @@ IF(CMAKE_BUILD_TOOL MATCHES "(msdev|devenv|nmake)")
     ADD_DEFINITIONS(/W4)
 ELSE()
 #-D_GLIBCXX_DEBUG
-    SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall --std=c++11")
+    SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -std=c++11")
     SET(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} "  ) #--coverage
 ENDIF()
 
@@ -46,9 +46,9 @@ set(dcc_LIB_SOURCES
     src/control.cpp
     src/dataflow.cpp
     src/disassem.cpp
+    src/DccFrontend.cpp
     src/error.cpp
     src/fixwild.cpp
-    src/frontend.cpp
     src/graph.cpp
     src/hlicode.cpp
     src/hltype.cpp
@@ -77,6 +77,7 @@ set(dcc_LIB_SOURCES
     src/symtab.cpp
     src/udm.cpp
     src/BasicBlock.cpp
+    src/dcc_interface.cpp
 )
 set(dcc_SOURCES
     src/dcc.cpp
@@ -85,6 +86,7 @@ set(dcc_HEADERS
     include/ast.h
     include/bundle.h
     include/BinaryImage.h
+    include/DccFrontend.h
     include/dcc.h
     include/disassem.h
     include/dosdcc.h
@@ -113,18 +115,21 @@ set(dcc_HEADERS
     include/Procedure.h
     include/StackFrame.h
     include/BasicBlock.h
+    include/dcc_interface.h
 
 )
 SOURCE_GROUP(Source FILES ${dcc_SOURCES})
 SOURCE_GROUP(Headers FILES ${dcc_HEADERS})
 
 ADD_LIBRARY(dcc_lib STATIC ${dcc_LIB_SOURCES} ${dcc_HEADERS})
+qt5_use_modules(dcc_lib Core)
 #cotire(dcc_lib)
 
 ADD_EXECUTABLE(dcc_original ${dcc_SOURCES} ${dcc_HEADERS})
 ADD_DEPENDENCIES(dcc_original dcc_lib)
 TARGET_LINK_LIBRARIES(dcc_original dcc_lib disasm_s ${REQ_LLVM_LIBRARIES} ncurses LLVMSupport)
 qt5_use_modules(dcc_original Core)
+#ADD_SUBDIRECTORY(gui)
 if(dcc_build_tests)
 ADD_SUBDIRECTORY(src)
 endif()

File diff suppressed because it is too large
+ 464 - 122
CMakeScripts/cotire.cmake


+ 5 - 2
include/BinaryImage.h

@@ -1,5 +1,6 @@
 #pragma once
 #include <stdint.h>
+#include <vector>
 struct PROG /* Loaded program image parameters  */
 {
     int16_t     initCS;
@@ -8,15 +9,17 @@ struct PROG /* Loaded program image parameters  */
     uint16_t    initSP;
     bool        fCOM;       /* Flag set if COM program (else EXE)*/
     int         cReloc;     /* No. of relocation table entries  */
-    uint32_t *  relocTable; /* Ptr. to relocation table         */
+    std::vector<uint32_t> relocTable; /* Ptr. to relocation table         */
     uint8_t *   map;        /* Memory bitmap ptr                */
     int         cProcs;     /* Number of procedures so far      */
     int         offMain;    /* The offset  of the main() proc   */
     uint16_t    segMain;    /* The segment of the main() proc   */
     bool        bSigs;		/* True if signatures loaded		*/
     int         cbImage;    /* Length of image in bytes         */
-    const uint8_t *image() const {return Imagez;}
     uint8_t *   Imagez;      /* Allocated by loader to hold entire program image */
     int         addressingMode;
+public:
+    const uint8_t *image() const {return Imagez;}
+    void displayLoadInfo();
 };
 

+ 19 - 0
include/CallGraph.h

@@ -0,0 +1,19 @@
+#pragma once
+#include "Procedure.h"
+/* CALL GRAPH NODE */
+struct CALL_GRAPH
+{
+        ilFunction proc;               /* Pointer to procedure in pProcList	*/
+        std::vector<CALL_GRAPH *> outEdges; /* array of out edges                   */
+public:
+        void write();
+        CALL_GRAPH()
+        {
+        }
+public:
+        void writeNodeCallGraph(int indIdx);
+        bool insertCallGraph(ilFunction caller, ilFunction callee);
+        bool insertCallGraph(Function *caller, ilFunction callee);
+        void insertArc(ilFunction newProc);
+};
+//extern CALL_GRAPH * callGraph;	/* Pointer to the head of the call graph     */

+ 17 - 0
include/DccFrontend.h

@@ -0,0 +1,17 @@
+#pragma once
+#include <QObject>
+class Project;
+class DccFrontend : public QObject
+{
+    Q_OBJECT
+    void    LoadImage();
+    void    parse(Project &proj);
+    std::string m_fname;
+public:
+    explicit DccFrontend(QObject *parent = 0);
+    bool FrontEnd();            /* frontend.c   */
+
+signals:
+
+public slots:
+};

+ 4 - 14
include/dcc.h

@@ -9,6 +9,7 @@
 #include <utility>
 #include <algorithm>
 #include <bitset>
+#include <QtCore/QString>
 
 #include "Enums.h"
 #include "types.h"
@@ -26,7 +27,7 @@ extern bundle cCode;			/* Output C procedure's declaration and code */
 
 /**** Global variables ****/
 
-extern std::string asm1_name, asm2_name; /* Assembler output filenames 		*/
+extern QString asm1_name, asm2_name; /* Assembler output filenames 		*/
 
 typedef struct {            /* Command line option flags */
     unsigned verbose        : 1;
@@ -37,7 +38,7 @@ typedef struct {            /* Command line option flags */
     unsigned Stats          : 1;
     unsigned Interact       : 1;    /* Interactive mode */
     unsigned Calls          : 1;    /* Follow register indirect calls */
-    std::string	filename;			/* The input filename */
+    QString	filename;			/* The input filename */
 } OPTION;
 
 extern OPTION option;       /* Command line options             */
@@ -71,22 +72,11 @@ extern STATS stats; /* Icode statistics */
 
 
 /**** Global function prototypes ****/
-class DccFrontend
-{
-    void    LoadImage(Project &proj);
-    void    parse(Project &proj);
-    std::string m_fname;
-public:
-    DccFrontend(const std::string &fname) : m_fname(fname)
-    {
-    }
-    bool FrontEnd();            /* frontend.c   */
-};
 
 void    udm(void);                                          /* udm.c        */
 void    freeCFG(BB * cfg);                                  /* graph.c      */
 BB *    newBB(BB *, int, int, uint8_t, int, Function *);    /* graph.c      */
-void    BackEnd(const std::string &filename, CALL_GRAPH *);              /* backend.c    */
+void    BackEnd(CALL_GRAPH *);              /* backend.c    */
 extern char   *cChar(uint8_t c);                            /* backend.c    */
 eErrorId scan(uint32_t ip, ICODE &p);                       /* scanner.c    */
 void    parse (CALL_GRAPH * *);                             /* parser.c     */

+ 25 - 0
include/dcc_interface.h

@@ -0,0 +1,25 @@
+#pragma once
+#include "Procedure.h"
+
+#include <QtCore/QObject>
+#include <QtCore/QDir>
+#include <llvm/ADT/ilist.h>
+
+class IXmlTarget;
+
+struct IDcc {
+    static IDcc *get();
+    virtual void BaseInit()=0;
+    virtual void Init(QObject *tgt)=0;
+    virtual lFunction::iterator GetFirstFuncHandle()=0;
+    virtual lFunction::iterator GetCurFuncHandle()=0;
+    virtual void analysis_Once()=0;
+    virtual void load(QString name)=0; // load and preprocess -> find entry point
+    virtual void prtout_asm(IXmlTarget *,int level=0)=0;
+    virtual void prtout_cpp(IXmlTarget *,int level=0)=0;
+    virtual size_t getFuncCount()=0;
+    virtual const lFunction &validFunctions() const =0;
+    virtual void SetCurFunc_by_Name(QString )=0;
+    virtual QDir installDir()=0;
+    virtual QDir dataDir(QString kind)=0;
+};

+ 14 - 7
include/project.h

@@ -8,22 +8,25 @@
 #include <boost/icl/interval_map.hpp>
 #include <boost/icl/split_interval_map.hpp>
 #include <unordered_set>
+#include <QtCore/QString>
 #include "symtab.h"
 #include "BinaryImage.h"
 #include "Procedure.h"
+class QString;
 class SourceMachine;
 struct CALL_GRAPH;
 class IProject
 {
     virtual PROG *binary()=0;
-    virtual const std::string & project_name() const =0;
-    virtual const std::string & binary_path() const =0;
+    virtual const QString & project_name() const =0;
+    virtual const QString & binary_path() const =0;
 };
 class Project : public IProject
 {
     static Project *s_instance;
-    std::string m_fname;
-    std::string m_project_name;
+    QString m_fname;
+    QString m_project_name;
+    QString m_output_path;
 public:
 
 typedef llvm::iplist<Function> FunctionListType;
@@ -41,9 +44,12 @@ typedef FunctionListType lFunction;
     Project(); // default constructor,
 
 public:
-    void create(const std::string & a);
-    const std::string &project_name() const {return m_project_name;}
-    const std::string &binary_path() const {return m_fname;}
+    void create(const QString &a);
+    bool load();
+    const QString &output_path() const {return m_output_path;}
+    const QString &project_name() const {return m_project_name;}
+    const QString &binary_path() const {return m_fname;}
+    QString output_name(const char *ext);
     ilFunction funcIter(Function *to_find);
     ilFunction findByEntry(uint32_t entry);
     ilFunction createFunction(FunctionType *f,const std::string &name);
@@ -60,6 +66,7 @@ public:
     PROG * binary() {return &prog;}
     SourceMachine *machine();
 
+    const FunctionListType &functions() const { return pProcList; }
 protected:
     void initialize();
     void writeGlobSymTable();

BIN
prototypes/dcclibs.dat


BIN
sigs/dccb2s.sig


+ 14 - 14
src/BasicBlock.cpp

@@ -28,11 +28,11 @@ BB *BB::Create(const rCODE &r,eBBKind _nodeType, Function *parent)
     pnewBB->loopHead = pnewBB->caseHead = pnewBB->caseTail =
     pnewBB->latchNode= pnewBB->loopFollow = NO_NODE;
     pnewBB->instructions = r;
-    int addr = pnewBB->begin()->loc_ip;
     /* Mark the basic block to which the icodes belong to, but only for
      * real code basic blocks (ie. not interval bbs) */
     if(parent)
     {
+        int addr = pnewBB->begin()->loc_ip;
         //setInBB should automatically handle if our range is empty
         parent->Icode.SetInBB(pnewBB->instructions, pnewBB);
 
@@ -40,10 +40,10 @@ BB *BB::Create(const rCODE &r,eBBKind _nodeType, Function *parent)
         parent->m_ip_to_bb[addr] = pnewBB;
         parent->m_actual_cfg.push_back(pnewBB);
         pnewBB->Parent = parent;
-    }
 
     if ( r.begin() != parent->Icode.end() )		/* Only for code BB's */
         stats.numBBbef++;
+    }
     return pnewBB;
 
 }
@@ -90,7 +90,7 @@ void BB::displayDfs()
            dfsFirstNum, dfsLastNum,
            immedDom == MAX ? -1 : immedDom);
     printf("loopType = %s, loopHead = %d, latchNode = %d, follow = %d\n",
-           s_loopType[loopType],
+           s_loopType[(int)loopType],
            loopHead == MAX ? -1 : loopHead,
            latchNode == MAX ? -1 : latchNode,
            loopFollow == MAX ? -1 : loopFollow);
@@ -136,12 +136,14 @@ void BB::displayDfs()
 */
 ICODE* BB::writeLoopHeader(int &indLevel, Function* pProc, int *numLoc, BB *&latch, bool &repCond)
 {
+    if(loopType == eNodeHeaderType::NO_TYPE)
+        return nullptr;
     latch = pProc->m_dfsLast[this->latchNode];
     std::ostringstream ostr;
     ICODE* picode;
     switch (loopType)
     {
-        case WHILE_TYPE:
+    case eNodeHeaderType::WHILE_TYPE:
             picode = &this->back();
 
             /* Check for error in while condition */
@@ -169,15 +171,16 @@ ICODE* BB::writeLoopHeader(int &indLevel, Function* pProc, int *numLoc, BB *&lat
             picode->invalidate();
             break;
 
-        case REPEAT_TYPE:
+    case eNodeHeaderType::REPEAT_TYPE:
             ostr << "\n"<<indentStr(indLevel)<<"do {\n";
             picode = &latch->back();
             picode->invalidate();
             break;
 
-        case ENDLESS_TYPE:
+    case eNodeHeaderType::ENDLESS_TYPE:
             ostr << "\n"<<indentStr(indLevel)<<"for (;;) {\n";
             picode = &latch->back();
+        break;
     }
     cCode.appendCode(ostr.str());
     stats.numHLIcode += 1;
@@ -209,10 +212,7 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode,
     /* Check for start of loop */
     repCond = false;
     latch = nullptr;
-    if (loopType)
-    {
        picode=writeLoopHeader(indLevel, pProc, numLoc, latch, repCond);
-    }
 
     /* Write the code for this basic block */
     if (repCond == false)
@@ -227,12 +227,12 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode,
         return;
 
     /* Check type of loop/node and process code */
-    if ( loopType )	/* there is a loop */
+    if ( loopType!=eNodeHeaderType::NO_TYPE )	/* there is a loop */
     {
         assert(latch);
         if (this != latch)		/* loop is over several bbs */
         {
-            if (loopType == WHILE_TYPE)
+            if (loopType == eNodeHeaderType::WHILE_TYPE)
             {
                 succ = edges[THEN].BBptr;
                 if (succ->dfsLastNum == loopFollow)
@@ -248,7 +248,7 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode,
 
         /* Loop epilogue: generate the loop trailer */
         indLevel--;
-        if (loopType == WHILE_TYPE)
+        if (loopType == eNodeHeaderType::WHILE_TYPE)
         {
             std::ostringstream ostr;
             /* Check if there is need to repeat other statements involved
@@ -260,9 +260,9 @@ void BB::writeCode (int indLevel, Function * pProc , int *numLoc,int _latchNode,
             ostr <<indentStr(indLevel)<< "}	/* end of while */\n";
             cCode.appendCode(ostr.str());
         }
-        else if (loopType == ENDLESS_TYPE)
+        else if (loopType == eNodeHeaderType::ENDLESS_TYPE)
             cCode.appendCode( "%s}	/* end of loop */\n",indentStr(indLevel));
-        else if (loopType == REPEAT_TYPE)
+        else if (loopType == eNodeHeaderType::REPEAT_TYPE)
         {
             string e = "//*failed*//";
             if (picode->hl()->opcode != HLI_JCOND)

+ 410 - 0
src/DccFrontend.cpp

@@ -0,0 +1,410 @@
+#include <QtCore/QFileInfo>
+#include <QtCore/QDebug>
+#include <cstdio>
+#include "dcc.h"
+#include "DccFrontend.h"
+#include "project.h"
+#include "disassem.h"
+#include "CallGraph.h"
+
+
+class Loader
+{
+    bool loadIntoProject(IProject *);
+};
+
+struct PSP {			/*        PSP structure					*/
+    uint16_t int20h;			/* interrupt 20h						*/
+    uint16_t eof;				/* segment, end of allocation block		*/
+    uint8_t res1;				/* reserved                         	*/
+    uint8_t dosDisp[5];		/* far call to DOS function dispatcher	*/
+    uint8_t int22h[4];			/* vector for terminate routine			*/
+    uint8_t int23h[4];			/* vector for ctrl+break routine		*/
+    uint8_t int24h[4];			/* vector for error routine				*/
+    uint8_t res2[22];			/* reserved								*/
+    uint16_t segEnv;			/* segment address of environment block	*/
+    uint8_t res3[34];			/* reserved								*/
+    uint8_t int21h[6];			/* opcode for int21h and far return		*/
+    uint8_t res4[6];			/* reserved								*/
+    uint8_t fcb1[16];			/* default file control block 1			*/
+    uint8_t fcb2[16];      	/* default file control block 2			*/
+    uint8_t res5[4];			/* reserved								*/
+    uint8_t cmdTail[0x80];		/* command tail and disk transfer area	*/
+};
+
+static struct MZHeader {				/*      EXE file header		 	 */
+    uint8_t     sigLo;			/* .EXE signature: 0x4D 0x5A	 */
+    uint8_t     sigHi;
+    uint16_t	lastPageSize;	/* Size of the last page		 */
+    uint16_t	numPages;		/* Number of pages in the file	 */
+    uint16_t	numReloc;		/* Number of relocation items	 */
+    uint16_t	numParaHeader;	/* # of paragraphs in the header */
+    uint16_t	minAlloc;		/* Minimum number of paragraphs	 */
+    uint16_t	maxAlloc;		/* Maximum number of paragraphs	 */
+    uint16_t	initSS;			/* Segment displacement of stack */
+    uint16_t	initSP;			/* Contents of SP at entry       */
+    uint16_t	checkSum;		/* Complemented checksum         */
+    uint16_t	initIP;			/* Contents of IP at entry       */
+    uint16_t	initCS;			/* Segment displacement of code  */
+    uint16_t	relocTabOffset;	/* Relocation table offset       */
+    uint16_t	overlayNum;		/* Overlay number                */
+} header;
+
+#define EXE_RELOCATION  0x10		/* EXE images rellocated to above PSP */
+
+//static void LoadImage(char *filename);
+static void displayMemMap(void);
+/****************************************************************************
+* displayLoadInfo - Displays low level loader type info.
+***************************************************************************/
+void PROG::displayLoadInfo(void)
+{
+    int	i;
+
+    printf("File type is %s\n", (fCOM)?"COM":"EXE");
+    if (! fCOM) {
+        printf("Signature            = %02X%02X\n", header.sigLo, header.sigHi);
+        printf("File size %% 512     = %04X\n", LH(&header.lastPageSize));
+        printf("File size / 512      = %04X pages\n", LH(&header.numPages));
+        printf("# relocation items   = %04X\n", LH(&header.numReloc));
+        printf("Offset to load image = %04X paras\n", LH(&header.numParaHeader));
+        printf("Minimum allocation   = %04X paras\n", LH(&header.minAlloc));
+        printf("Maximum allocation   = %04X paras\n", LH(&header.maxAlloc));
+    }
+    printf("Load image size      = %04" PRIiPTR "\n", cbImage - sizeof(PSP));
+    printf("Initial SS:SP        = %04X:%04X\n", initSS, initSP);
+    printf("Initial CS:IP        = %04X:%04X\n", initCS, initIP);
+
+    if (option.VeryVerbose && cReloc)
+    {
+        printf("\nRelocation Table\n");
+        for (i = 0; i < cReloc; i++)
+        {
+            printf("%06X -> [%04X]\n", relocTable[i],LH(image() + relocTable[i]));
+        }
+    }
+    printf("\n");
+}
+
+/*****************************************************************************
+* fill - Fills line for displayMemMap()
+****************************************************************************/
+static void fill(int ip, char *bf)
+{
+    PROG &prog(Project::get()->prog);
+    static uint8_t type[4] = {'.', 'd', 'c', 'x'};
+    uint8_t	i;
+
+    for (i = 0; i < 16; i++, ip++)
+    {
+        *bf++ = ' ';
+        *bf++ = (ip < prog.cbImage)? type[(prog.map[ip >> 2] >> ((ip & 3) * 2)) & 3]: ' ';
+    }
+    *bf = '\0';
+}
+
+
+/*****************************************************************************
+* displayMemMap - Displays the memory bitmap
+****************************************************************************/
+static void displayMemMap(void)
+{
+    PROG &prog(Project::get()->prog);
+
+    char	c, b1[33], b2[33], b3[33];
+    uint8_t i;
+    int ip = 0;
+
+    printf("\nMemory Map\n");
+    while (ip < prog.cbImage)
+    {
+        fill(ip, b1);
+        printf("%06X %s\n", ip, b1);
+        ip += 16;
+        for (i = 3, c = b1[1]; i < 32 && c == b1[i]; i += 2)
+            ;		/* Check if all same */
+        if (i > 32)
+        {
+            fill(ip, b2);	/* Skip until next two are not same */
+            fill(ip+16, b3);
+            if (! (strcmp(b1, b2) || strcmp(b1, b3)))
+            {
+                printf("                   :\n");
+                do
+                {
+                    ip += 16;
+                    fill(ip+16, b1);
+                } while (! strcmp(b1, b2));
+            }
+        }
+    }
+    printf("\n");
+}
+DccFrontend::DccFrontend(QObject *parent) :
+    QObject(parent)
+{
+}
+
+/*****************************************************************************
+* FrontEnd - invokes the loader, parser, disassembler (if asm1), icode
+* rewritter, and displays any useful information.
+****************************************************************************/
+bool DccFrontend::FrontEnd ()
+{
+
+    /* Do depth first flow analysis building call graph and procedure list,
+     * and attaching the I-code to each procedure          */
+    parse (*Project::get());
+
+    if (option.asm1)
+    {
+        std::cout << "dcc: writing assembler file "<<asm1_name.toStdString()<<'\n';
+    }
+
+    /* Search through code looking for impure references and flag them */
+    Disassembler ds(1);
+    for(Function &f : Project::get()->pProcList)
+    {
+        f.markImpure();
+        if (option.asm1)
+        {
+            ds.disassem(&f);
+        }
+    }
+    if (option.Interact)
+    {
+        interactDis(&Project::get()->pProcList.front(), 0);     /* Interactive disassembler */
+    }
+
+    /* Converts jump target addresses to icode offsets */
+    for(Function &f : Project::get()->pProcList)
+    {
+        f.bindIcodeOff();
+    }
+    /* Print memory bitmap */
+    if (option.Map)
+        displayMemMap();
+    return(true); // we no longer own proj !
+}
+struct DosLoader {
+protected:
+    void prepareImage(PROG &prog,size_t sz,QFile &fp) {
+        /* Allocate a block of memory for the program. */
+        prog.cbImage  = sz + sizeof(PSP);
+        prog.Imagez    = new uint8_t [prog.cbImage];
+        prog.Imagez[0] = 0xCD;		/* Fill in PSP int 20h location */
+        prog.Imagez[1] = 0x20;		/* for termination checking     */
+        /* Read in the image past where a PSP would go */
+        if (sz != fp.read((char *)prog.Imagez + sizeof(PSP),sz))
+            fatalError(CANNOT_READ, fp.fileName().toLocal8Bit().data());
+    }
+};
+struct ComLoader : public DosLoader {
+    bool canLoad(QFile &fp) {
+        fp.seek(0);
+        char sig[2];
+        if(2==fp.read(sig,2)) {
+            return not (sig[0] == 0x4D && sig[1] == 0x5A);
+        }
+        return false;
+    }
+    bool load(PROG &prog,QFile &fp) {
+        /* COM file
+         * In this case the load module size is just the file length
+         */
+        auto cb = fp.size();
+
+        /* COM programs start off with an ORG 100H (to leave room for a PSP)
+         * This is also the implied start address so if we load the image
+         * at offset 100H addresses should all line up properly again.
+         */
+        prog.initCS = 0;
+        prog.initIP = 0x100;
+        prog.initSS = 0;
+        prog.initSP = 0xFFFE;
+        prog.cReloc = 0;
+
+        prepareImage(prog,cb,fp);
+
+
+        /* Set up memory map */
+        cb = (prog.cbImage + 3) / 4;
+        prog.map = (uint8_t *)malloc(cb);
+        memset(prog.map, BM_UNKNOWN, (size_t)cb);
+        return true;
+    }
+};
+struct ExeLoader : public DosLoader {
+    bool canLoad(QFile &fp) {
+        if(fp.size()<sizeof(header))
+            return false;
+        MZHeader tmp_header;
+        fp.seek(0);
+        fp.read((char *)&tmp_header, sizeof(header));
+        if(not (tmp_header.sigLo == 0x4D && tmp_header.sigHi == 0x5A))
+            return false;
+
+        /* This is a typical DOS kludge! */
+        if (LH(&header.relocTabOffset) == 0x40)
+        {
+            qDebug() << "Don't understand new EXE format";
+            return false;
+        }
+        return true;
+    }
+    bool load(PROG &prog,QFile &fp) {
+        /* Read rest of header */
+        fp.seek(0);
+        if (fp.read((char *)&header, sizeof(header)) != sizeof(header))
+            return false;
+
+        /* Calculate the load module size.
+        * This is the number of pages in the file
+        * less the length of the header and reloc table
+        * less the number of bytes unused on last page
+        */
+        uint32_t cb = (uint32_t)LH(&header.numPages) * 512 - (uint32_t)LH(&header.numParaHeader) * 16;
+        if (header.lastPageSize)
+        {
+            cb -= 512 - LH(&header.lastPageSize);
+        }
+
+        /* We quietly ignore minAlloc and maxAlloc since for our
+        * purposes it doesn't really matter where in real memory
+        * the program would end up.  EXE programs can't really rely on
+        * their load location so setting the PSP segment to 0 is fine.
+        * Certainly programs that prod around in DOS or BIOS are going
+        * to have to load DS from a constant so it'll be pretty
+        * obvious.
+        */
+        prog.initCS = (int16_t)LH(&header.initCS) + EXE_RELOCATION;
+        prog.initIP = (int16_t)LH(&header.initIP);
+        prog.initSS = (int16_t)LH(&header.initSS) + EXE_RELOCATION;
+        prog.initSP = (int16_t)LH(&header.initSP);
+        prog.cReloc = (int16_t)LH(&header.numReloc);
+
+        /* Allocate the relocation table */
+        if (prog.cReloc)
+        {
+            prog.relocTable.resize(prog.cReloc);
+            fp.seek(LH(&header.relocTabOffset));
+
+            /* Read in seg:offset pairs and convert to Image ptrs */
+            uint8_t	buf[4];
+            for (int i = 0; i < prog.cReloc; i++)
+            {
+                fp.read((char *)buf,4);
+                prog.relocTable[i] = LH(buf) + (((int)LH(buf+2) + EXE_RELOCATION)<<4);
+            }
+        }
+        /* Seek to start of image */
+        uint32_t start_of_image= LH(&header.numParaHeader) * 16;
+        fp.seek(start_of_image);
+        /* Allocate a block of memory for the program. */
+        prepareImage(prog,cb,fp);
+
+        /* Set up memory map */
+        cb = (prog.cbImage + 3) / 4;
+        prog.map = (uint8_t *)malloc(cb);
+        memset(prog.map, BM_UNKNOWN, (size_t)cb);
+
+        /* Relocate segment constants */
+        for(uint32_t v : prog.relocTable) {
+            uint8_t *p = &prog.Imagez[v];
+            uint16_t  w = (uint16_t)LH(p) + EXE_RELOCATION;
+            *p++    = (uint8_t)(w & 0x00FF);
+            *p      = (uint8_t)((w & 0xFF00) >> 8);
+        }
+        return true;
+    }
+};
+/*****************************************************************************
+* LoadImage
+****************************************************************************/
+bool Project::load()
+{
+    // addTask(loaderSelection,PreCond(BinaryImage))
+    // addTask(applyLoader,PreCond(Loader))
+    const char *fname = binary_path().toLocal8Bit().data();
+    QFile finfo(binary_path());
+    /* Open the input file */
+    if(!finfo.open(QFile::ReadOnly)) {
+        fatalError(CANNOT_OPEN, fname);
+    }
+    /* Read in first 2 bytes to check EXE signature */
+    if (finfo.size()<=2)
+    {
+        fatalError(CANNOT_READ, fname);
+    }
+    ComLoader com_loader;
+    ExeLoader exe_loader;
+    if(exe_loader.canLoad(finfo)) {
+        prog.fCOM = false;
+        return exe_loader.load(prog,finfo);
+    }
+    if(com_loader.canLoad(finfo)) {
+        prog.fCOM = true;
+        return com_loader.load(prog,finfo);
+    }
+    return false;
+}
+uint32_t SynthLab;
+/* Parses the program, builds the call graph, and returns the list of
+ * procedures found     */
+void DccFrontend::parse(Project &proj)
+{
+    PROG &prog(proj.prog);
+    STATE state;
+
+    /* Set initial state */
+    state.setState(rES, 0);   /* PSP segment */
+    state.setState(rDS, 0);
+    state.setState(rCS, prog.initCS);
+    state.setState(rSS, prog.initSS);
+    state.setState(rSP, prog.initSP);
+    state.IP = ((uint32_t)prog.initCS << 4) + prog.initIP;
+    SynthLab = SYNTHESIZED_MIN;
+
+    /* Check for special settings of initial state, based on idioms of the
+          startup code */
+    state.checkStartup();
+    Function *start_proc;
+    /* Make a struct for the initial procedure */
+    if (prog.offMain != -1)
+    {
+        start_proc = proj.createFunction(0,"main");
+        start_proc->retVal.loc = REG_FRAME;
+        start_proc->retVal.type = TYPE_WORD_SIGN;
+        start_proc->retVal.id.regi = rAX;
+        /* We know where main() is. Start the flow of control from there */
+        start_proc->procEntry = prog.offMain;
+        /* In medium and large models, the segment of main may (will?) not be
+            the same as the initial CS segment (of the startup code) */
+        state.setState(rCS, prog.segMain);
+        state.IP = prog.offMain;
+    }
+    else
+    {
+        start_proc = proj.createFunction(0,"start");
+        /* Create initial procedure at program start address */
+        start_proc->procEntry = (uint32_t)state.IP;
+    }
+
+    /* The state info is for the first procedure */
+    start_proc->state = state;
+
+    /* Set up call graph initial node */
+    proj.callGraph = new CALL_GRAPH;
+    proj.callGraph->proc = start_proc;
+
+    /* This proc needs to be called to set things up for LibCheck(), which
+       checks a proc to see if it is a know C (etc) library */
+    SetupLibCheck();
+    //BUG:  proj and g_proj are 'live' at this point !
+
+    /* Recursively build entire procedure list */
+    start_proc->FollowCtrl(proj.callGraph, &state);
+
+    /* This proc needs to be called to clean things up from SetupLibCheck() */
+    CleanupLibCheck();
+}

+ 11 - 10
src/backend.cpp

@@ -4,6 +4,8 @@
  * Purpose:	Back-end module.  Generates C code for each procedure.
  * (C) Cristina Cifuentes
  ****************************************************************************/
+#include <QDir>
+#include <QFile>
 #include <cassert>
 #include <string>
 #include <boost/range.hpp>
@@ -167,13 +169,13 @@ void Project::writeGlobSymTable()
 
 /* Writes the header information and global variables to the output C file
  * fp. */
-static void writeHeader (std::ostream &_ios, const char *fileName)
+static void writeHeader (std::ostream &_ios, const std::string &fileName)
 {
     PROG &prog(Project::get()->prog);
     /* Write header information */
     cCode.init();
     cCode.appendDecl( "/*\n");
-    cCode.appendDecl( " * Input file\t: %s\n", fileName);
+    cCode.appendDecl( " * Input file\t: %s\n", fileName.c_str());
     cCode.appendDecl( " * File type\t: %s\n", (prog.fCOM)?"COM":"EXE");
     cCode.appendDecl( " */\n\n#include \"dcc.h\"\n\n");
 
@@ -341,22 +343,21 @@ static void backBackEnd (CALL_GRAPH * pcallGraph, std::ostream &_ios)
 
 
 /* Invokes the necessary routines to produce code one procedure at a time. */
-void BackEnd (const std::string &fileName, CALL_GRAPH * pcallGraph)
+void BackEnd(CALL_GRAPH * pcallGraph)
 {
     std::ofstream fs; /* Output C file 	*/
 
     /* Get output file name */
-    std::string outNam(fileName);
-    outNam = outNam.substr(0,outNam.rfind("."))+".b"; /* b for beta */
+    QString outNam(Project::get()->output_name("b")); /* b for beta */
 
     /* Open output file */
-    fs.open(outNam);
+    fs.open(outNam.toStdString());
     if(!fs.is_open())
-        fatalError (CANNOT_OPEN, outNam.c_str());
-    printf ("dcc: Writing C beta file %s\n", outNam.c_str());
+        fatalError (CANNOT_OPEN, outNam.toStdString().c_str());
+    std::cout<<"dcc: Writing C beta file "<<outNam.toStdString()<<"\n";
 
     /* Header information */
-    writeHeader (fs, option.filename.c_str());
+    writeHeader (fs, option.filename.toStdString());
 
     /* Initialize total Icode instructions statistics */
     stats.totalLL = 0;
@@ -367,7 +368,7 @@ void BackEnd (const std::string &fileName, CALL_GRAPH * pcallGraph)
 
     /* Close output file */
     fs.close();
-    printf ("dcc: Finished writing C beta file\n");
+    std::cout << "dcc: Finished writing C beta file\n";
 }
 
 

+ 18 - 49
src/chklib.cpp

@@ -5,17 +5,16 @@
  * (C) Mike van Emmerik
 */
 
+#include "dcc.h"
+#include "project.h"
+#include "perfhlib.h"
+#include "dcc_interface.h"
+
+#include <QDir>
 #include <stdio.h>
 #include <stdlib.h>
-#ifdef __BORLAND__
-#include <mem.h>
-#else
 #include <memory.h>
-#endif
 #include <string.h>
-#include "dcc.h"
-#include "project.h"
-#include "perfhlib.h"
 
 #define  NIL   -1                   /* Used like NULL, but 0 is valid */
 
@@ -300,10 +299,11 @@ void SetupLibCheck(void)
     PROG &prog(Project::get()->prog);
     uint16_t w, len;
     int i;
-
-    if ((g_file = fopen(sSigName, "rb")) == nullptr)
+    IDcc *dcc = IDcc::get();
+    QString fpath = dcc->dataDir("sigs").absoluteFilePath(sSigName);
+    if ((g_file = fopen(qPrintable(fpath), "rb")) == nullptr)
     {
-        printf("Warning: cannot open signature file %s\n", sSigName);
+        printf("Warning: cannot open signature file %s\n", qPrintable(fpath));
         return;
     }
 
@@ -638,7 +638,6 @@ void STATE::checkStartup()
     char chModel = 'x';
     char chVendor = 'x';
     char chVersion = 'x';
-    char *pPath;
     char temp[4];
 
     startOff = ((uint32_t)prog.initCS << 4) + prog.initIP;
@@ -829,21 +828,6 @@ void STATE::checkStartup()
 
 gotVendor:
 
-    /* Use the DCC environment variable to set where the .sig files will
-        be found. Otherwise, assume current directory */
-    pPath = getenv("DCC");
-    if (pPath)
-    {
-        strcpy(sSigName, pPath);            /* Use path given */
-        if (sSigName[strlen(sSigName)-1] != '/')
-        {
-            strcat(sSigName, "/");          /* Append a slash if necessary */
-        }
-    }
-    else
-    {
-        strcpy(sSigName, "./");             /* Current directory */
-    }
     strcat(sSigName, "dcc");
     temp[1] = '\0';
     temp[0] = chVendor;
@@ -866,45 +850,30 @@ gotVendor:
 */
 void readProtoFile(void)
 {
+    IDcc *dcc = IDcc::get();
+    QString szProFName = dcc->dataDir("prototypes").absoluteFilePath(DCCLIBS); /* Full name of dclibs.lst */
+
     FILE *fProto;
     char *pPath;                /* Point to the environment string */
-    char szProFName[81];        /* Full name of dclibs.lst */
     int  i;
 
-    /* Use the DCC environment variable to set where the dcclibs.lst file will
-        be found. Otherwise, assume current directory */
-    pPath = getenv("DCC");
-    if (pPath)
-    {
-        strcpy(szProFName, pPath);           /* Use path given */
-        if (szProFName[strlen(szProFName)-1] != '/')
-        {
-            strcat(szProFName, "/");         /* Append a slash if necessary */
-        }
-    }
-    else
-    {
-        strcpy(szProFName, "./");            /* Current directory */
-    }
-    strcat(szProFName, DCCLIBS);
-
-    if ((fProto = fopen(szProFName, "rb")) == nullptr)
+    if ((fProto = fopen(qPrintable(szProFName), "rb")) == nullptr)
     {
-        printf("Warning: cannot open library prototype data file %s\n", szProFName);
+        printf("Warning: cannot open library prototype data file %s\n", qPrintable(szProFName));
         return;
     }
 
     grab(4, fProto);
     if (strncmp(buf, "dccp", 4) != 0)
     {
-        printf("%s is not a dcc prototype file\n", szProFName);
+        printf("%s is not a dcc prototype file\n", qPrintable(szProFName));
         exit(1);
     }
 
     grab(2, fProto);
     if (strncmp(buf, "FN", 2) != 0)
     {
-        printf("FN (Function Name) subsection expected in %s\n", szProFName);
+        printf("FN (Function Name) subsection expected in %s\n", qPrintable(szProFName));
         exit(2);
     }
 
@@ -931,7 +900,7 @@ void readProtoFile(void)
     grab(2, fProto);
     if (strncmp(buf, "PM", 2) != 0)
     {
-        printf("PM (Parameter) subsection expected in %s\n", szProFName);
+        printf("PM (Parameter) subsection expected in %s\n", qPrintable(szProFName));
         exit(2);
     }
 

+ 7 - 7
src/control.cpp

@@ -168,7 +168,7 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int
                 (inList (loopNodes, head->edges[THEN].BBptr->dfsLastNum) &&
                  inList (loopNodes, head->edges[ELSE].BBptr->dfsLastNum)))
             {
-                head->loopType = REPEAT_TYPE;
+                head->loopType = eNodeHeaderType::REPEAT_TYPE;
                 if (latchNode->edges[0].BBptr == head)
                     head->loopFollow = latchNode->edges[ELSE].BBptr->dfsLastNum;
                 else
@@ -177,7 +177,7 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int
             }
             else
             {
-                head->loopType = WHILE_TYPE;
+                head->loopType = eNodeHeaderType::WHILE_TYPE;
                 if (inList (loopNodes, head->edges[THEN].BBptr->dfsLastNum))
                     head->loopFollow = head->edges[ELSE].BBptr->dfsLastNum;
                 else
@@ -186,7 +186,7 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int
             }
         else /* head = anything besides 2-way, latch = 2-way */
         {
-            head->loopType = REPEAT_TYPE;
+            head->loopType = eNodeHeaderType::REPEAT_TYPE;
             if (latchNode->edges[THEN].BBptr == head)
                 head->loopFollow = latchNode->edges[ELSE].BBptr->dfsLastNum;
             else
@@ -196,12 +196,12 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int
     else	/* latch = 1-way */
         if (latchNode->nodeType == LOOP_NODE)
         {
-            head->loopType = REPEAT_TYPE;
+            head->loopType = eNodeHeaderType::REPEAT_TYPE;
             head->loopFollow = latchNode->edges[0].BBptr->dfsLastNum;
         }
         else if (intNodeType == TWO_BRANCH)
         {
-            head->loopType = WHILE_TYPE;
+            head->loopType = eNodeHeaderType::WHILE_TYPE;
             pbb = latchNode;
             thenDfs = head->edges[THEN].BBptr->dfsLastNum;
             elseDfs = head->edges[ELSE].BBptr->dfsLastNum;
@@ -222,7 +222,7 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int
                                  * loop, so it is safer to consider it an endless loop */
                 if (pbb->dfsLastNum <= head->dfsLastNum)
                 {
-                    head->loopType = ENDLESS_TYPE;
+                    head->loopType = eNodeHeaderType::ENDLESS_TYPE;
                     findEndlessFollow (pProc, loopNodes, head);
                     break;
                 }
@@ -234,7 +234,7 @@ static void findNodesInLoop(BB * latchNode,BB * head,Function * pProc,queue &int
         }
         else
         {
-            head->loopType = ENDLESS_TYPE;
+            head->loopType = eNodeHeaderType::ENDLESS_TYPE;
             findEndlessFollow (pProc, loopNodes, head);
         }
 

+ 0 - 2
src/dataflow.cpp

@@ -143,7 +143,6 @@ void Function::elimCondCodes ()
         //auto reversed_instructions = pBB->range() | reversed;
         for (useAt = pBB->rbegin(); useAt != pBB->rend(); useAt++)
         {
-            ICODE &useIcode(*useAt);
             llIcode useAtOp = llIcode(useAt->ll()->getOpcode());
             use = useAt->ll()->flagDU.u;
             if ((useAt->type != LOW_LEVEL) || ( ! useAt->valid() ) || ( 0 == use ))
@@ -159,7 +158,6 @@ void Function::elimCondCodes ()
                     continue;
                 notSup = false;
                 LLOperand *dest_ll = defIcode.ll()->get(DST);
-                LLOperand *src_ll = defIcode.ll()->get(SRC);
                 if ((useAtOp >= iJB) && (useAtOp <= iJNS))
                 {
                     iICODE befDefAt = (++riICODE(defAt)).base();

+ 28 - 24
src/dcc.cpp

@@ -4,26 +4,10 @@
  * (C) Cristina Cifuentes
  ****************************************************************************/
 
+#include <cstring>
+#include <iostream>
 #include <QtCore/QCoreApplication>
 #include <QCommandLineParser>
-#include <cstring>
-#include "dcc.h"
-#include "project.h"
-
-#include "CallGraph.h"
-/* Global variables - extern to other modules */
-extern std::string asm1_name, asm2_name;     /* Assembler output filenames     */
-extern SYMTAB  symtab;             /* Global symbol table      			  */
-extern STATS   stats;              /* cfg statistics       				  */
-//PROG    prog;               /* programs fields      				  */
-extern OPTION  option;             /* Command line options     			  */
-//Function *   pProcList;			/* List of procedures, topologically sort */
-//Function *	pLastProc;			/* Pointer to last node in procedure list */
-//FunctionListType pProcList;
-//CALL_GRAPH	*callGraph;		/* Call graph of the program			  */
-
-static char *initargs(int argc, char *argv[]);
-static void displayTotalStats(void);
 #include <llvm/Support/raw_os_ostream.h>
 #include <llvm/Support/CommandLine.h>
 #include <llvm/Support/TargetSelect.h>
@@ -39,11 +23,24 @@ static void displayTotalStats(void);
 #include <llvm/TableGen/Main.h>
 #include <llvm/TableGen/TableGenBackend.h>
 #include <llvm/TableGen/Record.h>
+#include <QtCore/QFile>
+
+#include "dcc.h"
+#include "project.h"
+#include "CallGraph.h"
+#include "DccFrontend.h"
+
+/* Global variables - extern to other modules */
+extern QString asm1_name, asm2_name;     /* Assembler output filenames     */
+extern SYMTAB  symtab;             /* Global symbol table      			  */
+extern STATS   stats;              /* cfg statistics       				  */
+extern OPTION  option;             /* Command line options     			  */
+
+static char *initargs(int argc, char *argv[]);
+static void displayTotalStats(void);
 /****************************************************************************
  * main
  ***************************************************************************/
-#include <QtCore/QFile>
-#include <iostream>
 using namespace llvm;
 bool TVisitor(raw_ostream &OS, RecordKeeper &Records)
 {
@@ -161,9 +158,9 @@ void setupOptions(QCoreApplication &app) {
     option.Stats = parser.isSet(boolOpts[4]);
     option.Interact = false;
     option.Calls = parser.isSet(boolOpts[2]);
-    option.filename = args.first().toStdString();
+    option.filename = args.first();
     if(parser.isSet(targetFileOption))
-        asm1_name = asm2_name = parser.value(targetFileOption).toStdString();
+        asm1_name = asm2_name = parser.value(targetFileOption);
     else if(option.asm1 || option.asm2) {
         asm1_name = option.filename+".a1";
         asm2_name = option.filename+".a2";
@@ -181,7 +178,14 @@ int main(int argc, char **argv)
      * building the call graph and attaching appropriate bits of code for
      * each procedure.
     */
-    DccFrontend fe(option.filename);
+    Project::get()->create(option.filename);
+
+    DccFrontend fe(&app);
+    if(!Project::get()->load()) {
+        return -1;
+    }
+    if (option.verbose)
+        Project::get()->prog.displayLoadInfo();
     if(false==fe.FrontEnd ())
         return -1;
     if(option.asm1)
@@ -198,7 +202,7 @@ int main(int argc, char **argv)
      * analysis, data flow etc. and outputs it to output file ready for
      * re-compilation.
     */
-    BackEnd(!asm1_name.empty() ? asm1_name:option.filename, Project::get()->callGraph);
+    BackEnd(Project::get()->callGraph);
 
     Project::get()->callGraph->write();
 

+ 61 - 0
src/dcc_interface.cpp

@@ -0,0 +1,61 @@
+#include "dcc_interface.h"
+#include "dcc.h"
+#include "project.h"
+struct DccImpl : public IDcc{
+
+
+    // IDcc interface
+public:
+    void BaseInit()
+    {
+    }
+    void Init(QObject *tgt)
+    {
+    }
+    ilFunction GetFirstFuncHandle()
+    {
+    }
+    ilFunction GetCurFuncHandle()
+    {
+    }
+    void analysis_Once()
+    {
+    }
+    void load(QString name)
+    {
+        option.filename = name;
+        Project::get()->create(name);
+    }
+    void prtout_asm(IXmlTarget *, int level)
+    {
+    }
+    void prtout_cpp(IXmlTarget *, int level)
+    {
+    }
+    size_t getFuncCount()
+    {
+    }
+    const lFunction &validFunctions() const
+    {
+        return Project::get()->functions();
+    }
+    void SetCurFunc_by_Name(QString)
+    {
+    }
+    QDir installDir() {
+        return QDir(".");
+    }
+    QDir dataDir(QString kind) { // return directory containing decompilation helper data -> signatures/includes/etc.
+        QDir res(installDir());
+        res.cd(kind);
+        return res;
+    }
+};
+
+IDcc* IDcc::get() {
+    static IDcc *v=0;
+    if(!v)
+        v = new DccImpl;
+
+    return v;
+}

+ 2 - 2
src/disassem.cpp

@@ -150,10 +150,10 @@ void Disassembler::disassem(Function * ppProc)
     if (pass != 3)
     {
         auto p = (pass == 1)? asm1_name: asm2_name;
-        m_fp.open(p,ios_base::app);
+        m_fp.open(p.toStdString(),ios_base::app);
         if (!m_fp.is_open())
         {
-            fatalError(CANNOT_OPEN, p.c_str());
+            fatalError(CANNOT_OPEN, p.toStdString().c_str());
         }
     }
     /* Create temporary code array */

+ 5 - 0
src/idioms.cpp

@@ -3,7 +3,12 @@
  * (C) Cristina Cifuentes
  ****************************************************************************/
 
+#include <llvm/Config/llvm-config.h>
+#if( (LLVM_VERSION_MAJOR==3 ) && (LLVM_VERSION_MINOR>3) )
+#include <llvm/IR/PatternMatch.h>
+#else
 #include <llvm/Support/PatternMatch.h>
+#endif
 #include <boost/iterator/filter_iterator.hpp>
 #include <cstring>
 #include <deque>

+ 9 - 12
src/idioms/mov_idioms.cpp

@@ -27,16 +27,16 @@ bool Idiom14::match(iICODE pIcode)
         return false;
     m_icodes[0]=pIcode++;
     m_icodes[1]=pIcode++;
-    LLInst * matched [] = {m_icodes[0]->ll(),m_icodes[1]->ll()};
+    LLInst * matched [] {m_icodes[0]->ll(),m_icodes[1]->ll()};
     /* Check for regL */
-    m_regL = m_icodes[0]->ll()->m_dst.regi;
-    if (not m_icodes[0]->ll()->testFlags(I) && ((m_regL == rAX) || (m_regL ==rBX)))
+    m_regL = matched[0]->m_dst.regi;
+    if (not matched[0]->testFlags(I) && ((m_regL == rAX) || (m_regL ==rBX)))
     {
         /* Check for XOR regH, regH */
-        if (m_icodes[1]->ll()->match(iXOR) && not m_icodes[1]->ll()->testFlags(I))
+        if (matched[1]->match(iXOR) && not matched[1]->testFlags(I))
         {
-            m_regH = m_icodes[1]->ll()->m_dst.regi;
-            if (m_regH == m_icodes[1]->ll()->src().getReg2())
+            m_regH = matched[1]->m_dst.regi;
+            if (m_regH == matched[1]->src().getReg2())
             {
                 if ((m_regL == rAX) && (m_regH == rDX))
                     return true;
@@ -49,14 +49,11 @@ bool Idiom14::match(iICODE pIcode)
 }
 int Idiom14::action()
 {
-    int idx;
-    AstIdent *lhs;
-    Expr *rhs;
 
-    idx = m_func->localId.newLongReg (TYPE_LONG_SIGN, LONGID_TYPE(m_regH,m_regL), m_icodes[0]);
-    lhs = AstIdent::LongIdx (idx);
+    int idx = m_func->localId.newLongReg (TYPE_LONG_SIGN, LONGID_TYPE(m_regH,m_regL), m_icodes[0]);
+    AstIdent *lhs = AstIdent::LongIdx (idx);
     m_icodes[0]->setRegDU( m_regH, eDEF);
-    rhs = AstIdent::id (*m_icodes[0]->ll(), SRC, m_func, m_icodes[0], *m_icodes[0], NONE);
+    Expr *rhs = AstIdent::id (*m_icodes[0]->ll(), SRC, m_func, m_icodes[0], *m_icodes[0], NONE);
     m_icodes[0]->setAsgn(lhs, rhs);
     m_icodes[1]->invalidate();
     return 2;

+ 1 - 63
src/parser.cpp

@@ -20,70 +20,8 @@ static void     setBits(int16_t type, uint32_t start, uint32_t len);
 static void     process_MOV(LLInst &ll, STATE * pstate);
 static SYM *     lookupAddr (LLOperand *pm, STATE * pstate, int size, uint16_t duFlag);
 void    interactDis(Function * initProc, int ic);
-static uint32_t    SynthLab;
+extern uint32_t    SynthLab;
 
-/* Parses the program, builds the call graph, and returns the list of
- * procedures found     */
-void DccFrontend::parse(Project &proj)
-{
-    PROG &prog(proj.prog);
-    STATE state;
-
-    /* Set initial state */
-    state.setState(rES, 0);   /* PSP segment */
-    state.setState(rDS, 0);
-    state.setState(rCS, prog.initCS);
-    state.setState(rSS, prog.initSS);
-    state.setState(rSP, prog.initSP);
-    state.IP = ((uint32_t)prog.initCS << 4) + prog.initIP;
-    SynthLab = SYNTHESIZED_MIN;
-
-    // default-construct a Function object !
-    /*auto func = */;
-
-    /* Check for special settings of initial state, based on idioms of the
-          startup code */
-    state.checkStartup();
-    Function *start_proc;
-    /* Make a struct for the initial procedure */
-    if (prog.offMain != -1)
-    {
-        start_proc = proj.createFunction(0,"main");
-        start_proc->retVal.loc = REG_FRAME;
-        start_proc->retVal.type = TYPE_WORD_SIGN;
-        start_proc->retVal.id.regi = rAX;
-        /* We know where main() is. Start the flow of control from there */
-        start_proc->procEntry = prog.offMain;
-        /* In medium and large models, the segment of main may (will?) not be
-            the same as the initial CS segment (of the startup code) */
-        state.setState(rCS, prog.segMain);
-        state.IP = prog.offMain;
-    }
-    else
-    {
-        start_proc = proj.createFunction(0,"start");
-        /* Create initial procedure at program start address */
-        start_proc->procEntry = (uint32_t)state.IP;
-    }
-
-    /* The state info is for the first procedure */
-    start_proc->state = state;
-
-    /* Set up call graph initial node */
-    proj.callGraph = new CALL_GRAPH;
-    proj.callGraph->proc = start_proc;
-
-    /* This proc needs to be called to set things up for LibCheck(), which
-       checks a proc to see if it is a know C (etc) library */
-    SetupLibCheck();
-    //BUG:  proj and g_proj are 'live' at this point !
-
-    /* Recursively build entire procedure list */
-    start_proc->FollowCtrl(proj.callGraph, &state);
-
-    /* This proc needs to be called to clean things up from SetupLibCheck() */
-    CleanupLibCheck();
-}
 
 /* Returns the size of the string pointed by sym and delimited by delim.
  * Size includes delimiter.     */

+ 17 - 8
src/project.cpp

@@ -1,3 +1,5 @@
+#include <QtCore/QString>
+#include <QtCore/QDir>
 #include <utility>
 #include "dcc.h"
 #include "CallGraph.h"
@@ -5,7 +7,7 @@
 #include "Procedure.h"
 using namespace std;
 //Project g_proj;
-string asm1_name, asm2_name;     /* Assembler output filenames     */
+QString asm1_name, asm2_name;     /* Assembler output filenames     */
 SYMTAB  symtab;             /* Global symbol table      			  */
 STATS   stats;              /* cfg statistics       				  */
 //PROG    prog;               /* programs fields      				  */
@@ -20,19 +22,26 @@ void Project::initialize()
     delete callGraph;
     callGraph = nullptr;
 }
-void Project::create(const string &a)
+void Project::create(const QString &a)
 {
+    initialize();
     m_fname=a;
-    string::size_type ext_loc=a.find_last_of('.');
-    string::size_type slash_loc=a.find_last_of('/',ext_loc);
-    if(slash_loc==string::npos)
+    auto ext_loc=a.lastIndexOf('.');
+    auto slash_loc=a.lastIndexOf('/',ext_loc);
+    if(slash_loc==-1)
         slash_loc=0;
     else
         slash_loc++;
-    if(ext_loc!=string::npos)
-        m_project_name = a.substr(slash_loc,(ext_loc-slash_loc));
+    if(ext_loc!=-1) {
+        m_project_name = a.mid(slash_loc,ext_loc-slash_loc);
+    }
     else
-        m_project_name = a.substr(slash_loc);
+        m_project_name = a.mid(slash_loc);
+    m_output_path = a.left(slash_loc);
+}
+
+QString Project::output_name(const char *ext) {
+    return m_output_path+QDir::separator()+m_project_name+"."+ext;
 }
 bool Project::valid(ilFunction iter)
 {

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