z8000_as.6 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166
  1. .\" $Id$
  2. .TH Z8000_AS 6 "$Revision$"
  3. .ad
  4. .SH NAME
  5. z8000_as \- assembler for Zilog z8000 (segmented version)
  6. .SH SYNOPSIS
  7. ~em/lib.bin/z8000/as [options] argument ...
  8. .SH DESCRIPTION
  9. This assembler is made with the general framework
  10. described in \fIuni_ass\fP(6). It is an assembler\-loader. Output is
  11. in \fIack.out\fP(5) format, but not relocatable.
  12. .SH SYNTAX
  13. .IP instructions
  14. Instruction mnemonics are implemented exactly as described in
  15. \fIZ8000 PLZ/ASM Assembly Language Programming Manual\fP and
  16. \fIAmZ8001/2 Processor Instruction Set\fP.
  17. .IP registers
  18. The z8000 has sixteen 16-bit general purpose registers specified
  19. as R0 through R15. All sixteen registers can be used as accumulators.
  20. In addition to this, fifteen of the sixteen registers may be used
  21. in addressing mode calculations as either indirect, index or
  22. base-address registers. Because the instruction format encoding
  23. uses the value zero to differentiate between various addressing
  24. modes, register R0 (or the register pair RR0) cannot be used as an
  25. indirect, index or base-address register.
  26. It is also possible to address registers as groups of 8, 32 or 64 bits.
  27. These registers are specified as follows.
  28. .nf
  29. .ta 8n 16n 24n 32n 40n 48n
  30. - RH0, RL0, RH1, RL1, ..., RH7, RL7 for 8-bit regis-
  31. ters. (\fIH\fP stands for high-order byte, and \fIL\fP stands
  32. for low-order byte within a word register). These
  33. registers overlap 16-bit registers R0 through R7.
  34. - RR0, RR2, ..., RR14 for 32-bit register pairs.
  35. - RQ0, RQ4, RQ8 and RQ12 for 64-bit register quadruples.
  36. .fi
  37. Besides register pair RR14 is used as stackpointer.
  38. .IP "addressing modes"
  39. .nf
  40. .ta 8n 16n 24n 32n 40n 48n
  41. syntax meaning (name-mnemonic)
  42. $expr the value of expr is the operand.
  43. (immediate-IM)
  44. reg contents of register reg is operand. Any
  45. register as described above is allowed.
  46. (register-R)
  47. *reg32 contents of register pair reg32 is add-
  48. ress of operand. Any register pair can
  49. be used except RR0.
  50. (indirect register-IR)
  51. expr expr is address of operand.
  52. (direct address-DA)
  53. expr(reg16) value of expr + contents of word regis-
  54. ter reg16 yields address of operand.
  55. Any word register can be used except R0.
  56. (indexed address-X)
  57. expr expr is address of operand. This mode
  58. is implied by its instruction. It is
  59. only used by CALR, DJNZ, JR, LDAR and
  60. LDR and is the only mode available to
  61. these instructions. In fact this mode
  62. differs not from the mode DA.
  63. (relative address-RA)
  64. reg32($expr) contents of register pair reg32 + value
  65. of expr yields address of operand. Any
  66. register pair can be used except RR0.
  67. (based address-BA)
  68. reg32(reg16) contents of register pair reg32 + con-
  69. tents of word register reg16 yields
  70. address of operand. Any register pair/
  71. word register can be used except RR0/R0.
  72. (based indexed address-BX)
  73. .fi
  74. .IP "segmented addresses"
  75. Segmented addresses require 23 bits, 7 bits for the segment number
  76. and 16 bits for the offset within a segment.
  77. So segment 0 contains addresses 0-FFFF, segment 1 contains addresses
  78. 10000-1FFFF, and so on.
  79. .br
  80. Assembler syntax of addresses and immediate data is as described above
  81. (modes IM, DA and X).
  82. Thus the assembler treats e.g. address 2BC0F as an address in segment 2
  83. with offset BC0F within the segment.
  84. There is also an explicit way to express this using the, more unusual,
  85. syntax <<segment>>offset.
  86. .br
  87. There are two internal representations of segmented addresses
  88. depending on the size of the offset. If the offset fits into 8 bits
  89. the address is stored in one word (the low-order byte containing
  90. the offset, bits 8 to 14 containing the segment number and
  91. bit 15 containing a zero) otherwise the address is stored in two
  92. words (the lower word containing the offset, the upper word as
  93. before but bit 15 containing 1 indicating that the offset is in
  94. the next word).
  95. This is important for instructions which has an operand of mode DA
  96. or X.
  97. .IP "extended branches"
  98. When the target address in a relative jump/call (JR/CALR)
  99. does not fit into the instruction format, the assembler generates
  100. a corresponding `normal' jump/call (JP/CALL).
  101. .SH EXAMPLE
  102. An example of z8000 assembly code.
  103. .nf
  104. .ta 8n 16n 24n 32n 40n 48n
  105. ! This z8000 assembly routine converts a positive number
  106. !(in R1) to a string representing the number and puts this
  107. !string into a buffer (R3 contains the starting address of
  108. !this buffer. The base is in R4 determining %x, %d or %o.
  109. .sect .text
  110. convert:
  111. exts RR0 !sign-extend R1
  112. div RR0, R4 !divide by the base
  113. test R1 !R1 contains the quotient
  114. jr EQ, 5f
  115. !if quotient is 0 convert is ready
  116. !else push remainder onto the stack
  117. push *RR14, R0
  118. calr convert !and again...
  119. pop R0, *RR14
  120. 5: add R0, $060 !add `0'
  121. cp R0, $071 !compare to `9'
  122. jr LE, 8f
  123. add R0, $7 !in case of %x `A'-`F'
  124. 8: ldb 0(R3), RL0 !put character into buffer
  125. inc R3
  126. ret
  127. .fi
  128. .SH "SEE ALSO"
  129. uni_ass(6),
  130. ack(1),
  131. ack.out(5),
  132. .br
  133. Z8000 PLZ/ASM Assembly Language Programming Manual, april 1979.
  134. .br
  135. AmZ8001/2 Processor Instruction Set, 1979.
  136. .SH BUGS
  137. You cannot use (reg16) instead of 0(reg16).
  138. .br
  139. Condition codes \fIZ\fP (meaning zero), \fIC\fP (meaning carry) and <nothing>
  140. (meaning always false) are not implemented.
  141. The first two because they also represent flags and the third one
  142. because it's useless.
  143. So for \fIZ\fP/\fIC\fP use \fIEQ\fP/\fIULT\fP.
  144. .br
  145. The z8000 assembly instruction set as described in the book
  146. \fIAmZ8001/2 Processor Instruction Set\fP differs from the one
  147. described in the manual \fIZ8000 PLZ/ASM Assembly Language Programming
  148. Manual\fP in that the book includes CLRL, LDL (format F5.1) and
  149. PUSHL (format F5.1) which all in fact do not (!) work.
  150. .br
  151. On the other side the book excludes SIN, SIND, SINDR, SINI, SINIR,
  152. SOUT, SOUTD, SOTDR, SOUTI and SOTIR.
  153. Whether these instructions do work as described in the manual has not
  154. been tested yet.