m68k2_as.6 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100
  1. .\" $Id$
  2. .TH M68K2_AS 6 "$Revision$"
  3. .ad
  4. .SH NAME
  5. m68k2_as \- assembler for Motorola 68000
  6. .SH SYNOPSIS
  7. ~em/lib.bin/m68k2/as [options] argument ...
  8. .SH DESCRIPTION
  9. This assembler is made with the general framework
  10. described in \fIuni_ass\fP(6). It is an assembler generating relocatable
  11. object code in \fIack.out\fP(5) format.
  12. .SH SYNTAX
  13. .IP registers
  14. The 68000 has the following registers:
  15. seven data-registers (d1 - d7), seven address-registers (a1 - a6, sp)
  16. of which sp is the system stack pointer, a program counter (pc),
  17. a status register (sr), and a condition codes register (ccr) which is actually
  18. just the low order byte of the status register.
  19. .IP "addressing modes"
  20. .nf
  21. .ta 8n 16n 24n 32n 40n 48n
  22. syntax meaning (name)
  23. reg contents of \fIreg\fP is operand, where \fIreg\fP is
  24. one of the registers mentioned above (register direct)
  25. (areg) contents of \fIareg\fP is address of operand, where
  26. \fIareg\fP is an address-register
  27. (address register indirect)
  28. (areg)+ same as (areg), but after the address is used,
  29. \fIareg\fP is incremented by the operand length
  30. (postincrement)
  31. -(areg) same as (areg), but before the address is used,
  32. \fIareg\fP is decremented by the operand length
  33. (predecrement)
  34. expr(areg)
  35. expr(pc) \fIexpr\fP + the contents of the register yields the
  36. address of the operand (displacement)
  37. expr(areg, ireg)
  38. expr(pc, ireg) \fIexpr\fP + the contents of the register + the contents
  39. of \fIireg\fP yields the address of the operand. \fIireg\fP is
  40. an address- or a data-register.
  41. \fIireg\fP may be followed by .w or .l indicating whether
  42. the size of the index is a word or a long
  43. (displacement with index)
  44. expr \fIexpr\fP is the address of the operand
  45. (absolute address)
  46. #expr \fIexpr\fP is the operand (immediate)
  47. .fi
  48. Some instructions have as operand a register list. This list consists of
  49. one or more ranges of registers separated by '/'s. A register range consists
  50. of either one register (e.g. d3) or two registers separated by a '-'
  51. (e.g. a2-a4, or d4-d5). The two registers must be in the same set (address-
  52. or data-registers) and the first must have a lower number than the second.
  53. .IP instructions
  54. Some instructions can have a byte, word, or longword operand.
  55. This may be indicated by prepending the mnemonic with .b, .w, or .l
  56. respectively. Default is .w.
  57. .SH "SEE ALSO"
  58. uni_ass(6),
  59. ack(1),
  60. ack.out(5),
  61. .br
  62. MC68000 16-bit microprocessor User's manual, Motorola Inc, 1979
  63. .SH EXAMPLE
  64. .sp 2
  65. .nf
  66. .ta 8n 16n 24n 32n 40n 48n 56n 64n
  67. .define .cii
  68. .sect .text
  69. .cii:
  70. movem.l a0/d0/d1,.savreg
  71. move.l (sp)+,a0 ! return address
  72. move (sp)+,d0 ! destination size
  73. sub (sp)+,d0 ! destination - source size
  74. bgt 1f
  75. sub d0,sp ! pop extra bytes
  76. bra 3f
  77. 1:
  78. move (sp),d1
  79. ext.l d1
  80. swap d1
  81. asr #1,d0
  82. 2:
  83. move.w d1,-(sp)
  84. sub #1,d0
  85. bgt 2b
  86. 3:
  87. move.l a0,-(sp)
  88. movem.l .savreg,a0/d0/d1
  89. rts
  90. .fi