i86_as.6 3.2 KB

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  1. .\" $Id$
  2. .TH I86_AS 6 "$Revision$"
  3. .ad
  4. .SH NAME
  5. i86_as \- assembler for Intel 8086
  6. .SH SYNOPSIS
  7. ~em/lib.bin/i86/as [options] argument ...
  8. .SH DESCRIPTION
  9. This assembler is made with the general framework
  10. described in \fIuni_ass\fP(6). It is an assembler generating relocatable
  11. object code in \fIack.out\fP(5) format.
  12. .SH SYNTAX
  13. .IP segments
  14. An address on the Intel 8086 consists of two pieces:
  15. a segment number and an offset. A memory address is computed as
  16. the segment number shifted left 4 bits + the offset.
  17. Assembly language addresses only give the offset, with the exception of
  18. the address of an inter-segment jump or call (see \fIaddressing modes\fP
  19. below).
  20. .IP registers
  21. The Intel 8086 has the following 16-bit registers:
  22. .br
  23. Four general registers: ax (accumulator), bx (base), cx (count), and dx (data).
  24. The upper halves and lower halves of these registers are separately
  25. addressable as ah, bh, ch, dh, and al, bl, cl, dl respectively.
  26. .br
  27. Two pointer registers: sp (stack pointer) and bp (base pointer).
  28. .br
  29. Two index registers: si (source index) and di (destination index).
  30. .br
  31. Four segment registers: cs (code), ds (data), ss (stack), and es (extra).
  32. .IP "addressing modes"
  33. .nf
  34. .ta 8n 16n 24n 32n 40n 48n
  35. syntax meaning
  36. expr the value of \fIexpr\fP is immediate data or
  37. an address offset. There is no special
  38. notation for immediate data.
  39. register one of the aforementioned general registers
  40. or their upper or lower halves, or one of the
  41. four segment registers.
  42. (expr) the value of expr is the address of the operand.
  43. (reg)
  44. expr (reg) the value of \fIexpr\fP (if present) + the contents of
  45. \fIreg\fP (which must be a pointer or an index register)
  46. is the address of the operand.
  47. (preg) (ireg)
  48. expr (preg) (ireg)
  49. the value of \fIexpr\fP (if present) + the contents of
  50. \fIpreg\fP (which must be a pointer register) + the
  51. contents of \fIireg\fP (which must be an index register)
  52. is the address of the operand.
  53. The next addressing mode is only allowed with the instructions
  54. "callf" or "jmpf".
  55. expr : expr the value of the first \fIexpr\fP is a segment number,
  56. the value of the second \fIexpr\fP is an address offset.
  57. The (absolute) address of the operand is computed
  58. as described above.
  59. .fi
  60. .IP instructions
  61. Each time an address is computed the processor decides which segment register
  62. to use. You can override the processor's choice by prefixing the instruction
  63. with one of eseg, cseg, sseg, or dseg; these prefixes indicate that the
  64. assembler should choose es, cs, ss, or ds instead.
  65. .br
  66. Example:
  67. .ti +8
  68. dseg movs
  69. .SH "SEE ALSO"
  70. uni_ass(6),
  71. ack(1),
  72. ack.out(5),
  73. .br
  74. MCS-86 assembly language reference manual, 1978, Intel Corporation
  75. .SH EXAMPLE
  76. .nf
  77. .ta 8n 16n 24n 32n 40n 48n
  78. An example of Intel 8086 assembly language:
  79. .sect .text
  80. _panic:
  81. push bp
  82. mov bp,sp
  83. .sect .data
  84. _35:
  85. .data2 24944
  86. .data2 26990
  87. .data2 14947
  88. .data2 32
  89. .sect .text
  90. call _disable
  91. mov ax,_35
  92. push ax
  93. call _str
  94. pop si
  95. push 4(bp)
  96. call _str
  97. pop si
  98. call _nlcr
  99. call _exit
  100. mov sp,bp
  101. pop bp
  102. ret
  103. .extern _nopanic
  104. _nopanic:
  105. push bp
  106. mov bp,sp
  107. .sect .data
  108. _38:
  109. .data2 28526
  110. .data2 24944
  111. .data2 26990
  112. .data2 14947
  113. .data2 32
  114. .sect .text
  115. mov ax,_38
  116. push ax
  117. call _str
  118. pop si
  119. push 4(bp)
  120. call _str
  121. pop si
  122. push 6(bp)
  123. call _octal
  124. pop si
  125. mov sp,bp
  126. pop bp
  127. ret
  128. .fi