i386_as.6 4.1 KB

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  1. .\" $Id$
  2. .TH I386_AS 6 "$Revision$"
  3. .ad
  4. .SH NAME
  5. i386_as \- assembler for Intel 80386
  6. .SH SYNOPSIS
  7. ~em/lib.bin/i386/as [options] argument ...
  8. .SH DESCRIPTION
  9. This assembler is made with the general framework
  10. described in \fIuni_ass\fP(6). It is an assembler generating relocatable
  11. object code in \fIack.out\fP(5) format.
  12. .SH SYNTAX
  13. .IP segments
  14. An address on the Intel 80386 consists of two pieces:
  15. a segment number and an offset.
  16. Usually, the segment number resides in a segment register, and
  17. assembly language addresses only give the offset, with the exception of
  18. the address of an inter-segment jump or call (see \fIaddressing modes\fP
  19. below).
  20. .IP registers
  21. The Intel 80386 has the following 32-bit registers:
  22. .br
  23. Four general registers: eax (accumulator), ebx (base), ecx (count), and edx (data).
  24. The low- and high order bytes of the low order words of these registers
  25. are separately addressable as ah, bh, ch, dh, and al, bl, cl, dl respectively.
  26. .br
  27. Two pointer registers: esp (stack pointer) and ebp (base pointer).
  28. .br
  29. Two index registers: esi (source index) and edi (destination index).
  30. .br
  31. Six segment registers: cs (code), ds (data), ss (stack), es (extra),
  32. fs (extra), and gs (extra).
  33. .IP "addressing modes"
  34. .nf
  35. .ta 8n 16n 24n 32n 40n 48n
  36. syntax meaning
  37. expr the value of \fIexpr\fP is immediate data or
  38. an address offset. There is no special
  39. notation for immediate data.
  40. register one of the aforementioned general registers
  41. or their upper or lower halves, or one of the
  42. four segment registers.
  43. (expr) the value of expr is the address of the operand.
  44. (reg)
  45. expr (reg) the value of \fIexpr\fP (if present) + the contents of
  46. \fIreg\fP (which must be a pointer or an index register)
  47. is the address of the operand.
  48. (reg1) (reg2)
  49. expr (reg1) (reg2)
  50. the value of \fIexpr\fP (if present) + the contents of
  51. \fIreg1\fP + the
  52. contents of \fIreg2\fP is the address of the operand.
  53. (reg1) (reg2 * scale)
  54. expr (reg1) (reg2 * scale)
  55. the value of \fIexpr\fP (if present) + the contents of
  56. \fIreg1\fP + the
  57. contents of \fIreg2\fP multiplied by \fIscale\fP,
  58. is the address of the operand.
  59. \fIscale\fP can be either 1, 2, 4, or 8.
  60. This mode is only allowed for 32-bit addressing.
  61. The next addressing mode is only allowed with the instructions
  62. "callf" or "jmpf".
  63. expr : expr the value of the first \fIexpr\fP is a segment number,
  64. the value of the second \fIexpr\fP is an address offset.
  65. The following two addressing modes are only allowed with Intel 80[23]87 floating
  66. point processor instructions:
  67. st
  68. st(num) addresses the floating point processor stack. \fInum\fP
  69. must be between 0 and 7. st is the same as st(0).
  70. .fi
  71. .IP prefixes
  72. Each time an address is computed the processor decides which segment register
  73. to use. You can override the processor's choice by prefixing the instruction
  74. with one of eseg, cseg, sseg, dseg, fseg, or gseg; these prefixes indicate that the
  75. processor should choose es, cs, ss, ds, fs, or gs instead.
  76. .br
  77. Example:
  78. .ti +8
  79. dseg movs
  80. .IP ""
  81. There is also an address size toggle, which switches between 32-bit and
  82. 16-bit address generation: a16 or a32. Normally, the assembler generates
  83. 32-bit addresses; both of these toggles make it generate 16-bit addresses
  84. for the next instruction, and also generate code to set the processor
  85. temporarily in 16-bit address mode.
  86. .IP ""
  87. There is also an operand size toggle, which switches between 32-bit and
  88. 16-bit operands: o16 or o32. Normally, the assembler generates
  89. 32-bit operands; both of these toggles make it generate 16-bit operands
  90. for the next instruction, and also generate code to set the processor
  91. temporarily in 16-bit operand mode.
  92. .IP ""
  93. Prefixes only affect the next instruction.
  94. .IP ""
  95. There are also the .use32 and .use16 assembler directives, which do not
  96. generate code, but change the assemblers default for operand and address sizes.
  97. Obviously, .use16 gives 16-bit modes, .use32 gives 32-bit modes.
  98. This is useful for assembling real mode 80386 code, or pure 16-bit
  99. modules (that do not have the D-bit set in the segment descriptor).
  100. These assembler directives stay in effect until there is another one.
  101. .SH "SEE ALSO"
  102. uni_ass(6),
  103. ack(1),
  104. ack.out(5),
  105. .br
  106. 80386 Programmer's Reference Manual, 1986, Intel Corporation