6809_as.6 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150
  1. .\" $Id$
  2. .TH 6809_AS 6 "$Revision$"
  3. .ad
  4. .SH NAME
  5. 6809_as \- assembler for 6809
  6. .SH SYNOPSIS
  7. ~em/lib.bin/6809/as [options] argument ...
  8. .SH DESCRIPTION
  9. This assembler is made with the general framework
  10. described in \fIuni_ass\fP(6). It is an assembler generating relocatable
  11. object code in \fIack.out\fP(5) format.
  12. .SH SYNTAX
  13. .IP registers
  14. The 6809 contains four 8-bit registers registers:
  15. two accumulators (a and b),
  16. a direct page register (dp),
  17. and a condition code register (cc),
  18. and five 16-bit registers:
  19. two index registers (x and y),
  20. a user an a hardware stack pointer (u resp. s),
  21. and a program counter (pc).
  22. The index registers and the stack pointers are indexable.
  23. Accumulators a and b can be concatenated to form
  24. the double accumulator d,
  25. of which a is the high and b is the low byte.
  26. An instruction that refers to accumulator a
  27. has an "a" as last character.
  28. In the same way a "b" means that the instruction
  29. uses b as accumulator.
  30. .IP "pseudo instructions"
  31. The 6809 assembler recognizes one additional instruction
  32. that is not translated into a machine instruction: setdp.
  33. It expects an expression as argument.
  34. This is used for efficient address encoding of some addressing
  35. mode (see below).
  36. .IP "addressing modes"
  37. .nf
  38. .ta 8n 16n 24n 32n 40n 48n
  39. syntax meaning (name)
  40. reg The operand of the instruction is in \fIreg\fP.
  41. reglist \fIreglist\fP is a either list of registers, seperated
  42. by ','s, or the word "all". It encodes in a register
  43. save mask, where "all" means all registers, that can
  44. be used by the push-pull instructions pshs, pshu,
  45. puls, and pulu.
  46. <expr The one-byte value of \fIexpr\fP is an address within
  47. a 256-byte page. The particular page in use is
  48. indicated by the contents of dp, so \fIexpr\fP is the
  49. low byte of the effective address of the operand,
  50. and dp the high byte. (direct)
  51. >expr The two-byte value of \fIexpr\fP is the exact memory
  52. address. Not that this mode always requires one
  53. byte more than "<expr". (extended)
  54. expr The value of \fIexpr\fP is an address.
  55. Except for long branches, this value is examined
  56. first to see if a short encoding is possible.
  57. When the instruction is a short branch, the value
  58. is checked to see if the address is not too remote,
  59. because in that case this branch is automatically
  60. replaced by a long branch. When the instruction is
  61. not a branch, the high byte of the value is compared
  62. with the value of the argument of the last setdp
  63. pseudo. If they are equal, this mode is replaced by
  64. "<expr", else by ">expr".
  65. (relative for branch-instructions)
  66. #expr The value of \fIexpr\fP is one- or two-byte immediate
  67. data. (immediate)
  68. (expr) The value of \fIexpr\fP is a pointer to the address
  69. of the operand. (indirect)
  70. expr, reg The value of \fIexpr\fP added to the contents of \fIreg\fP
  71. (which must be a 16-bit register) yields the
  72. effective address of the operand.
  73. (constant-offset indexed)
  74. , ireg The contents of \fIireg\fP (which must be indexable)
  75. yields the effective address of the operand.
  76. (constant-offset indexed)
  77. (expr, reg) The value of \fIexpr\fP added to the contents of \fIreg\fP
  78. (which must be a 16-bit register) yields a pointer
  79. to the effective address of the operand.
  80. (constant-offset indexed indirect)
  81. (, ireg) The contents of \fIireg\fP (which must be indexable)
  82. yields a pointer to the effective address of the
  83. operand. (constant-offset indexed indirect)
  84. ac, ireg The contents of \fIac\fP (which must be an accumulator)
  85. added to the contents of \fIireg\fP (which must be
  86. indexable) yields the effective address of the
  87. operand. (accumulator indexed)
  88. (ac, ireg) The contents of \fIac\fP (which must be an accumulator)
  89. added to the contents of \fIireg\fP (which must be
  90. indexable) yields a pointer to the effective address
  91. of the operand. (accumulator indexed indirect)
  92. ,ireg+
  93. ,ireg++ The contents of \fIireg\fP (which must be indexable) is
  94. used as effective address of the operand. After that
  95. it is incremented by 1 (+) or 2 (++).
  96. (auto-increment)
  97. (,ireg++) The contents of \fIireg\fP (which must be indexable) is
  98. used as a pointer to the effective address of the
  99. operand. After that it is incremented by 2.
  100. (auto-increment indirect)
  101. ,-ireg
  102. ,--ireg \fIireg\fP (which must be indexable) is decremented
  103. by 1 (-) or 2 (--). After that, its contents is used
  104. as effective address of the operand.
  105. (auto-decrement)
  106. (,--ireg) \fIireg\fP (which must be indexable) is decremented by 2.
  107. After that, its contents is used as a pointer to the
  108. effective address of the operand.
  109. (auto-decrement indirect)
  110. .fi
  111. .SH "SEE ALSO"
  112. uni_ass(6),
  113. ack(1),
  114. ack.out(5),
  115. .br
  116. MC6809 preliminary programming manual, Motorola Inc., First Edition, 1979
  117. .SH EXAMPLE
  118. An example of 6809 assembly code.
  119. .nf
  120. .ta 8n 16n 24n 32n 40n 48n
  121. .sect .text
  122. contby = 80
  123. compgo: lda #contby
  124. ldx #table - 2 !start of table
  125. clrb
  126. co1: addb #2
  127. lsra
  128. bcc co1
  129. jmp (b, x) !accumulator offset indirect
  130. .fi