ppu.c 26 KB

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  1. /*
  2. * PPU emulation - The peTI-NESulator Project
  3. * ppu.c
  4. *
  5. * Define and emulate the PPU (Picture Processing Unit) of the real NES
  6. *
  7. * Created by Manoel TRAPIER.
  8. * Copyright (c) 2003-2018 986-Studio. All rights reserved.
  9. *
  10. */
  11. #include <stdio.h>
  12. #include <stdlib.h>
  13. #include <stdint.h>
  14. #include <os_dependent.h>
  15. #define __TINES_PPU_INTERNAL__
  16. #include <ppu/ppu.h>
  17. #include <ppu/ppu.memory.h>
  18. #include <ppu/ppu.debug.h>
  19. #include <memory/manager.h>
  20. #include <os_dependent.h>
  21. #define __TINES_PLUGINS__
  22. #include <plugins/manager.h>
  23. extern int VBLANK_TIME;
  24. extern volatile int frame;
  25. extern volatile uint32_t IPS, FPS;
  26. extern uint32_t ColorPalette[9 * 63];
  27. extern short IRQScanHit;
  28. extern short SZHit;
  29. typedef struct spriteData
  30. {
  31. uint8_t palette;
  32. uint8_t flip_h;
  33. uint8_t flip_v;
  34. uint8_t priority;
  35. uint8_t tile;
  36. uint8_t bank;
  37. uint8_t y;
  38. uint8_t x;
  39. uint8_t rel_y;
  40. uint8_t inUse;
  41. } spriteData;
  42. /* PPU registers */
  43. /* NT: Name Table */
  44. uint8_t PPU_Reg_NT;
  45. /* AT: Attribute/Color Table */
  46. uint8_t PPU_Reg_AT;
  47. /* FV: Fine Vertical Scroll latch/counter */
  48. uint8_t PPU_Reg_FV;
  49. /* HV: Fine Horizontal Scroll latch/counter */
  50. uint8_t PPU_Reg_FH;
  51. /* VT: Vertical Tile indev latch/counter */
  52. uint8_t PPU_Reg_VT;
  53. /* HT: Horizontal Tile indev latch/counter */
  54. uint8_t PPU_Reg_HT;
  55. /* V: Vertical Name Table Selection latch/counter */
  56. uint8_t PPU_Reg_V;
  57. /* H: Horizontal Name Table Selection latch/counter */
  58. uint8_t PPU_Reg_H;
  59. /* S: Playfield pattern table selection latch */
  60. uint16_t PPU_Reg_S;
  61. /* PAR: Picture Address Register */
  62. uint8_t PPU_Reg_PAR;
  63. /* AR: Tile Attribute (palette select) value latch */
  64. uint8_t PPU_Reg_AR;
  65. uint16_t PPU_Reg_Counter;
  66. /* PPU Memory Areas */
  67. uint8_t *ppu_mem_nameTables;
  68. uint8_t *ppu_mem_patternTables;
  69. uint8_t *ppu_mem_paletteValues;
  70. uint8_t ppu_mem_spritesTable[0x100];
  71. uint8_t ppu_mem_sptrTablePtr;
  72. /* Some other PPU "registers" */
  73. uint8_t ppu_VramAccessFlipFlop;
  74. uint8_t ppu_inVBlankTime;
  75. uint8_t ppu_spriteZeroHit;
  76. uint8_t ppu_scanlineSpriteOverflow;
  77. uint8_t ppu_bgColor;
  78. /* CR #1 variables */
  79. uint16_t ppu_spritePatternTable;
  80. uint8_t ppu_spriteSize;
  81. uint8_t ppu_addrIncrement;
  82. uint8_t ppu_execNMIonVBlank;
  83. /* CR #2 variables */
  84. uint8_t ppu_spriteVisibility;
  85. uint8_t ppu_backgroundVisibility;
  86. uint8_t ppu_spriteClipping;
  87. uint8_t ppu_backgroundClipping;
  88. uint8_t ppu_displayType;
  89. uint8_t ppu_mirrorMode;
  90. uint8_t ppu_singleScreenMode;
  91. uint8_t ppu_screenMode;
  92. #define PPU_MEM_PATTERNTABLES_SIZE 0x2000
  93. #define PPU_MEM_NAMETABLE_SIZE 0x1000
  94. #define PPU_MEM_PALETTEVALUES_SIZE 0x100 /* in fact its 20 but we must allocate a least one page */
  95. #define PPU_SPRITE_FLAGS_VFLIP ( 1 << 7 )
  96. #define PPU_SPRITE_FLAGS_HFLIP ( 1 << 6 )
  97. #define PPU_SPRITE_FLAGS_BGPRIO ( 1 << 5 )
  98. #define PPU_SPRITE_FLAGS_UPPERCOLOR ( 0x03 )
  99. #define PPU_FLAG_SR_VBLANK ( 1 << 7 )
  100. #define PPU_FLAG_SR_SPRT0 ( 1 << 6 )
  101. #define PPU_FLAG_SR_8SPRT ( 1 << 5 )
  102. #define PPU_FLAG_SR_RDWRALLOW ( 1 << 4 )
  103. #define PPU_CR1_SPRTSIZE ( 1 << 5 )
  104. #define PPU_CR1_EXECNMI ( 1 << 7 )
  105. #define PPU_CR2_BGVISIBILITY ( 1 << 3 )
  106. #define PPU_CR2_SPRTVISIBILITY ( 1 << 4 )
  107. int ppu_init()
  108. {
  109. int i;
  110. /*uint8_t defaultColors[] = { 0x09,0x01,0x00,0x01,0x00,0x02,0x02,0x0D,0x08,0x10,0x08,0x24,0x00,0x00,0x04,0x2C,
  111. 0x09,0x01,0x34,0x03,0x00,0x04,0x00,0x14,0x08,0x3A,0x00,0x02,0x00,0x20,0x2C,0x08 };*/
  112. if ( ppu_initMemory() )
  113. return -1;
  114. /* Set ppu memory parameters */
  115. /* First: Allocate each memory zone */
  116. ppu_mem_patternTables = (uint8_t *) malloc(PPU_MEM_PATTERNTABLES_SIZE);
  117. if ( !ppu_mem_patternTables )
  118. return -1;
  119. ppu_mem_nameTables = (uint8_t *) malloc(PPU_MEM_NAMETABLE_SIZE);
  120. if ( !ppu_mem_nameTables )
  121. return -1;
  122. ppu_mem_paletteValues = (uint8_t *) malloc(PPU_MEM_PALETTEVALUES_SIZE);
  123. if ( !ppu_mem_paletteValues )
  124. return -1;
  125. console_printf(Console_Default, "ppu_mem_nameTables :%p\n"
  126. "ppu_mem_patternTables:%p\n"
  127. "ppu_mem_paletteValues:%p\n",
  128. ppu_mem_nameTables,
  129. ppu_mem_patternTables,
  130. ppu_mem_paletteValues);
  131. /* Second: make the ppu memory manager point on the memory zones */
  132. ppu_setPagePtr8k(0x00, ppu_mem_patternTables);
  133. ppu_setPagePtr4k(0x20, ppu_mem_nameTables);
  134. ppu_setPagePtr(0x3F, ppu_mem_paletteValues);
  135. for ( i = 0x00 ; i < 0x0F ; i++ )
  136. ppu_setPageGhost(0x30 + i, true, 0x20 + i);
  137. /* Third: set registers to defaults */
  138. /* Now test the memory ! */
  139. /* Fille PPU memory with garbage */
  140. for ( i = 0x0000 ; i < 0x2000 ; i++ )
  141. ppu_mem_patternTables[i] = rand() % 0xFF;
  142. for ( i = 0x0000 ; i < 0x1000 ; i++ )
  143. ppu_mem_nameTables[i] = rand() % 0xFF;
  144. for ( i = 0x0000 ; i < 0x001F ; i++ )
  145. ppu_mem_paletteValues[i] = rand() % 0xFF;
  146. //memcpy(ppu_mem_paletteValues, defaultColors, 32);
  147. /* Set some other variables */
  148. ppu_VramAccessFlipFlop = 0;
  149. ppu_addrIncrement = 1;
  150. ppu_spritePatternTable = 0;
  151. ppu_spriteSize = 8;
  152. ppu_execNMIonVBlank = 0;
  153. ppu_spriteVisibility = 0;
  154. ppu_backgroundVisibility = 0;
  155. ppu_spriteClipping = 0;
  156. ppu_backgroundClipping = 0;
  157. ppu_displayType = 0;
  158. ppu_inVBlankTime = 0;
  159. ppu_bgColor = 0;
  160. /* Set PPU registers on CPU side */
  161. set_page_rd_hook(0x20, ppu_readReg);
  162. set_page_wr_hook(0x20, ppu_writeReg);
  163. set_page_readable(0x20, true);
  164. set_page_writeable(0x20, true);
  165. /* Set PPU Ghost Registers */
  166. for ( i = 0x21 ; i < 0x40 ; i++ )
  167. set_page_ghost(i, true, 0x20);
  168. /* allocate the PPU Video memory */
  169. graphics_init();
  170. return 0;
  171. }
  172. void ppu_setMirroring(uint8_t direction)
  173. {
  174. if ( ppu_screenMode != PPU_SCMODE_NORMAL )
  175. return;
  176. if ( ppu_mirrorMode == direction )
  177. return; /* Same value, no need to change! */
  178. switch(direction)
  179. {
  180. default:
  181. direction = PPU_MIRROR_HORIZTAL;
  182. ppu_mirrorMode = direction;
  183. case PPU_MIRROR_HORIZTAL: /* Horizontal */
  184. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x000);
  185. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x000);
  186. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x400);
  187. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0x400);
  188. break;
  189. case PPU_MIRROR_VERTICAL: /* Vertical */
  190. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x000);
  191. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x400);
  192. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x000);
  193. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0x400);
  194. break;
  195. }
  196. ppu_mirrorMode = direction;
  197. }
  198. void ppu_setSingleScreen(uint8_t screen)
  199. {
  200. if ( ppu_screenMode != PPU_SCMODE_SINGLE )
  201. return;
  202. if ( ppu_singleScreenMode == screen )
  203. return; /* Same value, no need to change! */
  204. switch(screen)
  205. {
  206. default:
  207. screen = PPU_SCREEN_000;
  208. ppu_singleScreenMode = screen;
  209. case PPU_SCREEN_000: /* 0x2000 */
  210. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x000);
  211. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x000);
  212. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x000);
  213. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0x000);
  214. break;
  215. case PPU_SCREEN_400: /* 0x2400 */
  216. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x400);
  217. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x400);
  218. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x400);
  219. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0x400);
  220. break;
  221. case PPU_SCREEN_800: /* 0x2800 */
  222. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x800);
  223. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x800);
  224. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x800);
  225. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0x800);
  226. break;
  227. case PPU_SCREEN_C00: /* 0x2C00 */
  228. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0xC00);
  229. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0xC00);
  230. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0xC00);
  231. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0xC00);
  232. break;
  233. }
  234. ppu_singleScreenMode = screen;
  235. }
  236. /* Let set display to
  237. Single screen (1 NT with mirroring)
  238. Normal screen (2 NT with mirroring)
  239. Four screen (4 NT without mirroring) */
  240. void ppu_setScreenMode(uint8_t mode)
  241. {
  242. if ( ppu_screenMode == mode )
  243. return; /* Same value, no need to change! */
  244. ppu_screenMode = mode;
  245. switch(mode)
  246. {
  247. case PPU_SCMODE_SINGLE: /* Single screen (1 NT with mirroring) */
  248. ppu_setSingleScreen(~ppu_singleScreenMode);
  249. break;
  250. default:
  251. mode = PPU_SCMODE_NORMAL;
  252. ppu_screenMode = mode;
  253. case PPU_SCMODE_NORMAL: /* Normal screen (2 NT with mirroring) */
  254. ppu_setMirroring(~ppu_mirrorMode);
  255. break;
  256. case PPU_SCMODE_FOURSC: /* Four screen (4 NT withou mirroring) */
  257. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x000);
  258. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x400);
  259. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x800);
  260. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0xC00);
  261. break;
  262. }
  263. }
  264. /* update whole counters */
  265. void ppu_updateCounters()
  266. {
  267. /*
  268. +---------------+-----------------------------------------------+
  269. | |+===++=++=++=====++=====++===++=++========++==+|
  270. |PPU registers || FV||V||H|| VT|| HT|| FH||S|| PAR||AR||
  271. |PPU counters |+---++-++-++-----++-----++===++=++========++==+|
  272. | |+===++=++=++=====++=====+ |
  273. +---------------+-----------------------------------------------+
  274. |2007 access | DC B A 98765 43210 |
  275. +===============+===============================================+
  276. 8421 8421 8421 8421
  277. -------------------
  278. 1111 1100 0000 0000
  279. 5432 1098 7654 3210
  280. _AAA BCDD DDDE EEEE
  281. */
  282. PPU_Reg_Counter = ( PPU_Reg_FV & 0x07 ) << 12;
  283. PPU_Reg_Counter |= PPU_Reg_V << 11;
  284. PPU_Reg_Counter |= PPU_Reg_H << 10;
  285. PPU_Reg_Counter |= PPU_Reg_VT << 5;
  286. PPU_Reg_Counter |= PPU_Reg_HT;
  287. }
  288. int ppu_hblank(uint16_t scanline)
  289. {
  290. /* Sprite to display on current scanline */
  291. spriteData scanSprites[8];
  292. ppu_scanlineSpriteOverflow = 0;
  293. if ( scanline == 0 )
  294. {
  295. if ( ( ppu_spriteVisibility != 0 ) || ( ppu_backgroundVisibility != 0 ) )
  296. ppu_updateCounters();
  297. }
  298. if ( scanline < 240 )
  299. {
  300. int i;
  301. uint8_t spriteCount = 0;
  302. /* Search for sprites on current scanline */
  303. for (i = 0 ; i < 8 ; i++)
  304. {
  305. scanSprites[i].inUse = 0;
  306. }
  307. for (i = 0 ; i < 64 && spriteCount < 8; i++)
  308. {
  309. uint8_t spriteY = ppu_mem_spritesTable[i*4] + 1;
  310. if ((scanline >= spriteY) && (scanline < (spriteY + ppu_spriteSize)))
  311. {
  312. /* This sprite is on the scanline */
  313. scanSprites[spriteCount].inUse = 1;
  314. scanSprites[spriteCount].x = ppu_mem_spritesTable[i*4 + 3];
  315. scanSprites[spriteCount].y = spriteY;
  316. scanSprites[spriteCount].rel_y = scanline - scanSprites[spriteCount].y;
  317. scanSprites[spriteCount].tile = ppu_mem_spritesTable[i * 4 + 1];
  318. scanSprites[spriteCount].bank = ppu_mem_spritesTable[i * 4 + 1] & 0x01;
  319. scanSprites[spriteCount].flip_h = ( ppu_mem_spritesTable[i * 4 + 2] & PPU_SPRITE_FLAGS_HFLIP )?1:0;
  320. scanSprites[spriteCount].flip_v = ( ppu_mem_spritesTable[i * 4 + 2] & PPU_SPRITE_FLAGS_VFLIP )?1:0;
  321. scanSprites[spriteCount].palette = ( ppu_mem_spritesTable[i * 4 + 2] & PPU_SPRITE_FLAGS_UPPERCOLOR ) & 0x0F;
  322. scanSprites[spriteCount].priority = ( ppu_mem_spritesTable[i * 4 + 2] & PPU_SPRITE_FLAGS_BGPRIO )?1:0;
  323. spriteCount++;
  324. }
  325. }
  326. ppu_bgColor = ppu_readMemory(0x3F, 00);
  327. /* For each PPU pixel of this scanline */
  328. for ( i = 0 ; i < 256 ; i++ )
  329. {
  330. uint16_t addr;
  331. uint8_t value;
  332. uint8_t pixelColor = 0;
  333. uint8_t BgColor = 0;
  334. /* Set the current pixel color to the bg color */
  335. pixelColor = ppu_bgColor;
  336. BgColor = 0;
  337. /* Compute current pixel bg color if bg is visible */
  338. if (( ppu_backgroundVisibility == 1 ) && (!getKeyStatus('B')))
  339. {
  340. if ( ((i < 8) && (!ppu_backgroundClipping)) || (i >= 8))
  341. {
  342. addr = ( PPU_Reg_Counter & 0x0C00 );
  343. addr = addr | 0x03C0;
  344. addr |= ( PPU_Reg_Counter >> 4 ) & 0x0038;
  345. addr |= ( PPU_Reg_Counter >> 2 ) & 0x0007;
  346. PPU_Reg_AR = ppu_readMemory(0x20 | ( ( addr >> 8 ) & 0x0F ), addr & 0xFF);
  347. PPU_Reg_AR = PPU_Reg_AR >> ( ( ( PPU_Reg_Counter >> 4 ) & 0x04 ) | ( ( PPU_Reg_Counter ) & 0x02 ) );
  348. PPU_Reg_AR = ( PPU_Reg_AR << 2 ) & 0x0C;
  349. PPU_Reg_PAR = ppu_readMemory(0x20 | ( ( PPU_Reg_Counter >> 8 ) & 0x0F ), PPU_Reg_Counter & 0xFF);
  350. addr = PPU_Reg_S;
  351. addr |= ( ( PPU_Reg_PAR & 0xFF ) << 4 );
  352. addr |= ( ( PPU_Reg_Counter >> 12 ) & 0x07 );
  353. value = ppu_readMemory(( addr >> 8 ), addr);
  354. BgColor = ( value & ( 1 << ( 7 - ( i + PPU_Reg_FH ) % 8 ) ) )?0x01:0;
  355. value = ppu_readMemory(( addr >> 8 ), addr | 0x08);
  356. BgColor |= ( value & ( 1 << ( 7 - ( i + PPU_Reg_FH ) % 8 ) ) )?0x02:0;
  357. if ( BgColor > 0x00 )
  358. {
  359. BgColor |= PPU_Reg_AR;
  360. BgColor &= 0x0F;
  361. pixelColor = ppu_readMemory(0x3F, BgColor);
  362. }
  363. if ( ( ( i + PPU_Reg_FH ) % 8 ) == 7 )
  364. {
  365. uint16_t tmp_HHT = 0;
  366. tmp_HHT = ( ( PPU_Reg_Counter >> 5 ) & 0x0020 ) |
  367. ( PPU_Reg_Counter & 0x001F );
  368. tmp_HHT = ( tmp_HHT + 1 ) & 0x003F;
  369. /* Reassemble with HT & H */
  370. PPU_Reg_Counter = ( PPU_Reg_Counter & 0xFBE0 ) |
  371. ( ( tmp_HHT & 0x0020 ) << 5 ) |
  372. ( tmp_HHT & 0x001F );
  373. }
  374. }
  375. #if 0
  376. // ISPAL
  377. else
  378. {
  379. pixelColor = 0x1D;
  380. }
  381. #endif
  382. }
  383. /* Now calculate if there is a sprite here and sprite visibility is on */
  384. if ( ppu_spriteVisibility == 1 )
  385. {
  386. if (((!ppu_spriteClipping) && (i < 8)) || (i >= 8))
  387. {
  388. uint32_t j;
  389. for( j = 0 ; j < 8 ; j++)
  390. {
  391. spriteData *sprite = &scanSprites[j];
  392. int8_t spriteRelX;
  393. if ( sprite->inUse == 0 )
  394. break;
  395. spriteRelX = i - sprite->x;
  396. if ( ( spriteRelX >= 0 ) && ( spriteRelX < 8 ) )
  397. {
  398. uint8_t SpriteColor = 0;
  399. /* Get sprite tile address */
  400. if ( ppu_spriteSize == 8 )
  401. {
  402. addr = ( sprite->tile << 4 ) + ppu_spritePatternTable;
  403. }
  404. else
  405. {
  406. if ( sprite->rel_y < 8 )
  407. {
  408. addr = ( ( ( sprite->tile & 0xFE ) + ( sprite->flip_v?1:0 ) ) << 4 ) +
  409. ( ( sprite->bank )?0x1000:0x0000 );
  410. }
  411. else
  412. {
  413. addr = ( ( ( sprite->tile & 0xFE ) + ( sprite->flip_v?0:1 ) ) << 4 ) +
  414. ( ( sprite->bank )?0x1000:0x0000 );
  415. }
  416. }
  417. if ( sprite->flip_v )
  418. {
  419. addr += 7;
  420. addr -= sprite->rel_y % 8;
  421. }
  422. else
  423. {
  424. addr += sprite->rel_y % 8;
  425. }
  426. if ( sprite->flip_h )
  427. {
  428. value = ppu_readMemory(( addr >> 8 ), addr);
  429. SpriteColor = ( value & ( 1 << ( spriteRelX ) ) )?0x01:0;
  430. value = ppu_readMemory(( addr >> 8 ), addr | 0x08);
  431. SpriteColor |= ( value & ( 1 << ( spriteRelX ) ) )?0x02:0;
  432. }
  433. else
  434. {
  435. value = ppu_readMemory(( addr >> 8 ), addr);
  436. SpriteColor = ( value & ( 1 << ( 7 - ( spriteRelX ) ) ) )?0x01:0;
  437. value = ppu_readMemory(( addr >> 8 ), addr | 0x08);
  438. SpriteColor |= ( value & ( 1 << ( 7 - ( spriteRelX ) ) ) )?0x02:0;
  439. }
  440. /* If we get a color different from 0, the pixel is not transparent */
  441. if ( SpriteColor > 0 )
  442. {
  443. /* Add second part of the colour */
  444. SpriteColor |= ( ( sprite->palette ) << 2 );
  445. SpriteColor &= 0x0F;
  446. if ( j == 0 )
  447. {
  448. /* Sprite 0 */
  449. if ( ( BgColor != 0 ) && ( !ppu_spriteZeroHit ) )
  450. {
  451. ppu_spriteZeroHit = ( ppu_backgroundVisibility )?1:0;
  452. if ( ppu_spriteZeroHit )
  453. SZHit = scanline;
  454. }
  455. }
  456. if ( sprite->priority )
  457. {
  458. if ( SpriteColor > 0x00 )
  459. {
  460. if ( BgColor == 0 )
  461. {
  462. pixelColor = ppu_readMemory(0x3F, ( 0x10 + SpriteColor ));
  463. }
  464. break;
  465. }
  466. }
  467. else
  468. {
  469. if ( SpriteColor != 0x00 )
  470. {
  471. pixelColor = ppu_readMemory(0x3F, ( 0x10 + SpriteColor ));
  472. break;
  473. }
  474. }
  475. }
  476. }
  477. }
  478. }
  479. }
  480. /* Set to monochrome if needed */
  481. if ( ppu_displayType )
  482. pixelColor &= 0x30;
  483. /* draw the pixel */
  484. graphics_drawpixel(i, scanline, pixelColor);
  485. }
  486. if (spriteCount > 8)
  487. {
  488. ppu_scanlineSpriteOverflow = 1;
  489. }
  490. if ( ppu_backgroundVisibility == 1 )
  491. {
  492. uint16_t tmp_VVTFV = 0;
  493. tmp_VVTFV = ( ( PPU_Reg_Counter >> 3 ) & 0x0100 ) | /* V */
  494. ( ( PPU_Reg_Counter >> 2 ) & 0x00F8 ) | /* VT */
  495. ( ( PPU_Reg_Counter >> 12 ) & 0x0007 ); /* FV */
  496. tmp_VVTFV++;
  497. if ( ( tmp_VVTFV & 0x0F8 ) == 0xF0 )
  498. {
  499. tmp_VVTFV &= ~0x0F8;
  500. tmp_VVTFV ^= 0x100;
  501. }
  502. PPU_Reg_Counter = ( PPU_Reg_Counter & 0x041F ) |
  503. ( ( tmp_VVTFV & 0x0100 ) << 3 ) | /* V */
  504. ( ( tmp_VVTFV & 0x00F8 ) << 2 ) | /* VT */
  505. ( ( tmp_VVTFV & 0x0007 ) << 12 ); /* FV */
  506. /* Update H & HT */
  507. PPU_Reg_Counter = ( PPU_Reg_Counter & ~0x041F ) |
  508. ( PPU_Reg_H << 10 ) |
  509. PPU_Reg_HT;
  510. }
  511. }
  512. /* Increment only V, VT & FV*/
  513. /*
  514. 8421 8421 8421 8421
  515. -------------------
  516. 1111 1100 0000 0000
  517. 5432 1098 7654 3210
  518. _AAA BCDD DDDE EEEE
  519. xxx x xx xxx : vvtfv = 7BE0
  520. x x xxxx : hht
  521. B DDDD DAAA : vvtfv
  522. CE EEEE : hht
  523. A = FV
  524. B = V
  525. C = H
  526. D = VT
  527. E = HT
  528. */
  529. if ( scanline == 239 )
  530. {
  531. ppu_inVBlankTime = 1;
  532. // textprintf_ex(Buffer, font, 260, 3, 4, 0, "FPS : %ld (CPU@~%2.2fMhz : %d%%)", FPS, (float) (((float) IPS) / 1000000.0), (int) ((((float) IPS) / 1770000.0) * 100.0));
  533. graphics_blit(0, 0, 256, 240);
  534. return ppu_execNMIonVBlank;
  535. }
  536. /* Debug tools */
  537. /*if ( scanline == SZHit )
  538. {
  539. graphics_drawline(0, scanline, 256, scanline, 0x12);
  540. }
  541. if ( scanline == IRQScanHit )
  542. {
  543. graphics_drawline(0, scanline, 256, scanline, 0x13);
  544. }*/
  545. /* */
  546. if ( scanline == ( 239 + VBLANK_TIME ) + 0 )
  547. {
  548. ppu_inVBlankTime = 0;
  549. ppu_spriteZeroHit = 0;
  550. ppu_scanlineSpriteOverflow = 0;
  551. }
  552. return 0;
  553. }
  554. uint8_t PPU_RegValues[8];
  555. uint8_t ppu_readReg(uint8_t id)
  556. {
  557. id &= 0x07;
  558. static uint8_t garbage;
  559. static uint8_t lastValue;
  560. switch(id)
  561. {
  562. default:
  563. garbage = PPU_RegValues[id];
  564. break;
  565. case 0x02: /* PPU Status Register */
  566. /* Reset VRam 2005/2006 flipflop */
  567. ppu_VramAccessFlipFlop = 0;
  568. garbage = 0;
  569. garbage |= ( ppu_inVBlankTime != 0 )?PPU_FLAG_SR_VBLANK:0;
  570. garbage |= ( ppu_spriteZeroHit != 0 )?PPU_FLAG_SR_SPRT0:0;
  571. garbage |= ( ppu_scanlineSpriteOverflow != 0 )?PPU_FLAG_SR_8SPRT:0;
  572. ppu_inVBlankTime = 0;
  573. break;
  574. case 0x04: /* SPR-RAM I/O */
  575. garbage = ppu_mem_spritesTable[ppu_mem_sptrTablePtr];
  576. break;
  577. case 0x07: /* VRAM I/O */
  578. if ( PPU_Reg_Counter < 0x3F00 )
  579. {
  580. garbage = lastValue;
  581. lastValue = ppu_readMemory(( PPU_Reg_Counter >> 8 ) & 0x3F,
  582. PPU_Reg_Counter & 0xFF);
  583. }
  584. else
  585. {
  586. lastValue = ppu_readMemory(0x2F,
  587. PPU_Reg_Counter & 0xFF);
  588. garbage = ppu_readMemory(0x3F,
  589. PPU_Reg_Counter & 0xFF);
  590. }
  591. PPU_Reg_Counter += ppu_addrIncrement;
  592. break;
  593. }
  594. return garbage;
  595. }
  596. void ppu_writeReg(uint8_t id, uint8_t val)
  597. {
  598. id &= 0x07;
  599. PPU_RegValues[id] = val;
  600. switch(id)
  601. {
  602. default:
  603. break;
  604. case 0x00: /* PPU Control Register #1 */
  605. /*
  606. +===============+===============================================+
  607. |2000 | 1 0 4 |
  608. +---------------+-----------------------------------------------+
  609. | |+===++=++=++=====++=====++===++=++========++==+|
  610. |PPU registers || FV||V||H|| VT|| HT|| FH||S|| PAR||AR||
  611. |PPU counters |+---++-++-++-----++-----++===++=++========++==+|
  612. | |+===++=++=++=====++=====+ |
  613. +---------------+-----------------------------------------------+
  614. */
  615. /* Set PPU internal registers */
  616. PPU_Reg_V = ( val & 0x02 )?1:0;
  617. PPU_Reg_H = ( val & 0x01 )?1:0;
  618. PPU_Reg_S = ( val & 0x10 )?0x1000:0x0000;
  619. /* Set Other parameters */
  620. ppu_addrIncrement = ( val & 0x04 )?0x20:0x01;
  621. ppu_spritePatternTable = ( val & 0x08 )?0x1000:0;
  622. ppu_spriteSize = ( val & 0x20 )?16:8;
  623. ppu_execNMIonVBlank = ( val & 0x80 )?1:0;
  624. break;
  625. case 0x01: /* PPU Control Register #2 */
  626. ppu_spriteVisibility = ( val & 0x10 )?1:0;
  627. ppu_backgroundVisibility = ( val & 0x08 )?1:0;
  628. ppu_spriteClipping = ( val & 0x04 )?0:1;
  629. ppu_backgroundClipping = ( val & 0x02 )?0:1;
  630. ppu_displayType = ( val & 0x01 )?1:0;
  631. break;
  632. case 0x03: /* SPR-RAM Address Register */
  633. ppu_mem_sptrTablePtr = val;
  634. break;
  635. case 0x04: /* SPR-RAM I/O */
  636. ppu_mem_spritesTable[ppu_mem_sptrTablePtr++] = val;
  637. break;
  638. case 0x05: /* 2005 VRAM Register */
  639. /*
  640. +===============+===============================================+
  641. |2005/1 | 76543 210 |
  642. |2005/2 | 210 76543 |
  643. +---------------+-----------------------------------------------+
  644. | |+===++=++=++=====++=====++===++=++========++==+|
  645. |PPU registers || FV||V||H|| VT|| HT|| FH||S|| PAR||AR||
  646. |PPU counters |+---++-++-++-----++-----++===++=++========++==+|
  647. | |+===++=++=++=====++=====+ |
  648. +---------------+-----------------------------------------------+
  649. */
  650. if ( ppu_VramAccessFlipFlop == 0 )
  651. {
  652. ppu_VramAccessFlipFlop = ~0;
  653. PPU_Reg_FH = val & 0x07;
  654. PPU_Reg_HT = ( val & 0xF8 ) >> 3;
  655. }
  656. else
  657. {
  658. ppu_VramAccessFlipFlop = 0;
  659. PPU_Reg_FV = val & 0x07;
  660. PPU_Reg_VT = ( val & 0xF8 ) >> 3;
  661. }
  662. break;
  663. case 0x06: /* 2006 VRAM Register */
  664. /*
  665. +===============+===============================================+
  666. |2006/1 | -54 3 2 10 |
  667. |2006/2 | 765 43210 |
  668. +---------------+-----------------------------------------------+
  669. | |+===++=++=++=====++=====++===++=++========++==+|
  670. |PPU registers || FV||V||H|| VT|| HT|| FH||S|| PAR||AR||
  671. |PPU counters |+---++-++-++-----++-----++===++=++========++==+|
  672. | |+===++=++=++=====++=====+ |
  673. +---------------+-----------------------------------------------+
  674. */
  675. if ( ppu_VramAccessFlipFlop == 0 )
  676. {
  677. ppu_VramAccessFlipFlop = ~0;
  678. PPU_Reg_FV = ( val >> 4 ) & 0x03;
  679. PPU_Reg_V = ( val >> 3 ) & 0x01;
  680. PPU_Reg_H = ( val >> 2 ) & 0x01;
  681. PPU_Reg_VT = ( PPU_Reg_VT & 0x07 ) | ( ( val & 0x03 ) << 3 );
  682. }
  683. else
  684. {
  685. ppu_VramAccessFlipFlop = 0;
  686. PPU_Reg_VT = ( PPU_Reg_VT & 0x18 ) | ( ( val >> 5 ) & 0x07 );
  687. PPU_Reg_HT = val & 0x1F;
  688. ppu_updateCounters();
  689. }
  690. break;
  691. case 0x07: /* VRAM I/O */
  692. /*
  693. +---------------+-----------------------------------------------+
  694. | |+===++=++=++=====++=====++===++=++========++==+|
  695. |PPU registers || FV||V||H|| VT|| HT|| FH||S|| PAR||AR||
  696. |PPU counters |+---++-++-++-----++-----++===++=++========++==+|
  697. | |+===++=++=++=====++=====+ |
  698. +---------------+-----------------------------------------------+
  699. |2007 access | DC B A 98765 43210 |
  700. +===============+===============================================+
  701. */
  702. ppu_writeMemory(( PPU_Reg_Counter >> 8 ) & 0x3F, PPU_Reg_Counter & 0xFF, val);
  703. PPU_Reg_Counter += ppu_addrIncrement;
  704. break;
  705. }
  706. }
  707. void ppu_fillSprRamDMA(uint8_t value)
  708. {
  709. short i;
  710. uint8_t *ptr = get_page_ptr(value);
  711. for ( i = 0 ; i < 0x100 ; i++ )
  712. {
  713. ppu_mem_spritesTable[( ppu_mem_sptrTablePtr + i ) & 0xFF] = *( ptr + i );
  714. }
  715. }