ppu.c 26 KB

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  1. /*
  2. * PPU emulation - The peTI-NESulator Project
  3. * ppu.c
  4. *
  5. * Define and emulate the PPU (Picture Processing Unit) of the real NES
  6. *
  7. * Created by Manoël Trapier.
  8. * Copyright (c) 2002-2019 986-Studio.
  9. *
  10. */
  11. #include <stdio.h>
  12. #include <stdlib.h>
  13. #include <stdint.h>
  14. #include <os_dependent.h>
  15. #define __TINES_PPU_INTERNAL__
  16. #include <ppu/ppu.h>
  17. #include <ppu/ppu.memory.h>
  18. #include <ppu/ppu.debug.h>
  19. #include <memory/manager.h>
  20. #include <os_dependent.h>
  21. #define __TINES_PLUGINS__
  22. #include <plugins/manager.h>
  23. extern int VBLANK_TIME;
  24. extern volatile int frame;
  25. extern volatile uint32_t IPS, FPS;
  26. extern uint32_t ColorPalette[9 * 63];
  27. extern short IRQScanHit;
  28. extern short SZHit;
  29. typedef struct spriteData
  30. {
  31. uint8_t palette;
  32. uint8_t flip_h;
  33. uint8_t flip_v;
  34. uint8_t priority;
  35. uint8_t tile;
  36. uint8_t bank;
  37. uint8_t y;
  38. uint8_t x;
  39. uint8_t rel_y;
  40. uint8_t inUse;
  41. } spriteData;
  42. /* PPU registers */
  43. /* FV: Fine Vertical Scroll latch/counter */
  44. uint8_t PPU_Reg_FV;
  45. /* HV: Fine Horizontal Scroll latch/counter */
  46. uint8_t PPU_Reg_FH;
  47. /* VT: Vertical Tile indev latch/counter */
  48. uint8_t PPU_Reg_VT;
  49. /* HT: Horizontal Tile indev latch/counter */
  50. uint8_t PPU_Reg_HT;
  51. /* V: Vertical Name Table Selection latch/counter */
  52. uint8_t PPU_Reg_V;
  53. /* H: Horizontal Name Table Selection latch/counter */
  54. uint8_t PPU_Reg_H;
  55. /* S: Play-field pattern table selection latch */
  56. uint16_t PPU_Reg_S;
  57. /* PAR: Picture Address Register */
  58. uint8_t PPU_Reg_PAR;
  59. /* AR: Tile Attribute (palette select) value latch */
  60. uint8_t PPU_Reg_AR;
  61. uint16_t PPU_Reg_Counter;
  62. /* PPU Memory Areas */
  63. uint8_t *ppu_mem_nameTables;
  64. uint8_t *ppu_mem_patternTables;
  65. uint8_t *ppu_mem_paletteValues;
  66. uint8_t ppu_mem_spritesTable[0x100];
  67. uint8_t ppu_mem_sptrTablePtr;
  68. /* Some other PPU "registers" */
  69. uint8_t ppu_VramAccessFlipFlop;
  70. uint8_t ppu_inVBlankTime;
  71. uint8_t ppu_spriteZeroHit;
  72. uint8_t ppu_scanlineSpriteOverflow;
  73. uint8_t ppu_bgColor;
  74. /* CR #1 variables */
  75. uint16_t ppu_spritePatternTable;
  76. uint8_t ppu_spriteSize;
  77. uint8_t ppu_addrIncrement;
  78. uint8_t ppu_execNMIonVBlank;
  79. /* CR #2 variables */
  80. uint8_t ppu_spriteVisibility;
  81. uint8_t ppu_backgroundVisibility;
  82. uint8_t ppu_spriteClipping;
  83. uint8_t ppu_backgroundClipping;
  84. uint8_t ppu_displayType;
  85. uint8_t ppu_mirrorMode;
  86. uint8_t ppu_singleScreenMode;
  87. uint8_t ppu_screenMode;
  88. #define PPU_MEM_PATTERNTABLES_SIZE 0x2000
  89. #define PPU_MEM_NAMETABLE_SIZE 0x1000
  90. #define PPU_MEM_PALETTEVALUES_SIZE 0x100 /* in fact its 20 but we must allocate a least one page */
  91. #define PPU_SPRITE_FLAGS_VFLIP ( 1 << 7 )
  92. #define PPU_SPRITE_FLAGS_HFLIP ( 1 << 6 )
  93. #define PPU_SPRITE_FLAGS_BGPRIO ( 1 << 5 )
  94. #define PPU_SPRITE_FLAGS_UPPERCOLOR ( 0x03 )
  95. #define PPU_FLAG_SR_VBLANK ( 1 << 7 )
  96. #define PPU_FLAG_SR_SPRT0 ( 1 << 6 )
  97. #define PPU_FLAG_SR_8SPRT ( 1 << 5 )
  98. #define PPU_FLAG_SR_RDWRALLOW ( 1 << 4 )
  99. #define PPU_CR1_SPRTSIZE ( 1 << 5 )
  100. #define PPU_CR1_EXECNMI ( 1 << 7 )
  101. #define PPU_CR2_BGVISIBILITY ( 1 << 3 )
  102. #define PPU_CR2_SPRTVISIBILITY ( 1 << 4 )
  103. int ppu_init()
  104. {
  105. int i;
  106. /*uint8_t defaultColors[] = { 0x09,0x01,0x00,0x01,0x00,0x02,0x02,0x0D,0x08,0x10,0x08,0x24,0x00,0x00,0x04,0x2C,
  107. 0x09,0x01,0x34,0x03,0x00,0x04,0x00,0x14,0x08,0x3A,0x00,0x02,0x00,0x20,0x2C,0x08 };*/
  108. if ( ppu_initMemory() )
  109. return -1;
  110. /* Set ppu memory parameters */
  111. /* First: Allocate each memory zone */
  112. ppu_mem_patternTables = (uint8_t *) malloc(PPU_MEM_PATTERNTABLES_SIZE);
  113. if ( !ppu_mem_patternTables )
  114. return -1;
  115. ppu_mem_nameTables = (uint8_t *) malloc(PPU_MEM_NAMETABLE_SIZE);
  116. if ( !ppu_mem_nameTables )
  117. return -1;
  118. ppu_mem_paletteValues = (uint8_t *) malloc(PPU_MEM_PALETTEVALUES_SIZE);
  119. if ( !ppu_mem_paletteValues )
  120. return -1;
  121. console_printf(Console_Default, "ppu_mem_nameTables :%p\n"
  122. "ppu_mem_patternTables:%p\n"
  123. "ppu_mem_paletteValues:%p\n",
  124. ppu_mem_nameTables,
  125. ppu_mem_patternTables,
  126. ppu_mem_paletteValues);
  127. /* Second: make the ppu memory manager point on the memory zones */
  128. ppu_setPagePtr8k(0x00, ppu_mem_patternTables);
  129. ppu_setPagePtr4k(0x20, ppu_mem_nameTables);
  130. ppu_setPagePtr(0x3F, ppu_mem_paletteValues);
  131. for ( i = 0x00 ; i < 0x0F ; i++ )
  132. ppu_setPageGhost(0x30 + i, true, 0x20 + i);
  133. /* Third: set registers to defaults */
  134. /* Now test the memory ! */
  135. /* Fille PPU memory with garbage */
  136. for ( i = 0x0000 ; i < 0x2000 ; i++ )
  137. ppu_mem_patternTables[i] = rand() % 0xFF;
  138. for ( i = 0x0000 ; i < 0x1000 ; i++ )
  139. ppu_mem_nameTables[i] = rand() % 0xFF;
  140. for ( i = 0x0000 ; i < 0x001F ; i++ )
  141. ppu_mem_paletteValues[i] = rand() % 0xFF;
  142. //memcpy(ppu_mem_paletteValues, defaultColors, 32);
  143. /* Set some other variables */
  144. ppu_VramAccessFlipFlop = 0;
  145. ppu_addrIncrement = 1;
  146. ppu_spritePatternTable = 0;
  147. ppu_spriteSize = 8;
  148. ppu_execNMIonVBlank = 0;
  149. ppu_spriteVisibility = 0;
  150. ppu_backgroundVisibility = 0;
  151. ppu_spriteClipping = 0;
  152. ppu_backgroundClipping = 0;
  153. ppu_displayType = 0;
  154. ppu_inVBlankTime = 0;
  155. ppu_bgColor = 0;
  156. /* Set PPU registers on CPU side */
  157. set_page_rd_hook(0x20, ppu_readReg);
  158. set_page_wr_hook(0x20, ppu_writeReg);
  159. set_page_readable(0x20, true);
  160. set_page_writeable(0x20, true);
  161. /* Set PPU Ghost Registers */
  162. for ( i = 0x21 ; i < 0x40 ; i++ )
  163. set_page_ghost(i, true, 0x20);
  164. /* allocate the PPU Video memory */
  165. graphics_init();
  166. return 0;
  167. }
  168. void ppu_setMirroring(uint8_t direction)
  169. {
  170. if ( ppu_screenMode != PPU_SCMODE_NORMAL )
  171. return;
  172. if ( ppu_mirrorMode == direction )
  173. return; /* Same value, no need to change! */
  174. switch(direction)
  175. {
  176. default:
  177. direction = PPU_MIRROR_HORIZTAL;
  178. ppu_mirrorMode = direction;
  179. case PPU_MIRROR_HORIZTAL: /* Horizontal */
  180. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x000);
  181. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x000);
  182. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x400);
  183. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0x400);
  184. break;
  185. case PPU_MIRROR_VERTICAL: /* Vertical */
  186. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x000);
  187. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x400);
  188. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x000);
  189. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0x400);
  190. break;
  191. }
  192. ppu_mirrorMode = direction;
  193. }
  194. void ppu_setSingleScreen(uint8_t screen)
  195. {
  196. if ( ppu_screenMode != PPU_SCMODE_SINGLE )
  197. return;
  198. if ( ppu_singleScreenMode == screen )
  199. return; /* Same value, no need to change! */
  200. switch(screen)
  201. {
  202. default:
  203. screen = PPU_SCREEN_000;
  204. ppu_singleScreenMode = screen;
  205. case PPU_SCREEN_000: /* 0x2000 */
  206. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x000);
  207. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x000);
  208. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x000);
  209. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0x000);
  210. break;
  211. case PPU_SCREEN_400: /* 0x2400 */
  212. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x400);
  213. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x400);
  214. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x400);
  215. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0x400);
  216. break;
  217. case PPU_SCREEN_800: /* 0x2800 */
  218. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x800);
  219. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x800);
  220. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x800);
  221. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0x800);
  222. break;
  223. case PPU_SCREEN_C00: /* 0x2C00 */
  224. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0xC00);
  225. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0xC00);
  226. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0xC00);
  227. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0xC00);
  228. break;
  229. }
  230. ppu_singleScreenMode = screen;
  231. }
  232. /* Let set display to
  233. Single screen (1 NT with mirroring)
  234. Normal screen (2 NT with mirroring)
  235. Four screen (4 NT without mirroring) */
  236. void ppu_setScreenMode(uint8_t mode)
  237. {
  238. if ( ppu_screenMode == mode )
  239. return; /* Same value, no need to change! */
  240. ppu_screenMode = mode;
  241. switch(mode)
  242. {
  243. case PPU_SCMODE_SINGLE: /* Single screen (1 NT with mirroring) */
  244. ppu_setSingleScreen(~ppu_singleScreenMode);
  245. break;
  246. default:
  247. mode = PPU_SCMODE_NORMAL;
  248. ppu_screenMode = mode;
  249. case PPU_SCMODE_NORMAL: /* Normal screen (2 NT with mirroring) */
  250. ppu_setMirroring(~ppu_mirrorMode);
  251. break;
  252. case PPU_SCMODE_FOURSC: /* Four screen (4 NT withou mirroring) */
  253. ppu_setPagePtr1k(0x20, ppu_mem_nameTables + 0x000);
  254. ppu_setPagePtr1k(0x24, ppu_mem_nameTables + 0x400);
  255. ppu_setPagePtr1k(0x28, ppu_mem_nameTables + 0x800);
  256. ppu_setPagePtr1k(0x2C, ppu_mem_nameTables + 0xC00);
  257. break;
  258. }
  259. }
  260. /* update whole counters */
  261. void ppu_updateCounters()
  262. {
  263. /*
  264. +---------------+-----------------------------------------------+
  265. | |+===++=++=++=====++=====++===++=++========++==+|
  266. |PPU registers || FV||V||H|| VT|| HT|| FH||S|| PAR||AR||
  267. |PPU counters |+---++-++-++-----++-----++===++=++========++==+|
  268. | |+===++=++=++=====++=====+ |
  269. +---------------+-----------------------------------------------+
  270. |2007 access | DC B A 98765 43210 |
  271. +===============+===============================================+
  272. 8421 8421 8421 8421
  273. -------------------
  274. 1111 1100 0000 0000
  275. 5432 1098 7654 3210
  276. _AAA BCDD DDDE EEEE
  277. */
  278. PPU_Reg_Counter = ( PPU_Reg_FV & 0x07 ) << 12;
  279. PPU_Reg_Counter |= PPU_Reg_V << 11;
  280. PPU_Reg_Counter |= PPU_Reg_H << 10;
  281. PPU_Reg_Counter |= PPU_Reg_VT << 5;
  282. PPU_Reg_Counter |= PPU_Reg_HT;
  283. }
  284. int ppu_hblank(uint16_t scanline)
  285. {
  286. /* Sprite to display on current scanline */
  287. spriteData scanSprites[8];
  288. ppu_scanlineSpriteOverflow = 0;
  289. if ( scanline == 0 )
  290. {
  291. if ( ( ppu_spriteVisibility != 0 ) || ( ppu_backgroundVisibility != 0 ) )
  292. ppu_updateCounters();
  293. }
  294. if ( scanline < 240 )
  295. {
  296. int i;
  297. uint8_t spriteCount = 0;
  298. /* Search for sprites on current scanline */
  299. for (i = 0 ; i < 8 ; i++)
  300. {
  301. scanSprites[i].inUse = 0;
  302. }
  303. for (i = 0 ; i < 64 && spriteCount < 8; i++)
  304. {
  305. uint8_t spriteY = ppu_mem_spritesTable[i*4] + 1;
  306. if ((scanline >= spriteY) && (scanline < (spriteY + ppu_spriteSize)))
  307. {
  308. /* This sprite is on the scanline */
  309. scanSprites[spriteCount].inUse = 1;
  310. scanSprites[spriteCount].x = ppu_mem_spritesTable[i*4 + 3];
  311. scanSprites[spriteCount].y = spriteY;
  312. scanSprites[spriteCount].rel_y = scanline - scanSprites[spriteCount].y;
  313. scanSprites[spriteCount].tile = ppu_mem_spritesTable[i * 4 + 1];
  314. scanSprites[spriteCount].bank = ppu_mem_spritesTable[i * 4 + 1] & 0x01;
  315. scanSprites[spriteCount].flip_h = ( ppu_mem_spritesTable[i * 4 + 2] & PPU_SPRITE_FLAGS_HFLIP )?1:0;
  316. scanSprites[spriteCount].flip_v = ( ppu_mem_spritesTable[i * 4 + 2] & PPU_SPRITE_FLAGS_VFLIP )?1:0;
  317. scanSprites[spriteCount].palette = ( ppu_mem_spritesTable[i * 4 + 2] & PPU_SPRITE_FLAGS_UPPERCOLOR ) & 0x0F;
  318. scanSprites[spriteCount].priority = ( ppu_mem_spritesTable[i * 4 + 2] & PPU_SPRITE_FLAGS_BGPRIO )?1:0;
  319. spriteCount++;
  320. }
  321. }
  322. ppu_bgColor = ppu_readMemory(0x3F, 00);
  323. /* For each PPU pixel of this scanline */
  324. for ( i = 0 ; i < 256 ; i++ )
  325. {
  326. uint16_t addr;
  327. uint8_t value;
  328. uint8_t pixelColor = 0;
  329. uint8_t BgColor = 0;
  330. /* Set the current pixel color to the bg color */
  331. pixelColor = ppu_bgColor;
  332. BgColor = 0;
  333. /* Compute current pixel bg color if bg is visible */
  334. if (( ppu_backgroundVisibility == 1 ) && (!getKeyStatus('B')))
  335. {
  336. if ( ((i < 8) && (!ppu_backgroundClipping)) || (i >= 8))
  337. {
  338. addr = ( PPU_Reg_Counter & 0x0C00 );
  339. addr = addr | 0x03C0;
  340. addr |= ( PPU_Reg_Counter >> 4 ) & 0x0038;
  341. addr |= ( PPU_Reg_Counter >> 2 ) & 0x0007;
  342. PPU_Reg_AR = ppu_readMemory(0x20 | ( ( addr >> 8 ) & 0x0F ), addr & 0xFF);
  343. PPU_Reg_AR = PPU_Reg_AR >> ( ( ( PPU_Reg_Counter >> 4 ) & 0x04 ) | ( ( PPU_Reg_Counter ) & 0x02 ) );
  344. PPU_Reg_AR = ( PPU_Reg_AR << 2 ) & 0x0C;
  345. PPU_Reg_PAR = ppu_readMemory(0x20 | ( ( PPU_Reg_Counter >> 8 ) & 0x0F ), PPU_Reg_Counter & 0xFF);
  346. addr = PPU_Reg_S;
  347. addr |= ( ( PPU_Reg_PAR & 0xFF ) << 4 );
  348. addr |= ( ( PPU_Reg_Counter >> 12 ) & 0x07 );
  349. value = ppu_readMemory(( addr >> 8 ), addr);
  350. BgColor = ( value & ( 1 << ( 7 - ( i + PPU_Reg_FH ) % 8 ) ) )?0x01:0;
  351. value = ppu_readMemory(( addr >> 8 ), addr | 0x08);
  352. BgColor |= ( value & ( 1 << ( 7 - ( i + PPU_Reg_FH ) % 8 ) ) )?0x02:0;
  353. if ( BgColor > 0x00 )
  354. {
  355. BgColor |= PPU_Reg_AR;
  356. BgColor &= 0x0F;
  357. pixelColor = ppu_readMemory(0x3F, BgColor);
  358. }
  359. if ( ( ( i + PPU_Reg_FH ) % 8 ) == 7 )
  360. {
  361. uint16_t tmp_HHT = 0;
  362. tmp_HHT = ( ( PPU_Reg_Counter >> 5 ) & 0x0020 ) |
  363. ( PPU_Reg_Counter & 0x001F );
  364. tmp_HHT = ( tmp_HHT + 1 ) & 0x003F;
  365. /* Reassemble with HT & H */
  366. PPU_Reg_Counter = ( PPU_Reg_Counter & 0xFBE0 ) |
  367. ( ( tmp_HHT & 0x0020 ) << 5 ) |
  368. ( tmp_HHT & 0x001F );
  369. }
  370. }
  371. #if 0
  372. // ISPAL
  373. else
  374. {
  375. pixelColor = 0x1D;
  376. }
  377. #endif
  378. }
  379. /* Now calculate if there is a sprite here and sprite visibility is on */
  380. if ( ppu_spriteVisibility == 1 )
  381. {
  382. if (((!ppu_spriteClipping) && (i < 8)) || (i >= 8))
  383. {
  384. uint32_t j;
  385. for( j = 0 ; j < 8 ; j++)
  386. {
  387. spriteData *sprite = &scanSprites[j];
  388. int8_t spriteRelX;
  389. if ( sprite->inUse == 0 )
  390. break;
  391. spriteRelX = i - sprite->x;
  392. if ( ( spriteRelX >= 0 ) && ( spriteRelX < 8 ) )
  393. {
  394. uint8_t SpriteColor = 0;
  395. /* Get sprite tile address */
  396. if ( ppu_spriteSize == 8 )
  397. {
  398. addr = ( sprite->tile << 4 ) + ppu_spritePatternTable;
  399. }
  400. else
  401. {
  402. if ( sprite->rel_y < 8 )
  403. {
  404. addr = ( ( ( sprite->tile & 0xFE ) + ( sprite->flip_v?1:0 ) ) << 4 ) +
  405. ( ( sprite->bank )?0x1000:0x0000 );
  406. }
  407. else
  408. {
  409. addr = ( ( ( sprite->tile & 0xFE ) + ( sprite->flip_v?0:1 ) ) << 4 ) +
  410. ( ( sprite->bank )?0x1000:0x0000 );
  411. }
  412. }
  413. if ( sprite->flip_v )
  414. {
  415. addr += 7;
  416. addr -= sprite->rel_y % 8;
  417. }
  418. else
  419. {
  420. addr += sprite->rel_y % 8;
  421. }
  422. if ( sprite->flip_h )
  423. {
  424. value = ppu_readMemory(( addr >> 8 ), addr);
  425. SpriteColor = ( value & ( 1 << ( spriteRelX ) ) )?0x01:0;
  426. value = ppu_readMemory(( addr >> 8 ), addr | 0x08);
  427. SpriteColor |= ( value & ( 1 << ( spriteRelX ) ) )?0x02:0;
  428. }
  429. else
  430. {
  431. value = ppu_readMemory(( addr >> 8 ), addr);
  432. SpriteColor = ( value & ( 1 << ( 7 - ( spriteRelX ) ) ) )?0x01:0;
  433. value = ppu_readMemory(( addr >> 8 ), addr | 0x08);
  434. SpriteColor |= ( value & ( 1 << ( 7 - ( spriteRelX ) ) ) )?0x02:0;
  435. }
  436. /* If we get a color different from 0, the pixel is not transparent */
  437. if ( SpriteColor > 0 )
  438. {
  439. /* Add second part of the colour */
  440. SpriteColor |= ( ( sprite->palette ) << 2 );
  441. SpriteColor &= 0x0F;
  442. if ( j == 0 )
  443. {
  444. /* Sprite 0 */
  445. if ( ( BgColor != 0 ) && ( !ppu_spriteZeroHit ) )
  446. {
  447. ppu_spriteZeroHit = ( ppu_backgroundVisibility )?1:0;
  448. if ( ppu_spriteZeroHit )
  449. SZHit = scanline;
  450. }
  451. }
  452. if ( sprite->priority )
  453. {
  454. if ( SpriteColor > 0x00 )
  455. {
  456. if ( BgColor == 0 )
  457. {
  458. pixelColor = ppu_readMemory(0x3F, ( 0x10 + SpriteColor ));
  459. }
  460. break;
  461. }
  462. }
  463. else
  464. {
  465. if ( SpriteColor != 0x00 )
  466. {
  467. pixelColor = ppu_readMemory(0x3F, ( 0x10 + SpriteColor ));
  468. break;
  469. }
  470. }
  471. }
  472. }
  473. }
  474. }
  475. }
  476. /* Set to monochrome if needed */
  477. if ( ppu_displayType )
  478. pixelColor &= 0x30;
  479. /* draw the pixel */
  480. graphics_drawpixel(i, scanline, pixelColor);
  481. }
  482. if (spriteCount > 8)
  483. {
  484. ppu_scanlineSpriteOverflow = 1;
  485. }
  486. if ( ppu_backgroundVisibility == 1 )
  487. {
  488. uint16_t tmp_VVTFV = 0;
  489. tmp_VVTFV = ( ( PPU_Reg_Counter >> 3 ) & 0x0100 ) | /* V */
  490. ( ( PPU_Reg_Counter >> 2 ) & 0x00F8 ) | /* VT */
  491. ( ( PPU_Reg_Counter >> 12 ) & 0x0007 ); /* FV */
  492. tmp_VVTFV++;
  493. if ( ( tmp_VVTFV & 0x0F8 ) == 0xF0 )
  494. {
  495. tmp_VVTFV &= ~0x0F8;
  496. tmp_VVTFV ^= 0x100;
  497. }
  498. PPU_Reg_Counter = ( PPU_Reg_Counter & 0x041F ) |
  499. ( ( tmp_VVTFV & 0x0100 ) << 3 ) | /* V */
  500. ( ( tmp_VVTFV & 0x00F8 ) << 2 ) | /* VT */
  501. ( ( tmp_VVTFV & 0x0007 ) << 12 ); /* FV */
  502. /* Update H & HT */
  503. PPU_Reg_Counter = ( PPU_Reg_Counter & ~0x041F ) |
  504. ( PPU_Reg_H << 10 ) |
  505. PPU_Reg_HT;
  506. }
  507. }
  508. /* Increment only V, VT & FV*/
  509. /*
  510. 8421 8421 8421 8421
  511. -------------------
  512. 1111 1100 0000 0000
  513. 5432 1098 7654 3210
  514. _AAA BCDD DDDE EEEE
  515. xxx x xx xxx : vvtfv = 7BE0
  516. x x xxxx : hht
  517. B DDDD DAAA : vvtfv
  518. CE EEEE : hht
  519. A = FV
  520. B = V
  521. C = H
  522. D = VT
  523. E = HT
  524. */
  525. if ( scanline == 239 )
  526. {
  527. ppu_inVBlankTime = 1;
  528. // textprintf_ex(Buffer, font, 260, 3, 4, 0, "FPS : %ld (CPU@~%2.2fMhz : %d%%)", FPS, (float) (((float) IPS) / 1000000.0), (int) ((((float) IPS) / 1770000.0) * 100.0));
  529. graphics_blit(0, 0, 256, 240);
  530. return ppu_execNMIonVBlank;
  531. }
  532. /* Debug tools */
  533. /*if ( scanline == SZHit )
  534. {
  535. graphics_drawline(0, scanline, 256, scanline, 0x12);
  536. }
  537. if ( scanline == IRQScanHit )
  538. {
  539. graphics_drawline(0, scanline, 256, scanline, 0x13);
  540. }*/
  541. /* */
  542. if ( scanline == ( 239 + VBLANK_TIME ) + 0 )
  543. {
  544. ppu_inVBlankTime = 0;
  545. ppu_spriteZeroHit = 0;
  546. ppu_scanlineSpriteOverflow = 0;
  547. }
  548. return 0;
  549. }
  550. uint8_t PPU_RegValues[8];
  551. uint8_t ppu_readReg(uint8_t id)
  552. {
  553. id &= 0x07;
  554. static uint8_t garbage;
  555. static uint8_t lastValue;
  556. switch(id)
  557. {
  558. default:
  559. garbage = PPU_RegValues[id];
  560. break;
  561. case 0x02: /* PPU Status Register */
  562. /* Reset VRam 2005/2006 flipflop */
  563. ppu_VramAccessFlipFlop = 0;
  564. garbage = 0;
  565. garbage |= ( ppu_inVBlankTime != 0 )?PPU_FLAG_SR_VBLANK:0;
  566. garbage |= ( ppu_spriteZeroHit != 0 )?PPU_FLAG_SR_SPRT0:0;
  567. garbage |= ( ppu_scanlineSpriteOverflow != 0 )?PPU_FLAG_SR_8SPRT:0;
  568. ppu_inVBlankTime = 0;
  569. break;
  570. case 0x04: /* SPR-RAM I/O */
  571. garbage = ppu_mem_spritesTable[ppu_mem_sptrTablePtr];
  572. break;
  573. case 0x07: /* VRAM I/O */
  574. if ( PPU_Reg_Counter < 0x3F00 )
  575. {
  576. garbage = lastValue;
  577. lastValue = ppu_readMemory(( PPU_Reg_Counter >> 8 ) & 0x3F,
  578. PPU_Reg_Counter & 0xFF);
  579. }
  580. else
  581. {
  582. lastValue = ppu_readMemory(0x2F,
  583. PPU_Reg_Counter & 0xFF);
  584. garbage = ppu_readMemory(0x3F,
  585. PPU_Reg_Counter & 0xFF);
  586. }
  587. PPU_Reg_Counter += ppu_addrIncrement;
  588. break;
  589. }
  590. return garbage;
  591. }
  592. void ppu_writeReg(uint8_t id, uint8_t val)
  593. {
  594. id &= 0x07;
  595. PPU_RegValues[id] = val;
  596. switch(id)
  597. {
  598. default:
  599. break;
  600. case 0x00: /* PPU Control Register #1 */
  601. /*
  602. +===============+===============================================+
  603. |2000 | 1 0 4 |
  604. +---------------+-----------------------------------------------+
  605. | |+===++=++=++=====++=====++===++=++========++==+|
  606. |PPU registers || FV||V||H|| VT|| HT|| FH||S|| PAR||AR||
  607. |PPU counters |+---++-++-++-----++-----++===++=++========++==+|
  608. | |+===++=++=++=====++=====+ |
  609. +---------------+-----------------------------------------------+
  610. */
  611. /* Set PPU internal registers */
  612. PPU_Reg_V = ( val & 0x02 )?1:0;
  613. PPU_Reg_H = ( val & 0x01 )?1:0;
  614. PPU_Reg_S = ( val & 0x10 )?0x1000:0x0000;
  615. /* Set Other parameters */
  616. ppu_addrIncrement = ( val & 0x04 )?0x20:0x01;
  617. ppu_spritePatternTable = ( val & 0x08 )?0x1000:0;
  618. ppu_spriteSize = ( val & 0x20 )?16:8;
  619. ppu_execNMIonVBlank = ( val & 0x80 )?1:0;
  620. break;
  621. case 0x01: /* PPU Control Register #2 */
  622. ppu_spriteVisibility = ( val & 0x10 )?1:0;
  623. ppu_backgroundVisibility = ( val & 0x08 )?1:0;
  624. ppu_spriteClipping = ( val & 0x04 )?0:1;
  625. ppu_backgroundClipping = ( val & 0x02 )?0:1;
  626. ppu_displayType = ( val & 0x01 )?1:0;
  627. break;
  628. case 0x03: /* SPR-RAM Address Register */
  629. ppu_mem_sptrTablePtr = val;
  630. break;
  631. case 0x04: /* SPR-RAM I/O */
  632. ppu_mem_spritesTable[ppu_mem_sptrTablePtr++] = val;
  633. break;
  634. case 0x05: /* 2005 VRAM Register */
  635. /*
  636. +===============+===============================================+
  637. |2005/1 | 76543 210 |
  638. |2005/2 | 210 76543 |
  639. +---------------+-----------------------------------------------+
  640. | |+===++=++=++=====++=====++===++=++========++==+|
  641. |PPU registers || FV||V||H|| VT|| HT|| FH||S|| PAR||AR||
  642. |PPU counters |+---++-++-++-----++-----++===++=++========++==+|
  643. | |+===++=++=++=====++=====+ |
  644. +---------------+-----------------------------------------------+
  645. */
  646. if ( ppu_VramAccessFlipFlop == 0 )
  647. {
  648. ppu_VramAccessFlipFlop = ~0;
  649. PPU_Reg_FH = val & 0x07;
  650. PPU_Reg_HT = ( val & 0xF8 ) >> 3;
  651. }
  652. else
  653. {
  654. ppu_VramAccessFlipFlop = 0;
  655. PPU_Reg_FV = val & 0x07;
  656. PPU_Reg_VT = ( val & 0xF8 ) >> 3;
  657. }
  658. break;
  659. case 0x06: /* 2006 VRAM Register */
  660. /*
  661. +===============+===============================================+
  662. |2006/1 | -54 3 2 10 |
  663. |2006/2 | 765 43210 |
  664. +---------------+-----------------------------------------------+
  665. | |+===++=++=++=====++=====++===++=++========++==+|
  666. |PPU registers || FV||V||H|| VT|| HT|| FH||S|| PAR||AR||
  667. |PPU counters |+---++-++-++-----++-----++===++=++========++==+|
  668. | |+===++=++=++=====++=====+ |
  669. +---------------+-----------------------------------------------+
  670. */
  671. if ( ppu_VramAccessFlipFlop == 0 )
  672. {
  673. ppu_VramAccessFlipFlop = ~0;
  674. PPU_Reg_FV = ( val >> 4 ) & 0x03;
  675. PPU_Reg_V = ( val >> 3 ) & 0x01;
  676. PPU_Reg_H = ( val >> 2 ) & 0x01;
  677. PPU_Reg_VT = ( PPU_Reg_VT & 0x07 ) | ( ( val & 0x03 ) << 3 );
  678. }
  679. else
  680. {
  681. ppu_VramAccessFlipFlop = 0;
  682. PPU_Reg_VT = ( PPU_Reg_VT & 0x18 ) | ( ( val >> 5 ) & 0x07 );
  683. PPU_Reg_HT = val & 0x1F;
  684. ppu_updateCounters();
  685. }
  686. break;
  687. case 0x07: /* VRAM I/O */
  688. /*
  689. +---------------+-----------------------------------------------+
  690. | |+===++=++=++=====++=====++===++=++========++==+|
  691. |PPU registers || FV||V||H|| VT|| HT|| FH||S|| PAR||AR||
  692. |PPU counters |+---++-++-++-----++-----++===++=++========++==+|
  693. | |+===++=++=++=====++=====+ |
  694. +---------------+-----------------------------------------------+
  695. |2007 access | DC B A 98765 43210 |
  696. +===============+===============================================+
  697. */
  698. ppu_writeMemory(( PPU_Reg_Counter >> 8 ) & 0x3F, PPU_Reg_Counter & 0xFF, val);
  699. PPU_Reg_Counter += ppu_addrIncrement;
  700. break;
  701. }
  702. }
  703. void ppu_fillSprRamDMA(uint8_t value)
  704. {
  705. short i;
  706. uint8_t *ptr = get_page_ptr(value);
  707. for ( i = 0 ; i < 0x100 ; i++ )
  708. {
  709. ppu_mem_spritesTable[( ppu_mem_sptrTablePtr + i ) & 0xFF] = *( ptr + i );
  710. }
  711. }