top.vhd 1.4 KB

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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5. ---- Uncomment the following library declaration if instantiating
  6. ---- any Xilinx primitives in this code.
  7. --library UNISIM;
  8. --use UNISIM.VComponents.all;
  9. entity top is
  10. port(
  11. CLK14M : in std_logic;
  12. CREF : in std_logic;
  13. nPRAS : in std_logic;
  14. nLDPS : in std_logic;
  15. VIDD7 : in std_logic;
  16. nSEROUT : in std_logic;
  17. nWNDW : in std_logic;
  18. nSYNC : in std_logic;
  19. TEXT : in std_logic;
  20. SEGB : in std_logic;
  21. GR : in std_logic;
  22. RED : out std_logic_vector(1 downto 0);
  23. GREEN : out std_logic_vector(1 downto 0);
  24. BLUE : out std_logic_vector(1 downto 0);
  25. nSYNCOUT : out std_logic;
  26. VGA_HS : out std_logic;
  27. VGA_VS : out std_logic;
  28. VGA_R : out std_logic;
  29. VGA_G : out std_logic;
  30. VGA_B : out std_logic
  31. );
  32. end top;
  33. architecture rtl of top is
  34. begin
  35. RGB : entity work.rgb_encoder
  36. port map(
  37. CLK14M => CLK14M,
  38. CREF => CREF,
  39. nSEROUT => nSEROUT,
  40. nSYNC => nSYNC,
  41. TEXT => TEXT,
  42. GR => GR,
  43. RED => RED,
  44. GREEN => GREEN,
  45. BLUE => BLUE,
  46. nSYNCOUT => nSYNCOUT
  47. );
  48. VGA : entity work.vga_controller
  49. port map(
  50. CLK_14M => CLK14M,
  51. nVIDEO => nSEROUT,
  52. COLOR_LINE => GR,
  53. CBL => nWNDW,
  54. nLDPS => nLDPS,
  55. VGA_HS => VGA_HS,
  56. VGA_VS => VGA_VS,
  57. VGA_R => VGA_R,
  58. VGA_G => VGA_G,
  59. VGA_B => VGA_B
  60. );
  61. end rtl;