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@@ -1,3 +1,5 @@
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+`default_nettype none
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+
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module top(
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input clka,
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output [2:0] vga_red,
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@@ -36,13 +38,39 @@ module top(
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.RST(0)
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);
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- textmode tm(.clk(clk),
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+ wire we;
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+ wire [7:0] wd;
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+ wire textMISO;
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+
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+ spi _s (.clk(clk),
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+ .SCK(SCK),
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+ .MOSI(MOSI),
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+ .MISO(textMISO),
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+ .SSEL(SSEL),
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+ .we(we),
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+ .byte_recv(wd),
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+ .byte_xmit(8'ha0));
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+
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+ reg[14:0] a;
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+ wire wclk = SCK;
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+
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+ textmode tm(.wclk(wclk),
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+ .write(we),
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+ .addr(a),
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+ .d(wd),
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+ .clk(clk),
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.vga_red(vga_red),
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.vga_green(vga_green),
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.vga_blue(vga_blue),
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.vga_hsync_n(vga_hsync_n),
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.vga_vsync_n(vga_vsync_n));
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+ always @(posedge SSEL or posedge SCK)
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+ if (SSEL == 1)
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+ a <= 5;
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+ else if (we)
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+ a <= a + 1;
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+
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assign AUDIOL = 0;
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assign AUDIOR = 0;
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@@ -50,15 +78,75 @@ module top(
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assign flashSCK = SCK;
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assign flashSSEL = AUX;
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- assign MISO = (SSEL == 0) ? 1'b0 : flashMISO;
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+ assign MISO = (SSEL == 0) ? textMISO : flashMISO;
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+
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+endmodule
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+
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+module spi(
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+ input clk,
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+ input SCK, input MOSI, output MISO, input SSEL,
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+
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+ output we,
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+ output [7:0] byte_recv,
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+ input [7:0] byte_xmit);
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+
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+ reg [2:0] bit;
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+ reg [7:0] recv;
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+ wire [7:0] recvN = {recv[6:0], MOSI};
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+
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+ always @(posedge SSEL or posedge SCK)
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+ if (SSEL == 1)
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+ bit <= 7;
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+ else begin
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+ recv <= recvN;
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+ bit <= bit - 1;
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+ end
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+
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+ assign MISO = byte_xmit[bit[2:0]];
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+ assign byte_recv = recvN;
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+ assign we = !SSEL & (bit == 0);
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+endmodule
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+
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+module ram16k(
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+ input wclk,
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+ input We,
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+ input [13:0] Waddr,
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+ input [7:0] Din,
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+
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+ input rclk,
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+ input [13:0] Raddr,
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+ output [7:0] Dout);
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+
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+ //synthesis attribute ram_style of mem is block
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+ reg [7:0] mem[0:16383]; //pragma attribute mem ram_block TRUE
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+ reg [13:0] raddr_reg;
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+
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+ initial begin
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+ $readmemh("init.hex", mem);
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+ end
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+
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+ always @ (posedge wclk)
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+ if (We)
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+ mem[Waddr] <= Din;
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+
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+ always @ (posedge rclk)
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+ raddr_reg <= Raddr;
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+ // Dout <= mem[raddr_reg]; //registered read
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+
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+ assign Dout = mem[raddr_reg]; //unregistered read
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endmodule
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module textmode(
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+ input wclk,
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+ input write,
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+ input [14:0] addr,
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+ input [7:0] d,
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+
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input clk,
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- output [2:0] vga_red,
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- output [2:0] vga_green,
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- output [2:0] vga_blue,
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+ output reg [2:0] vga_red,
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+ output reg [2:0] vga_green,
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+ output reg [2:0] vga_blue,
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output reg vga_hsync_n,
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output reg vga_vsync_n);
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@@ -91,32 +179,41 @@ module textmode(
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wire visible = (hcounter < 1024) & (vcounter < 768);
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+ wire [7:0] cc;
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+ ram16k r(.wclk(wclk), .rclk(clk), .We(write), .Waddr(addr[13:0]), .Raddr(hcounterN[10:3]), .Din(d), .Dout(cc));
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+ // assign cc = hcounterN[10:3] + vcounterN[9:4];
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wire pix;
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- fontrom fr(.ch(hcounterN[10:3] + vcounterN[9:4]), .row(vcounterN[3:0]), .col(hcounterN[2:0]), .pix(pix));
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+ fontrom fr(.clk(clk), .ch(cc), .row(vcounterN[3:0]), .col(hcounterN[2:0] - 1), .pix(pix));
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always @(posedge clk) begin
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hcounter <= hcounterN;
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vcounter <= vcounterN;
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vga_hsync_n <= !((1048 <= hcounter) & (hcounter < 1184));
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vga_vsync_n <= !((771 <= vcounter) & (vcounter < 777));
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+ vga_red <= visible ? {pix, pix, pix} : 3'b000;
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+ vga_green <= visible ? {pix, pix, pix} : 3'b000;
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+ vga_blue <= visible ? {pix, pix, pix} : 3'b000;
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end
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-
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- assign vga_red = visible ? {pix, pix, pix} : 3'b000;
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- assign vga_green = visible ? {pix, pix, pix} : 3'b000;
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- assign vga_blue = visible ? {pix, pix, pix} : 3'b000;
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-
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endmodule
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module fontrom(
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+ input clk,
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input [7:0] ch,
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input [3:0] row,
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input [2:0] col,
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output pix);
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+ reg [11:0] a;
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+ reg [2:0] col_;
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+ always @(posedge clk) begin
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+ a <= {ch, row};
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+ col_ <= col;
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+ end
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+
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reg [7:0] pattern;
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- assign pix = pattern[~col];
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+ assign pix = pattern[~col_];
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always @*
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- case ({ch, row})
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+ case (a)
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{ 8'h00, 4'h0 }: pattern = 8'b00000000;
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{ 8'h00, 4'h1 }: pattern = 8'b00000000;
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{ 8'h00, 4'h2 }: pattern = 8'b00000000;
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