tegra124.dtsi 16 KB

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  1. #include <dt-bindings/clock/tegra124-car.h>
  2. #include <dt-bindings/gpio/tegra-gpio.h>
  3. #include <dt-bindings/pinctrl/pinctrl-tegra.h>
  4. #include <dt-bindings/interrupt-controller/arm-gic.h>
  5. #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  6. #include "skeleton.dtsi"
  7. / {
  8. compatible = "nvidia,tegra124";
  9. interrupt-parent = <&gic>;
  10. pcie-controller@01003000 {
  11. compatible = "nvidia,tegra124-pcie";
  12. device_type = "pci";
  13. reg = <0x01003000 0x00000800 /* PADS registers */
  14. 0x01003800 0x00000800 /* AFI registers */
  15. 0x02000000 0x10000000>; /* configuration space */
  16. reg-names = "pads", "afi", "cs";
  17. interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  18. <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  19. interrupt-names = "intr", "msi";
  20. #interrupt-cells = <1>;
  21. interrupt-map-mask = <0 0 0 0>;
  22. interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  23. bus-range = <0x00 0xff>;
  24. #address-cells = <3>;
  25. #size-cells = <2>;
  26. ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */
  27. 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */
  28. 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
  29. 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
  30. 0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  31. clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  32. <&tegra_car TEGRA124_CLK_AFI>,
  33. <&tegra_car TEGRA124_CLK_PLL_E>,
  34. <&tegra_car TEGRA124_CLK_CML0>;
  35. clock-names = "pex", "afi", "pll_e", "cml";
  36. resets = <&tegra_car 70>,
  37. <&tegra_car 72>,
  38. <&tegra_car 74>;
  39. reset-names = "pex", "afi", "pcie_x";
  40. status = "disabled";
  41. phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
  42. phy-names = "pcie";
  43. pci@1,0 {
  44. device_type = "pci";
  45. assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  46. reg = <0x000800 0 0 0 0>;
  47. status = "disabled";
  48. #address-cells = <3>;
  49. #size-cells = <2>;
  50. ranges;
  51. nvidia,num-lanes = <2>;
  52. };
  53. pci@2,0 {
  54. device_type = "pci";
  55. assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  56. reg = <0x001000 0 0 0 0>;
  57. status = "disabled";
  58. #address-cells = <3>;
  59. #size-cells = <2>;
  60. ranges;
  61. nvidia,num-lanes = <1>;
  62. };
  63. };
  64. host1x@50000000 {
  65. compatible = "nvidia,tegra124-host1x", "simple-bus";
  66. reg = <0x50000000 0x00034000>;
  67. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  68. <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  69. clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  70. resets = <&tegra_car 28>;
  71. reset-names = "host1x";
  72. #address-cells = <1>;
  73. #size-cells = <1>;
  74. ranges = <0x54000000 0x54000000 0x01000000>;
  75. dc@54200000 {
  76. compatible = "nvidia,tegra124-dc";
  77. reg = <0x54200000 0x00040000>;
  78. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  79. clocks = <&tegra_car TEGRA124_CLK_DISP1>,
  80. <&tegra_car TEGRA124_CLK_PLL_P>;
  81. clock-names = "dc", "parent";
  82. resets = <&tegra_car 27>;
  83. reset-names = "dc";
  84. nvidia,head = <0>;
  85. };
  86. dc@54240000 {
  87. compatible = "nvidia,tegra124-dc";
  88. reg = <0x54240000 0x00040000>;
  89. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  90. clocks = <&tegra_car TEGRA124_CLK_DISP2>,
  91. <&tegra_car TEGRA124_CLK_PLL_P>;
  92. clock-names = "dc", "parent";
  93. resets = <&tegra_car 26>;
  94. reset-names = "dc";
  95. nvidia,head = <1>;
  96. };
  97. hdmi@54280000 {
  98. compatible = "nvidia,tegra124-hdmi";
  99. reg = <0x54280000 0x00040000>;
  100. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  101. clocks = <&tegra_car TEGRA124_CLK_HDMI>,
  102. <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
  103. clock-names = "hdmi", "parent";
  104. resets = <&tegra_car 51>;
  105. reset-names = "hdmi";
  106. status = "disabled";
  107. };
  108. sor@54540000 {
  109. compatible = "nvidia,tegra124-sor";
  110. reg = <0x54540000 0x00040000>;
  111. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  112. clocks = <&tegra_car TEGRA124_CLK_SOR0>,
  113. <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
  114. <&tegra_car TEGRA124_CLK_PLL_DP>,
  115. <&tegra_car TEGRA124_CLK_CLK_M>;
  116. clock-names = "sor", "parent", "dp", "safe";
  117. resets = <&tegra_car 182>;
  118. reset-names = "sor";
  119. status = "disabled";
  120. };
  121. dpaux: dpaux@545c0000 {
  122. compatible = "nvidia,tegra124-dpaux";
  123. reg = <0x545c0000 0x00040000>;
  124. interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  125. clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
  126. <&tegra_car TEGRA124_CLK_PLL_DP>;
  127. clock-names = "dpaux", "parent";
  128. resets = <&tegra_car 181>;
  129. reset-names = "dpaux";
  130. status = "disabled";
  131. };
  132. };
  133. gic: interrupt-controller@50041000 {
  134. compatible = "arm,cortex-a15-gic";
  135. #interrupt-cells = <3>;
  136. interrupt-controller;
  137. reg = <0x50041000 0x1000>,
  138. <0x50042000 0x2000>,
  139. <0x50044000 0x2000>,
  140. <0x50046000 0x2000>;
  141. interrupts = <GIC_PPI 9
  142. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  143. };
  144. tegra_car: clock@60006000 {
  145. compatible = "nvidia,tegra124-car";
  146. reg = <0x60006000 0x1000>;
  147. #clock-cells = <1>;
  148. };
  149. apbdma: dma@60020000 {
  150. compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
  151. reg = <0x60020000 0x1400>;
  152. interrupts = <0 104 0x04
  153. 0 105 0x04
  154. 0 106 0x04
  155. 0 107 0x04
  156. 0 108 0x04
  157. 0 109 0x04
  158. 0 110 0x04
  159. 0 111 0x04
  160. 0 112 0x04
  161. 0 113 0x04
  162. 0 114 0x04
  163. 0 115 0x04
  164. 0 116 0x04
  165. 0 117 0x04
  166. 0 118 0x04
  167. 0 119 0x04
  168. 0 128 0x04
  169. 0 129 0x04
  170. 0 130 0x04
  171. 0 131 0x04
  172. 0 132 0x04
  173. 0 133 0x04
  174. 0 134 0x04
  175. 0 135 0x04
  176. 0 136 0x04
  177. 0 137 0x04
  178. 0 138 0x04
  179. 0 139 0x04
  180. 0 140 0x04
  181. 0 141 0x04
  182. 0 142 0x04
  183. 0 143 0x04>;
  184. };
  185. gpio: gpio@6000d000 {
  186. compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
  187. reg = <0x6000d000 0x1000>;
  188. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  189. <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  190. <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  191. <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  192. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  193. <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  194. <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
  195. <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
  196. #gpio-cells = <2>;
  197. gpio-controller;
  198. #interrupt-cells = <2>;
  199. interrupt-controller;
  200. };
  201. i2c@7000c000 {
  202. compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
  203. reg = <0x7000c000 0x100>;
  204. interrupts = <0 38 0x04>;
  205. #address-cells = <1>;
  206. #size-cells = <0>;
  207. clocks = <&tegra_car 12>;
  208. status = "disabled";
  209. };
  210. i2c@7000c400 {
  211. compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
  212. reg = <0x7000c400 0x100>;
  213. interrupts = <0 84 0x04>;
  214. #address-cells = <1>;
  215. #size-cells = <0>;
  216. clocks = <&tegra_car 54>;
  217. status = "disabled";
  218. };
  219. i2c@7000c500 {
  220. compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
  221. reg = <0x7000c500 0x100>;
  222. interrupts = <0 92 0x04>;
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. clocks = <&tegra_car 67>;
  226. status = "disabled";
  227. };
  228. i2c@7000c700 {
  229. compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
  230. reg = <0x7000c700 0x100>;
  231. interrupts = <0 120 0x04>;
  232. #address-cells = <1>;
  233. #size-cells = <0>;
  234. clocks = <&tegra_car 103>;
  235. status = "disabled";
  236. };
  237. i2c@7000d000 {
  238. compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
  239. reg = <0x7000d000 0x100>;
  240. interrupts = <0 53 0x04>;
  241. #address-cells = <1>;
  242. #size-cells = <0>;
  243. clocks = <&tegra_car 47>;
  244. status = "disabled";
  245. };
  246. i2c@7000d100 {
  247. compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
  248. reg = <0x7000d100 0x100>;
  249. interrupts = <0 53 0x04>;
  250. #address-cells = <1>;
  251. #size-cells = <0>;
  252. clocks = <&tegra_car 47>;
  253. status = "disabled";
  254. };
  255. uarta: serial@70006000 {
  256. compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  257. reg = <0x70006000 0x40>;
  258. reg-shift = <2>;
  259. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  260. clocks = <&tegra_car TEGRA124_CLK_UARTA>;
  261. resets = <&tegra_car 6>;
  262. reset-names = "serial";
  263. dmas = <&apbdma 8>, <&apbdma 8>;
  264. dma-names = "rx", "tx";
  265. status = "disabled";
  266. };
  267. uartb: serial@70006040 {
  268. compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  269. reg = <0x70006040 0x40>;
  270. reg-shift = <2>;
  271. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  272. clocks = <&tegra_car TEGRA124_CLK_UARTB>;
  273. resets = <&tegra_car 7>;
  274. reset-names = "serial";
  275. dmas = <&apbdma 9>, <&apbdma 9>;
  276. dma-names = "rx", "tx";
  277. status = "disabled";
  278. };
  279. uartc: serial@70006200 {
  280. compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  281. reg = <0x70006200 0x40>;
  282. reg-shift = <2>;
  283. interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  284. clocks = <&tegra_car TEGRA124_CLK_UARTC>;
  285. resets = <&tegra_car 55>;
  286. reset-names = "serial";
  287. dmas = <&apbdma 10>, <&apbdma 10>;
  288. dma-names = "rx", "tx";
  289. status = "disabled";
  290. };
  291. uartd: serial@70006300 {
  292. compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  293. reg = <0x70006300 0x40>;
  294. reg-shift = <2>;
  295. interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  296. clocks = <&tegra_car TEGRA124_CLK_UARTD>;
  297. resets = <&tegra_car 65>;
  298. reset-names = "serial";
  299. dmas = <&apbdma 19>, <&apbdma 19>;
  300. dma-names = "rx", "tx";
  301. status = "disabled";
  302. };
  303. uarte: serial@70006400 {
  304. compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  305. reg = <0x70006400 0x40>;
  306. reg-shift = <2>;
  307. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  308. clocks = <&tegra_car TEGRA124_CLK_UARTE>;
  309. resets = <&tegra_car 66>;
  310. reset-names = "serial";
  311. dmas = <&apbdma 20>, <&apbdma 20>;
  312. dma-names = "rx", "tx";
  313. status = "disabled";
  314. };
  315. pwm: pwm@7000a000 {
  316. compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
  317. reg = <0x7000a000 0x100>;
  318. #pwm-cells = <2>;
  319. clocks = <&tegra_car TEGRA124_CLK_PWM>;
  320. resets = <&tegra_car 17>;
  321. reset-names = "pwm";
  322. status = "disabled";
  323. };
  324. spi@7000d400 {
  325. compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
  326. reg = <0x7000d400 0x200>;
  327. interrupts = <0 59 0x04>;
  328. nvidia,dma-request-selector = <&apbdma 15>;
  329. #address-cells = <1>;
  330. #size-cells = <0>;
  331. status = "disabled";
  332. clocks = <&tegra_car 41>;
  333. };
  334. spi@7000d600 {
  335. compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
  336. reg = <0x7000d600 0x200>;
  337. interrupts = <0 82 0x04>;
  338. nvidia,dma-request-selector = <&apbdma 16>;
  339. #address-cells = <1>;
  340. #size-cells = <0>;
  341. status = "disabled";
  342. clocks = <&tegra_car 44>;
  343. };
  344. spi@7000d800 {
  345. compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
  346. reg = <0x7000d800 0x200>;
  347. interrupts = <0 83 0x04>;
  348. nvidia,dma-request-selector = <&apbdma 17>;
  349. #address-cells = <1>;
  350. #size-cells = <0>;
  351. status = "disabled";
  352. clocks = <&tegra_car 46>;
  353. };
  354. spi@7000da00 {
  355. compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
  356. reg = <0x7000da00 0x200>;
  357. interrupts = <0 93 0x04>;
  358. nvidia,dma-request-selector = <&apbdma 18>;
  359. #address-cells = <1>;
  360. #size-cells = <0>;
  361. status = "disabled";
  362. clocks = <&tegra_car 68>;
  363. };
  364. spi@7000dc00 {
  365. compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
  366. reg = <0x7000dc00 0x200>;
  367. interrupts = <0 94 0x04>;
  368. nvidia,dma-request-selector = <&apbdma 27>;
  369. #address-cells = <1>;
  370. #size-cells = <0>;
  371. status = "disabled";
  372. clocks = <&tegra_car 104>;
  373. };
  374. spi@7000de00 {
  375. compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
  376. reg = <0x7000de00 0x200>;
  377. interrupts = <0 79 0x04>;
  378. nvidia,dma-request-selector = <&apbdma 28>;
  379. #address-cells = <1>;
  380. #size-cells = <0>;
  381. status = "disabled";
  382. clocks = <&tegra_car 105>;
  383. };
  384. pmc@7000e400 {
  385. compatible = "nvidia,tegra124-pmc";
  386. reg = <0x7000e400 0x400>;
  387. };
  388. padctl: padctl@7009f000 {
  389. compatible = "nvidia,tegra124-xusb-padctl";
  390. reg = <0x7009f000 0x1000>;
  391. resets = <&tegra_car 142>;
  392. reset-names = "padctl";
  393. #phy-cells = <1>;
  394. };
  395. sdhci@700b0000 {
  396. compatible = "nvidia,tegra124-sdhci";
  397. reg = <0x700b0000 0x200>;
  398. interrupts = <0 14 0x04>;
  399. clocks = <&tegra_car 14>;
  400. status = "disabled";
  401. };
  402. sdhci@700b0200 {
  403. compatible = "nvidia,tegra124-sdhci";
  404. reg = <0x700b0200 0x200>;
  405. interrupts = <0 15 0x04>;
  406. clocks = <&tegra_car 9>;
  407. status = "disabled";
  408. };
  409. sdhci@700b0400 {
  410. compatible = "nvidia,tegra124-sdhci";
  411. reg = <0x700b0400 0x200>;
  412. interrupts = <0 19 0x04>;
  413. clocks = <&tegra_car 69>;
  414. status = "disabled";
  415. };
  416. sdhci@700b0600 {
  417. compatible = "nvidia,tegra124-sdhci";
  418. reg = <0x700b0600 0x200>;
  419. interrupts = <0 31 0x04>;
  420. clocks = <&tegra_car 15>;
  421. status = "disabled";
  422. };
  423. ahub@70300000 {
  424. compatible = "nvidia,tegra124-ahub";
  425. reg = <0x70300000 0x200>,
  426. <0x70300800 0x800>,
  427. <0x70300200 0x600>;
  428. interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  429. clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
  430. <&tegra_car TEGRA124_CLK_APBIF>;
  431. clock-names = "d_audio", "apbif";
  432. resets = <&tegra_car 106>, /* d_audio */
  433. <&tegra_car 107>, /* apbif */
  434. <&tegra_car 30>, /* i2s0 */
  435. <&tegra_car 11>, /* i2s1 */
  436. <&tegra_car 18>, /* i2s2 */
  437. <&tegra_car 101>, /* i2s3 */
  438. <&tegra_car 102>, /* i2s4 */
  439. <&tegra_car 108>, /* dam0 */
  440. <&tegra_car 109>, /* dam1 */
  441. <&tegra_car 110>, /* dam2 */
  442. <&tegra_car 10>, /* spdif */
  443. <&tegra_car 153>, /* amx */
  444. <&tegra_car 185>, /* amx1 */
  445. <&tegra_car 154>, /* adx */
  446. <&tegra_car 180>, /* adx1 */
  447. <&tegra_car 186>, /* afc0 */
  448. <&tegra_car 187>, /* afc1 */
  449. <&tegra_car 188>, /* afc2 */
  450. <&tegra_car 189>, /* afc3 */
  451. <&tegra_car 190>, /* afc4 */
  452. <&tegra_car 191>; /* afc5 */
  453. reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
  454. "i2s3", "i2s4", "dam0", "dam1", "dam2",
  455. "spdif", "amx", "amx1", "adx", "adx1",
  456. "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
  457. dmas = <&apbdma 1>, <&apbdma 1>,
  458. <&apbdma 2>, <&apbdma 2>,
  459. <&apbdma 3>, <&apbdma 3>,
  460. <&apbdma 4>, <&apbdma 4>,
  461. <&apbdma 6>, <&apbdma 6>,
  462. <&apbdma 7>, <&apbdma 7>,
  463. <&apbdma 12>, <&apbdma 12>,
  464. <&apbdma 13>, <&apbdma 13>,
  465. <&apbdma 14>, <&apbdma 14>,
  466. <&apbdma 29>, <&apbdma 29>;
  467. dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
  468. "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
  469. "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
  470. "rx9", "tx9";
  471. ranges;
  472. #address-cells = <1>;
  473. #size-cells = <1>;
  474. tegra_i2s0: i2s@70301000 {
  475. compatible = "nvidia,tegra124-i2s";
  476. reg = <0x70301000 0x100>;
  477. nvidia,ahub-cif-ids = <4 4>;
  478. clocks = <&tegra_car TEGRA124_CLK_I2S0>;
  479. resets = <&tegra_car 30>;
  480. reset-names = "i2s";
  481. status = "disabled";
  482. };
  483. tegra_i2s1: i2s@70301100 {
  484. compatible = "nvidia,tegra124-i2s";
  485. reg = <0x70301100 0x100>;
  486. nvidia,ahub-cif-ids = <5 5>;
  487. clocks = <&tegra_car TEGRA124_CLK_I2S1>;
  488. resets = <&tegra_car 11>;
  489. reset-names = "i2s";
  490. status = "disabled";
  491. };
  492. tegra_i2s2: i2s@70301200 {
  493. compatible = "nvidia,tegra124-i2s";
  494. reg = <0x70301200 0x100>;
  495. nvidia,ahub-cif-ids = <6 6>;
  496. clocks = <&tegra_car TEGRA124_CLK_I2S2>;
  497. resets = <&tegra_car 18>;
  498. reset-names = "i2s";
  499. status = "disabled";
  500. };
  501. tegra_i2s3: i2s@70301300 {
  502. compatible = "nvidia,tegra124-i2s";
  503. reg = <0x70301300 0x100>;
  504. nvidia,ahub-cif-ids = <7 7>;
  505. clocks = <&tegra_car TEGRA124_CLK_I2S3>;
  506. resets = <&tegra_car 101>;
  507. reset-names = "i2s";
  508. status = "disabled";
  509. };
  510. tegra_i2s4: i2s@70301400 {
  511. compatible = "nvidia,tegra124-i2s";
  512. reg = <0x70301400 0x100>;
  513. nvidia,ahub-cif-ids = <8 8>;
  514. clocks = <&tegra_car TEGRA124_CLK_I2S4>;
  515. resets = <&tegra_car 102>;
  516. reset-names = "i2s";
  517. status = "disabled";
  518. };
  519. };
  520. usb@7d000000 {
  521. compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
  522. reg = <0x7d000000 0x4000>;
  523. interrupts = < 52 >;
  524. phy_type = "utmi";
  525. clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
  526. status = "disabled";
  527. };
  528. usb@7d004000 {
  529. compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
  530. reg = <0x7d004000 0x4000>;
  531. interrupts = < 53 >;
  532. phy_type = "hsic";
  533. clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
  534. status = "disabled";
  535. };
  536. usb@7d008000 {
  537. compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
  538. reg = <0x7d008000 0x4000>;
  539. interrupts = < 129 >;
  540. phy_type = "utmi";
  541. clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
  542. status = "disabled";
  543. };
  544. };