mrvl,cn73xx.dtsi 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Marvell / Cavium Inc. CN73xx
  4. */
  5. /dts-v1/;
  6. / {
  7. #address-cells = <2>;
  8. #size-cells = <2>;
  9. soc0: soc@0 {
  10. interrupt-parent = <&ciu3>;
  11. compatible = "simple-bus";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. ranges; /* Direct mapping */
  15. ciu3: interrupt-controller@1010000000000 {
  16. compatible = "cavium,octeon-7890-ciu3";
  17. interrupt-controller;
  18. /*
  19. * Interrupts are specified by two parts:
  20. * 1) Source number (20 significant bits)
  21. * 2) Trigger type: (4 == level, 1 == edge)
  22. */
  23. #address-cells = <0>;
  24. #interrupt-cells = <2>;
  25. reg = <0x10100 0x00000000 0x0 0xb0000000>;
  26. };
  27. bootbus: bootbus@1180000000000 {
  28. compatible = "cavium,octeon-3860-bootbus","simple-bus";
  29. reg = <0x11800 0x00000000 0x0 0x200>;
  30. /* The chip select number and offset */
  31. #address-cells = <2>;
  32. /* The size of the chip select region */
  33. #size-cells = <1>;
  34. };
  35. reset: reset@1180006001600 {
  36. compatible = "mrvl,cn7xxx-rst";
  37. reg = <0x11800 0x06001600 0x0 0x200>;
  38. };
  39. uart0: serial@1180000000800 {
  40. compatible = "cavium,octeon-3860-uart","ns16550";
  41. reg = <0x11800 0x00000800 0x0 0x400>;
  42. clock-frequency = <0>;
  43. current-speed = <115200>;
  44. reg-shift = <3>;
  45. interrupts = <0x08000 4>;
  46. };
  47. uart1: serial@1180000000c00 {
  48. compatible = "cavium,octeon-3860-uart","ns16550";
  49. reg = <0x11800 0x00000c00 0x0 0x400>;
  50. clock-frequency = <0>;
  51. current-speed = <115200>;
  52. reg-shift = <3>;
  53. interrupts = <0x08040 4>;
  54. };
  55. };
  56. };