cache-ncore.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <dm.h>
  7. #include <wait_bit.h>
  8. #include <asm/io.h>
  9. /* Directory */
  10. #define DIRUSFER 0x80010
  11. #define DIRUCASER0 0x80040
  12. #define DIRUSFMCR 0x80080
  13. #define DIRUSFMAR 0x80084
  14. #define DIRUSFMCR_SFID_SHIFT 16
  15. /* Coherent cache agent interface */
  16. #define CAIUIDR 0x00ffc
  17. #define CAIUIDR_CA_GET(v) (((v) & 0x00008000) >> 15)
  18. #define CAIUIDR_TYPE_GET(v) (((v) & 0x000f0000) >> 16)
  19. #define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT 0
  20. #define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT 1
  21. /* Coherent subsystem */
  22. #define CSADSER0 0xff040
  23. #define CSUIDR 0xffff8
  24. #define CSIDR 0xffffc
  25. #define CSUIDR_NUMCAIUS_GET(v) (((v) & 0x0000007f) >> 0)
  26. #define CSUIDR_NUMDIRUS_GET(v) (((v) & 0x003f0000) >> 16)
  27. #define CSUIDR_NUMCMIUS_GET(v) (((v) & 0x3f000000) >> 24)
  28. #define CSIDR_NUMSFS_GET(v) (((v) & 0x007c0000) >> 18)
  29. #define DIR_REG_SZ 0x1000
  30. #define CAIU_REG_SZ 0x1000
  31. #define CCU_DIR_REG_ADDR(base, reg, dir) \
  32. ((base) + (reg) + ((dir) * DIR_REG_SZ))
  33. /* OCRAM firewall register */
  34. #define OCRAM_FW_01 0x100204
  35. #define OCRAM_SECURE_REGIONS 4
  36. #define OCRAM_PRIVILEGED_MASK BIT(29)
  37. #define OCRAM_SECURE_MASK BIT(30)
  38. static void ncore_ccu_init_dirs(void __iomem *base)
  39. {
  40. ulong i, f;
  41. int ret;
  42. u32 num_of_dirs;
  43. u32 num_of_snoop_filters;
  44. u32 reg;
  45. num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
  46. num_of_snoop_filters =
  47. CSIDR_NUMSFS_GET(readl(base + CSIDR)) + 1;
  48. /* Initialize each snoop filter in each directory */
  49. for (f = 0; f < num_of_snoop_filters; f++) {
  50. reg = f << DIRUSFMCR_SFID_SHIFT;
  51. for (i = 0; i < num_of_dirs; i++) {
  52. /* Initialize all entries */
  53. writel(reg, CCU_DIR_REG_ADDR(base, DIRUSFMCR, i));
  54. /* Poll snoop filter maintenance operation active
  55. * bit become 0.
  56. */
  57. ret = wait_for_bit_le32((const void *)
  58. CCU_DIR_REG_ADDR(base,
  59. DIRUSFMAR, i),
  60. BIT(0), false, 1000, false);
  61. if (ret) {
  62. puts("CCU: Directory initialization failed!\n");
  63. hang();
  64. }
  65. /* Enable snoop filter, a bit per snoop filter */
  66. setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
  67. BIT(f));
  68. }
  69. }
  70. }
  71. static void ncore_ccu_init_coh_agent(void __iomem *base)
  72. {
  73. u32 num_of_coh_agent_intf;
  74. u32 num_of_dirs;
  75. u32 reg;
  76. u32 type;
  77. u32 i, dir;
  78. num_of_coh_agent_intf =
  79. CSUIDR_NUMCAIUS_GET(readl(base + CSUIDR));
  80. num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
  81. for (i = 0; i < num_of_coh_agent_intf; i++) {
  82. reg = readl(base + CAIUIDR + (i * CAIU_REG_SZ));
  83. if (CAIUIDR_CA_GET(reg)) {
  84. /* Caching agent bit is enabled, enable caching agent
  85. * snoop in each directory
  86. */
  87. for (dir = 0; dir < num_of_dirs; dir++) {
  88. setbits_le32((ulong)
  89. CCU_DIR_REG_ADDR(base, DIRUCASER0,
  90. dir),
  91. BIT(i));
  92. }
  93. }
  94. type = CAIUIDR_TYPE_GET(reg);
  95. if (type == CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT ||
  96. type == CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT) {
  97. /* DVM support is enabled, enable ACE DVM snoop*/
  98. setbits_le32((ulong)(base + CSADSER0),
  99. BIT(i));
  100. }
  101. }
  102. }
  103. static void ocram_bypass_firewall(void __iomem *base)
  104. {
  105. int i;
  106. for (i = 0; i < OCRAM_SECURE_REGIONS; i++) {
  107. clrbits_le32(base + OCRAM_FW_01 + (i * sizeof(u32)),
  108. OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
  109. }
  110. }
  111. static int ncore_ccu_probe(struct udevice *dev)
  112. {
  113. void __iomem *base;
  114. fdt_addr_t addr;
  115. addr = dev_read_addr(dev);
  116. if (addr == FDT_ADDR_T_NONE)
  117. return -EINVAL;
  118. base = (void __iomem *)addr;
  119. ncore_ccu_init_dirs(base);
  120. ncore_ccu_init_coh_agent(base);
  121. ocram_bypass_firewall(base);
  122. return 0;
  123. }
  124. static const struct udevice_id ncore_ccu_ids[] = {
  125. { .compatible = "arteris,ncore-ccu" },
  126. {}
  127. };
  128. U_BOOT_DRIVER(ncore_ccu) = {
  129. .name = "ncore_ccu",
  130. .id = UCLASS_CACHE,
  131. .of_match = ncore_ccu_ids,
  132. .probe = ncore_ccu_probe,
  133. .flags = DM_FLAG_PRE_RELOC,
  134. };