pcie_fsl.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2019 NXP
  4. *
  5. * PCIe DM U-Boot driver for Freescale PowerPC SoCs
  6. * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <malloc.h>
  11. #include <mapmem.h>
  12. #include <pci.h>
  13. #include <asm/fsl_pci.h>
  14. #include <asm/fsl_serdes.h>
  15. #include <asm/io.h>
  16. #include "pcie_fsl.h"
  17. LIST_HEAD(fsl_pcie_list);
  18. static int fsl_pcie_link_up(struct fsl_pcie *pcie);
  19. static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
  20. {
  21. struct udevice *bus = pcie->bus;
  22. if (!pcie->enabled)
  23. return -ENXIO;
  24. if (PCI_BUS(bdf) < bus->seq)
  25. return -EINVAL;
  26. if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
  27. return -EINVAL;
  28. if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
  29. return -EINVAL;
  30. if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
  31. return -EINVAL;
  32. return 0;
  33. }
  34. static int fsl_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
  35. uint offset, ulong *valuep,
  36. enum pci_size_t size)
  37. {
  38. struct fsl_pcie *pcie = dev_get_priv(bus);
  39. ccsr_fsl_pci_t *regs = pcie->regs;
  40. u32 val;
  41. if (fsl_pcie_addr_valid(pcie, bdf)) {
  42. *valuep = pci_get_ff(size);
  43. return 0;
  44. }
  45. bdf = bdf - PCI_BDF(bus->seq, 0, 0);
  46. val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  47. out_be32(&regs->cfg_addr, val);
  48. sync();
  49. switch (size) {
  50. case PCI_SIZE_8:
  51. *valuep = in_8((u8 *)&regs->cfg_data + (offset & 3));
  52. break;
  53. case PCI_SIZE_16:
  54. *valuep = in_le16((u16 *)((u8 *)&regs->cfg_data +
  55. (offset & 2)));
  56. break;
  57. case PCI_SIZE_32:
  58. *valuep = in_le32(&regs->cfg_data);
  59. break;
  60. }
  61. return 0;
  62. }
  63. static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
  64. uint offset, ulong value,
  65. enum pci_size_t size)
  66. {
  67. struct fsl_pcie *pcie = dev_get_priv(bus);
  68. ccsr_fsl_pci_t *regs = pcie->regs;
  69. u32 val;
  70. u8 val_8;
  71. u16 val_16;
  72. u32 val_32;
  73. if (fsl_pcie_addr_valid(pcie, bdf))
  74. return 0;
  75. bdf = bdf - PCI_BDF(bus->seq, 0, 0);
  76. val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  77. out_be32(&regs->cfg_addr, val);
  78. sync();
  79. switch (size) {
  80. case PCI_SIZE_8:
  81. val_8 = value;
  82. out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
  83. break;
  84. case PCI_SIZE_16:
  85. val_16 = value;
  86. out_le16((u16 *)((u8 *)&regs->cfg_data + (offset & 2)), val_16);
  87. break;
  88. case PCI_SIZE_32:
  89. val_32 = value;
  90. out_le32(&regs->cfg_data, val_32);
  91. break;
  92. }
  93. return 0;
  94. }
  95. static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
  96. ulong *valuep, enum pci_size_t size)
  97. {
  98. int ret;
  99. struct udevice *bus = pcie->bus;
  100. ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
  101. offset, valuep, size);
  102. return ret;
  103. }
  104. static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
  105. ulong value, enum pci_size_t size)
  106. {
  107. struct udevice *bus = pcie->bus;
  108. return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
  109. offset, value, size);
  110. }
  111. static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
  112. u8 *valuep)
  113. {
  114. ulong val;
  115. int ret;
  116. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
  117. *valuep = val;
  118. return ret;
  119. }
  120. static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
  121. u16 *valuep)
  122. {
  123. ulong val;
  124. int ret;
  125. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
  126. *valuep = val;
  127. return ret;
  128. }
  129. static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
  130. u32 *valuep)
  131. {
  132. ulong val;
  133. int ret;
  134. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
  135. *valuep = val;
  136. return ret;
  137. }
  138. static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
  139. u8 value)
  140. {
  141. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
  142. }
  143. static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
  144. u16 value)
  145. {
  146. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
  147. }
  148. static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
  149. u32 value)
  150. {
  151. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
  152. }
  153. static int fsl_pcie_link_up(struct fsl_pcie *pcie)
  154. {
  155. ccsr_fsl_pci_t *regs = pcie->regs;
  156. u16 ltssm;
  157. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  158. ltssm = (in_be32(&regs->pex_csr0)
  159. & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
  160. return ltssm == LTSSM_L0_REV3;
  161. }
  162. fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
  163. return ltssm == LTSSM_L0;
  164. }
  165. static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
  166. {
  167. u8 header_type;
  168. fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
  169. return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
  170. }
  171. static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
  172. {
  173. struct pci_region *io, *mem, *pref;
  174. pci_get_regions(pcie->bus, &io, &mem, &pref);
  175. if (mem)
  176. set_next_law(mem->phys_start,
  177. law_size_bits(mem->size),
  178. pcie->law_trgt_if);
  179. if (io)
  180. set_next_law(io->phys_start,
  181. law_size_bits(io->size),
  182. pcie->law_trgt_if);
  183. return 0;
  184. }
  185. static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
  186. {
  187. ccsr_fsl_pci_t *regs = pcie->regs;
  188. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  189. setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
  190. return;
  191. }
  192. fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
  193. }
  194. static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
  195. int type, u64 phys, u64 bus_addr,
  196. pci_size_t size)
  197. {
  198. ccsr_fsl_pci_t *regs = pcie->regs;
  199. pot_t *po = &regs->pot[idx];
  200. u32 war, sz;
  201. if (idx < 0)
  202. return -EINVAL;
  203. out_be32(&po->powbar, phys >> 12);
  204. out_be32(&po->potar, bus_addr >> 12);
  205. #ifdef CONFIG_SYS_PCI_64BIT
  206. out_be32(&po->potear, bus_addr >> 44);
  207. #else
  208. out_be32(&po->potear, 0);
  209. #endif
  210. sz = (__ilog2_u64((u64)size) - 1);
  211. war = POWAR_EN | sz;
  212. if (type == PCI_REGION_IO)
  213. war |= POWAR_IO_READ | POWAR_IO_WRITE;
  214. else
  215. war |= POWAR_MEM_READ | POWAR_MEM_WRITE;
  216. out_be32(&po->powar, war);
  217. return 0;
  218. }
  219. static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
  220. bool pf, u64 phys, u64 bus_addr,
  221. pci_size_t size)
  222. {
  223. ccsr_fsl_pci_t *regs = pcie->regs;
  224. pit_t *pi = &regs->pit[idx];
  225. u32 sz = (__ilog2_u64(size) - 1);
  226. u32 flag = PIWAR_LOCAL;
  227. if (idx < 0)
  228. return -EINVAL;
  229. out_be32(&pi->pitar, phys >> 12);
  230. out_be32(&pi->piwbar, bus_addr >> 12);
  231. #ifdef CONFIG_SYS_PCI_64BIT
  232. out_be32(&pi->piwbear, bus_addr >> 44);
  233. #else
  234. out_be32(&pi->piwbear, 0);
  235. #endif
  236. #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
  237. flag = 0;
  238. #endif
  239. flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
  240. if (pf)
  241. flag |= PIWAR_PF;
  242. out_be32(&pi->piwar, flag | sz);
  243. return 0;
  244. }
  245. static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
  246. {
  247. struct pci_region *io, *mem, *pref;
  248. int idx = 1; /* skip 0 */
  249. pci_get_regions(pcie->bus, &io, &mem, &pref);
  250. if (io)
  251. /* ATU : OUTBOUND : IO */
  252. fsl_pcie_setup_outbound_win(pcie, idx++,
  253. PCI_REGION_IO,
  254. io->phys_start,
  255. io->bus_start,
  256. io->size);
  257. if (mem)
  258. /* ATU : OUTBOUND : MEM */
  259. fsl_pcie_setup_outbound_win(pcie, idx++,
  260. PCI_REGION_MEM,
  261. mem->phys_start,
  262. mem->bus_start,
  263. mem->size);
  264. return 0;
  265. }
  266. static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
  267. {
  268. phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
  269. pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
  270. u64 sz = min((u64)gd->ram_size, (1ull << 32));
  271. pci_size_t pci_sz;
  272. int idx;
  273. if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
  274. idx = 2;
  275. else
  276. idx = 3;
  277. pci_sz = 1ull << __ilog2_u64(sz);
  278. dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
  279. (u64)bus_start, (u64)phys_start, (u64)sz);
  280. /* if we aren't an exact power of two match, pci_sz is smaller
  281. * round it up to the next power of two. We report the actual
  282. * size to pci region tracking.
  283. */
  284. if (pci_sz != sz)
  285. sz = 2ull << __ilog2_u64(sz);
  286. fsl_pcie_setup_inbound_win(pcie, idx--, true,
  287. CONFIG_SYS_PCI_MEMORY_PHYS,
  288. CONFIG_SYS_PCI_MEMORY_BUS, sz);
  289. #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
  290. /*
  291. * On 64-bit capable systems, set up a mapping for all of DRAM
  292. * in high pci address space.
  293. */
  294. pci_sz = 1ull << __ilog2_u64(gd->ram_size);
  295. /* round up to the next largest power of two */
  296. if (gd->ram_size > pci_sz)
  297. pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
  298. dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
  299. (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
  300. (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
  301. fsl_pcie_setup_inbound_win(pcie, idx--, true,
  302. CONFIG_SYS_PCI_MEMORY_PHYS,
  303. CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
  304. #endif
  305. return 0;
  306. }
  307. static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
  308. {
  309. fsl_pcie_setup_outbound_wins(pcie);
  310. fsl_pcie_setup_inbound_wins(pcie);
  311. return 0;
  312. }
  313. static int fsl_pcie_init_port(struct fsl_pcie *pcie)
  314. {
  315. ccsr_fsl_pci_t *regs = pcie->regs;
  316. u32 val_32;
  317. u16 val_16;
  318. fsl_pcie_init_atmu(pcie);
  319. #ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
  320. val_32 = 0;
  321. fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
  322. val_32 &= ~0x03;
  323. fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
  324. udelay(1);
  325. #endif
  326. #ifdef CONFIG_FSL_PCIE_RESET
  327. u16 ltssm;
  328. int i;
  329. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  330. /* assert PCIe reset */
  331. setbits_be32(&regs->pdb_stat, 0x08000000);
  332. (void)in_be32(&regs->pdb_stat);
  333. udelay(1000);
  334. /* clear PCIe reset */
  335. clrbits_be32(&regs->pdb_stat, 0x08000000);
  336. asm("sync;isync");
  337. for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
  338. udelay(1000);
  339. } else {
  340. fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
  341. if (ltssm == 1) {
  342. /* assert PCIe reset */
  343. setbits_be32(&regs->pdb_stat, 0x08000000);
  344. (void)in_be32(&regs->pdb_stat);
  345. udelay(100);
  346. /* clear PCIe reset */
  347. clrbits_be32(&regs->pdb_stat, 0x08000000);
  348. asm("sync;isync");
  349. for (i = 0; i < 100 &&
  350. !fsl_pcie_link_up(pcie); i++)
  351. udelay(1000);
  352. }
  353. }
  354. #endif
  355. #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
  356. if (!fsl_pcie_link_up(pcie)) {
  357. serdes_corenet_t *srds_regs;
  358. srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  359. val_32 = in_be32(&srds_regs->srdspccr0);
  360. if ((val_32 >> 28) == 3) {
  361. int i;
  362. out_be32(&srds_regs->srdspccr0, 2 << 28);
  363. setbits_be32(&regs->pdb_stat, 0x08000000);
  364. in_be32(&regs->pdb_stat);
  365. udelay(100);
  366. clrbits_be32(&regs->pdb_stat, 0x08000000);
  367. asm("sync;isync");
  368. for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
  369. udelay(1000);
  370. }
  371. }
  372. #endif
  373. /*
  374. * The Read-Only Write Enable bit defaults to 1 instead of 0.
  375. * Set to 0 to protect the read-only registers.
  376. */
  377. #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
  378. clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
  379. #endif
  380. /*
  381. * Enable All Error Interrupts except
  382. * - Master abort (pci)
  383. * - Master PERR (pci)
  384. * - ICCA (PCIe)
  385. */
  386. out_be32(&regs->peer, ~0x20140);
  387. /* set URR, FER, NFER (but not CER) */
  388. fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
  389. val_32 |= 0xf000e;
  390. fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
  391. /* Clear all error indications */
  392. out_be32(&regs->pme_msg_det, 0xffffffff);
  393. out_be32(&regs->pme_msg_int_en, 0xffffffff);
  394. out_be32(&regs->pedr, 0xffffffff);
  395. fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
  396. if (val_16)
  397. fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
  398. fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
  399. if (val_16)
  400. fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
  401. return 0;
  402. }
  403. static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
  404. {
  405. ccsr_fsl_pci_t *regs = pcie->regs;
  406. u32 classcode_reg;
  407. u32 val;
  408. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  409. classcode_reg = PCI_CLASS_REVISION;
  410. setbits_be32(&regs->dbi_ro_wr_en, 0x01);
  411. } else {
  412. classcode_reg = CSR_CLASSCODE;
  413. }
  414. fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
  415. val &= 0xff;
  416. val |= PCI_CLASS_BRIDGE_PCI << 16;
  417. fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
  418. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
  419. clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
  420. return 0;
  421. }
  422. static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
  423. {
  424. return fsl_pcie_fixup_classcode(pcie);
  425. }
  426. static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
  427. {
  428. fsl_pcie_config_ready(pcie);
  429. return 0;
  430. }
  431. static int fsl_pcie_probe(struct udevice *dev)
  432. {
  433. struct fsl_pcie *pcie = dev_get_priv(dev);
  434. ccsr_fsl_pci_t *regs = pcie->regs;
  435. u16 val_16;
  436. pcie->bus = dev;
  437. pcie->block_rev = in_be32(&regs->block_rev1);
  438. list_add(&pcie->list, &fsl_pcie_list);
  439. pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
  440. if (!pcie->enabled) {
  441. printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
  442. return 0;
  443. }
  444. fsl_pcie_setup_law(pcie);
  445. pcie->mode = fsl_pcie_is_agent(pcie);
  446. fsl_pcie_init_port(pcie);
  447. printf("PCIe%d: %s ", pcie->idx, dev->name);
  448. if (pcie->mode) {
  449. printf("Endpoint");
  450. fsl_pcie_init_ep(pcie);
  451. } else {
  452. printf("Root Complex");
  453. fsl_pcie_init_rc(pcie);
  454. }
  455. if (!fsl_pcie_link_up(pcie)) {
  456. printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
  457. return 0;
  458. }
  459. fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
  460. printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
  461. return 0;
  462. }
  463. static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
  464. {
  465. struct fsl_pcie *pcie = dev_get_priv(dev);
  466. struct fsl_pcie_data *info;
  467. int ret;
  468. pcie->regs = dev_remap_addr(dev);
  469. if (!pcie->regs) {
  470. pr_err("\"reg\" resource not found\n");
  471. return -EINVAL;
  472. }
  473. ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
  474. if (ret < 0) {
  475. pr_err("\"law_trgt_if\" not found\n");
  476. return ret;
  477. }
  478. info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
  479. pcie->info = info;
  480. pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
  481. info->block_offset) / info->stride;
  482. return 0;
  483. }
  484. static const struct dm_pci_ops fsl_pcie_ops = {
  485. .read_config = fsl_pcie_read_config,
  486. .write_config = fsl_pcie_write_config,
  487. };
  488. static struct fsl_pcie_data t2080_data = {
  489. .block_offset = 0x240000,
  490. .block_offset_mask = 0x3fffff,
  491. .stride = 0x10000,
  492. };
  493. static const struct udevice_id fsl_pcie_ids[] = {
  494. { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
  495. { }
  496. };
  497. U_BOOT_DRIVER(fsl_pcie) = {
  498. .name = "fsl_pcie",
  499. .id = UCLASS_PCI,
  500. .of_match = fsl_pcie_ids,
  501. .ops = &fsl_pcie_ops,
  502. .ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
  503. .probe = fsl_pcie_probe,
  504. .priv_auto_alloc_size = sizeof(struct fsl_pcie),
  505. };