sdram.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <ram.h>
  10. #include <asm/io.h>
  11. #include <asm/arch-rockchip/sdram.h>
  12. #include <dm/uclass-internal.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
  15. struct tos_parameter_t {
  16. u32 version;
  17. u32 checksum;
  18. struct {
  19. char name[8];
  20. s64 phy_addr;
  21. u32 size;
  22. u32 flags;
  23. } tee_mem;
  24. struct {
  25. char name[8];
  26. s64 phy_addr;
  27. u32 size;
  28. u32 flags;
  29. } drm_mem;
  30. s64 reserve[8];
  31. };
  32. int dram_init_banksize(void)
  33. {
  34. size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
  35. gd->ram_top);
  36. #ifdef CONFIG_ARM64
  37. /* Reserve 0x200000 for ATF bl31 */
  38. gd->bd->bi_dram[0].start = 0x200000;
  39. gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
  40. #else
  41. #ifdef CONFIG_SPL_OPTEE
  42. struct tos_parameter_t *tos_parameter;
  43. tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
  44. TRUST_PARAMETER_OFFSET);
  45. if (tos_parameter->tee_mem.flags == 1) {
  46. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  47. gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
  48. - CONFIG_SYS_SDRAM_BASE;
  49. gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
  50. tos_parameter->tee_mem.size;
  51. gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
  52. + top - gd->bd->bi_dram[1].start;
  53. } else {
  54. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  55. gd->bd->bi_dram[0].size = 0x8400000;
  56. /* Reserve 32M for OPTEE with TA */
  57. gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
  58. + gd->bd->bi_dram[0].size + 0x2000000;
  59. gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
  60. + top - gd->bd->bi_dram[1].start;
  61. }
  62. #else
  63. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  64. gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
  65. #endif
  66. #endif
  67. return 0;
  68. }
  69. size_t rockchip_sdram_size(phys_addr_t reg)
  70. {
  71. u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
  72. size_t chipsize_mb = 0;
  73. size_t size_mb = 0;
  74. u32 ch;
  75. u32 cs1_col = 0;
  76. u32 bg = 0;
  77. u32 dbw, dram_type;
  78. u32 sys_reg2 = readl(reg);
  79. u32 sys_reg3 = readl(reg + 4);
  80. u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
  81. & SYS_REG_NUM_CH_MASK);
  82. dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
  83. debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
  84. for (ch = 0; ch < ch_num; ch++) {
  85. rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
  86. SYS_REG_RANK_MASK);
  87. cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
  88. SYS_REG_COL_MASK);
  89. cs1_col = cs0_col;
  90. bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
  91. if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
  92. SYS_REG_VERSION_MASK) == 0x2) {
  93. cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
  94. SYS_REG_CS1_COL_MASK);
  95. if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
  96. SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
  97. SYS_REG_CS0_ROW_SHIFT(ch) &
  98. SYS_REG_CS0_ROW_MASK) == 7)
  99. cs0_row = 12;
  100. else
  101. cs0_row = 13 + (sys_reg2 >>
  102. SYS_REG_CS0_ROW_SHIFT(ch) &
  103. SYS_REG_CS0_ROW_MASK) +
  104. ((sys_reg3 >>
  105. SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
  106. SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
  107. if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
  108. SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
  109. SYS_REG_CS1_ROW_SHIFT(ch) &
  110. SYS_REG_CS1_ROW_MASK) == 7)
  111. cs1_row = 12;
  112. else
  113. cs1_row = 13 + (sys_reg2 >>
  114. SYS_REG_CS1_ROW_SHIFT(ch) &
  115. SYS_REG_CS1_ROW_MASK) +
  116. ((sys_reg3 >>
  117. SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
  118. SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
  119. } else {
  120. cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
  121. SYS_REG_CS0_ROW_MASK);
  122. cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
  123. SYS_REG_CS1_ROW_MASK);
  124. }
  125. bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
  126. SYS_REG_BW_MASK));
  127. row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
  128. SYS_REG_ROW_3_4_MASK;
  129. if (dram_type == DDR4) {
  130. dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
  131. SYS_REG_DBW_MASK;
  132. bg = (dbw == 2) ? 2 : 1;
  133. }
  134. chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
  135. if (rank > 1)
  136. chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
  137. (cs0_col - cs1_col));
  138. if (row_3_4)
  139. chipsize_mb = chipsize_mb * 3 / 4;
  140. size_mb += chipsize_mb;
  141. if (rank > 1)
  142. debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
  143. cs1_row %d bw %d row_3_4 %d\n",
  144. rank, cs0_col, cs1_col, bk, cs0_row,
  145. cs1_row, bw, row_3_4);
  146. else
  147. debug("rank %d cs0_col %d bk %d cs0_row %d\
  148. bw %d row_3_4 %d\n",
  149. rank, cs0_col, bk, cs0_row,
  150. bw, row_3_4);
  151. }
  152. /*
  153. * This is workaround for issue we can't get correct size for 4GB ram
  154. * in 32bit system and available before we really need ram space
  155. * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
  156. * The size of 4GB is '0x1 00000000', and this value will be truncated
  157. * to 0 in 32bit system, and system can not get correct ram size.
  158. * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
  159. * and we are now setting SDRAM_MAX_SIZE as max available space for
  160. * ram in 4GB, so we can use this directly to workaround the issue.
  161. * TODO:
  162. * 1. update correct value for SDRAM_MAX_SIZE as what dram
  163. * controller sees.
  164. * 2. update board_get_usable_ram_top() and dram_init_banksize()
  165. * to reserve memory for peripheral space after previous update.
  166. */
  167. if (size_mb > (SDRAM_MAX_SIZE >> 20))
  168. size_mb = (SDRAM_MAX_SIZE >> 20);
  169. return (size_t)size_mb << 20;
  170. }
  171. int dram_init(void)
  172. {
  173. struct ram_info ram;
  174. struct udevice *dev;
  175. int ret;
  176. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  177. if (ret) {
  178. debug("DRAM init failed: %d\n", ret);
  179. return ret;
  180. }
  181. ret = ram_get_info(dev, &ram);
  182. if (ret) {
  183. debug("Cannot get DRAM size: %d\n", ret);
  184. return ret;
  185. }
  186. gd->ram_size = ram.size;
  187. debug("SDRAM base=%lx, size=%lx\n",
  188. (unsigned long)ram.base, (unsigned long)ram.size);
  189. return 0;
  190. }
  191. ulong board_get_usable_ram_top(ulong total_size)
  192. {
  193. unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
  194. return (gd->ram_top > top) ? top : gd->ram_top;
  195. }