rk3399.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <spl.h>
  10. #include <spl_gpio.h>
  11. #include <syscon.h>
  12. #include <asm/armv8/mmu.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-rockchip/bootrom.h>
  15. #include <asm/arch-rockchip/clock.h>
  16. #include <asm/arch-rockchip/gpio.h>
  17. #include <asm/arch-rockchip/grf_rk3399.h>
  18. #include <asm/arch-rockchip/hardware.h>
  19. #include <power/regulator.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. #define GRF_EMMCCORE_CON11 0xff77f02c
  22. #define GRF_BASE 0xff770000
  23. const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  24. [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
  25. [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
  26. [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
  27. };
  28. static struct mm_region rk3399_mem_map[] = {
  29. {
  30. .virt = 0x0UL,
  31. .phys = 0x0UL,
  32. .size = 0xf8000000UL,
  33. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  34. PTE_BLOCK_INNER_SHARE
  35. }, {
  36. .virt = 0xf8000000UL,
  37. .phys = 0xf8000000UL,
  38. .size = 0x08000000UL,
  39. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  40. PTE_BLOCK_NON_SHARE |
  41. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  42. }, {
  43. /* List terminator */
  44. 0,
  45. }
  46. };
  47. struct mm_region *mem_map = rk3399_mem_map;
  48. #ifdef CONFIG_SPL_BUILD
  49. #define TIMER_END_COUNT_L 0x00
  50. #define TIMER_END_COUNT_H 0x04
  51. #define TIMER_INIT_COUNT_L 0x10
  52. #define TIMER_INIT_COUNT_H 0x14
  53. #define TIMER_CONTROL_REG 0x1c
  54. #define TIMER_EN 0x1
  55. #define TIMER_FMODE BIT(0)
  56. #define TIMER_RMODE BIT(1)
  57. void rockchip_stimer_init(void)
  58. {
  59. /* If Timer already enabled, don't re-init it */
  60. u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
  61. if (reg & TIMER_EN)
  62. return;
  63. writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
  64. writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
  65. writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
  66. writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
  67. writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
  68. TIMER_CONTROL_REG);
  69. }
  70. #endif
  71. int arch_cpu_init(void)
  72. {
  73. #ifdef CONFIG_SPL_BUILD
  74. struct rk3399_pmusgrf_regs *sgrf;
  75. struct rk3399_grf_regs *grf;
  76. /*
  77. * Disable DDR and SRAM security regions.
  78. *
  79. * As we are entered from the BootROM, the region from
  80. * 0x0 through 0xfffff (i.e. the first MB of memory) will
  81. * be protected. This will cause issues with the DW_MMC
  82. * driver, which tries to DMA from/to the stack (likely)
  83. * located in this range.
  84. */
  85. sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
  86. rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
  87. rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
  88. /* eMMC clock generator: disable the clock multipilier */
  89. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  90. rk_clrreg(&grf->emmccore_con[11], 0x0ff);
  91. #endif
  92. return 0;
  93. }
  94. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  95. void board_debug_uart_init(void)
  96. {
  97. #define GRF_BASE 0xff770000
  98. #define GPIO0_BASE 0xff720000
  99. #define PMUGRF_BASE 0xff320000
  100. struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  101. #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
  102. struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
  103. struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
  104. #endif
  105. #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  106. /* Enable early UART0 on the RK3399 */
  107. rk_clrsetreg(&grf->gpio2c_iomux,
  108. GRF_GPIO2C0_SEL_MASK,
  109. GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
  110. rk_clrsetreg(&grf->gpio2c_iomux,
  111. GRF_GPIO2C1_SEL_MASK,
  112. GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
  113. #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
  114. /* Enable early UART3 on the RK3399 */
  115. rk_clrsetreg(&grf->gpio3b_iomux,
  116. GRF_GPIO3B6_SEL_MASK,
  117. GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
  118. rk_clrsetreg(&grf->gpio3b_iomux,
  119. GRF_GPIO3B7_SEL_MASK,
  120. GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
  121. #else
  122. # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
  123. rk_setreg(&grf->io_vsel, 1 << 0);
  124. /*
  125. * Let's enable these power rails here, we are already running the SPI
  126. * Flash based code.
  127. */
  128. spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
  129. spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
  130. spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
  131. spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
  132. #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
  133. /* Enable early UART2 channel C on the RK3399 */
  134. rk_clrsetreg(&grf->gpio4c_iomux,
  135. GRF_GPIO4C3_SEL_MASK,
  136. GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
  137. rk_clrsetreg(&grf->gpio4c_iomux,
  138. GRF_GPIO4C4_SEL_MASK,
  139. GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
  140. /* Set channel C as UART2 input */
  141. rk_clrsetreg(&grf->soc_con7,
  142. GRF_UART_DBG_SEL_MASK,
  143. GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
  144. #endif
  145. }
  146. #endif
  147. #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
  148. const char *spl_decode_boot_device(u32 boot_device)
  149. {
  150. int i;
  151. static const struct {
  152. u32 boot_device;
  153. const char *ofpath;
  154. } spl_boot_devices_tbl[] = {
  155. { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
  156. { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
  157. { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
  158. };
  159. for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
  160. if (spl_boot_devices_tbl[i].boot_device == boot_device)
  161. return spl_boot_devices_tbl[i].ofpath;
  162. return NULL;
  163. }
  164. void spl_perform_fixups(struct spl_image_info *spl_image)
  165. {
  166. void *blob = spl_image->fdt_addr;
  167. const char *boot_ofpath;
  168. int chosen;
  169. /*
  170. * Inject the ofpath of the device the full U-Boot (or Linux in
  171. * Falcon-mode) was booted from into the FDT, if a FDT has been
  172. * loaded at the same time.
  173. */
  174. if (!blob)
  175. return;
  176. boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
  177. if (!boot_ofpath) {
  178. pr_err("%s: could not map boot_device to ofpath\n", __func__);
  179. return;
  180. }
  181. chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
  182. if (chosen < 0) {
  183. pr_err("%s: could not find/create '/chosen'\n", __func__);
  184. return;
  185. }
  186. fdt_setprop_string(blob, chosen,
  187. "u-boot,spl-boot-device", boot_ofpath);
  188. }
  189. #if defined(SPL_GPIO_SUPPORT)
  190. static void rk3399_force_power_on_reset(void)
  191. {
  192. ofnode node;
  193. struct gpio_desc sysreset_gpio;
  194. debug("%s: trying to force a power-on reset\n", __func__);
  195. node = ofnode_path("/config");
  196. if (!ofnode_valid(node)) {
  197. debug("%s: no /config node?\n", __func__);
  198. return;
  199. }
  200. if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
  201. &sysreset_gpio, GPIOD_IS_OUT)) {
  202. debug("%s: could not find a /config/sysreset-gpio\n", __func__);
  203. return;
  204. }
  205. dm_gpio_set_value(&sysreset_gpio, 1);
  206. }
  207. #endif
  208. void spl_board_init(void)
  209. {
  210. #if defined(SPL_GPIO_SUPPORT)
  211. struct rockchip_cru *cru = rockchip_get_cru();
  212. /*
  213. * The RK3399 resets only 'almost all logic' (see also in the TRM
  214. * "3.9.4 Global software reset"), when issuing a software reset.
  215. * This may cause issues during boot-up for some configurations of
  216. * the application software stack.
  217. *
  218. * To work around this, we test whether the last reset reason was
  219. * a power-on reset and (if not) issue an overtemp-reset to reset
  220. * the entire module.
  221. *
  222. * While this was previously fixed by modifying the various places
  223. * that could generate a software reset (e.g. U-Boot's sysreset
  224. * driver, the ATF or Linux), we now have it here to ensure that
  225. * we no longer have to track this through the various components.
  226. */
  227. if (cru->glb_rst_st != 0)
  228. rk3399_force_power_on_reset();
  229. #endif
  230. #if defined(SPL_DM_REGULATOR)
  231. /*
  232. * Turning the eMMC and SPI back on (if disabled via the Qseven
  233. * BIOS_ENABLE) signal is done through a always-on regulator).
  234. */
  235. if (regulators_enable_boot_on(false))
  236. debug("%s: Cannot enable boot on regulator\n", __func__);
  237. #endif
  238. }
  239. #endif