rk3368.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  4. * Copyright (c) 2016 Andreas Färber
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <syscon.h>
  9. #include <asm/armv8/mmu.h>
  10. #include <asm/io.h>
  11. #include <asm/arch-rockchip/bootrom.h>
  12. #include <asm/arch-rockchip/clock.h>
  13. #include <asm/arch-rockchip/cru_rk3368.h>
  14. #include <asm/arch-rockchip/grf_rk3368.h>
  15. #include <asm/arch-rockchip/hardware.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #define IMEM_BASE 0xFF8C0000
  18. /* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
  19. #define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4)
  20. #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
  21. #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
  22. /* exsram may using by mcu to accessing dram(0x0-0x20000000) */
  23. #define MCU_EXSRAM_BASE (0)
  24. #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
  25. #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
  26. /* experi no used, reserved value = 0 */
  27. #define MCU_EXPERI_BASE (0)
  28. #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
  29. #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
  30. static struct mm_region rk3368_mem_map[] = {
  31. {
  32. .virt = 0x0UL,
  33. .phys = 0x0UL,
  34. .size = 0x80000000UL,
  35. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  36. PTE_BLOCK_INNER_SHARE
  37. }, {
  38. .virt = 0xf0000000UL,
  39. .phys = 0xf0000000UL,
  40. .size = 0x10000000UL,
  41. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  42. PTE_BLOCK_NON_SHARE |
  43. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  44. }, {
  45. /* List terminator */
  46. 0,
  47. }
  48. };
  49. struct mm_region *mem_map = rk3368_mem_map;
  50. const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  51. [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
  52. [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
  53. };
  54. #ifdef CONFIG_ARCH_EARLY_INIT_R
  55. static int mcu_init(void)
  56. {
  57. struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  58. struct rk3368_cru *cru = rockchip_get_cru();
  59. rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
  60. MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
  61. rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
  62. MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
  63. rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
  64. MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
  65. rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
  66. MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
  67. rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
  68. MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
  69. rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
  70. MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
  71. rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
  72. (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
  73. (5 << MCU_CLK_DIV_SHIFT));
  74. /* mcu dereset, for start running */
  75. rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
  76. return 0;
  77. }
  78. int arch_early_init_r(void)
  79. {
  80. return mcu_init();
  81. }
  82. #endif
  83. #ifdef CONFIG_SPL_BUILD
  84. /*
  85. * The SPL (and also the full U-Boot stage on the RK3368) will run in
  86. * secure mode (i.e. EL3) and an ATF will eventually be booted before
  87. * starting up the operating system... so we can initialize the SGRF
  88. * here and rely on the ATF installing the final (secure) policy
  89. * later.
  90. */
  91. static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
  92. {
  93. const uintptr_t SGRF_BASE =
  94. (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
  95. return SGRF_BASE + sizeof(u32) * no;
  96. }
  97. static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
  98. {
  99. const uintptr_t SGRF_BASE =
  100. (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
  101. const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
  102. const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
  103. return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
  104. }
  105. static void sgrf_init(void)
  106. {
  107. struct rk3368_cru * const cru =
  108. (struct rk3368_cru * const)rockchip_get_cru();
  109. const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
  110. const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
  111. const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
  112. /* Set all configurable IP to 'non secure'-mode */
  113. rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
  114. rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
  115. rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
  116. /*
  117. * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
  118. * Original comment: "ddr space set no secure mode"
  119. */
  120. rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
  121. rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
  122. rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
  123. /* Set 'secure dma' to 'non secure'-mode */
  124. rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
  125. rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
  126. dsb(); /* barrier */
  127. rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
  128. rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
  129. dsb(); /* barrier */
  130. udelay(10);
  131. rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
  132. rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
  133. }
  134. int arch_cpu_init(void)
  135. {
  136. /* Reset security, so we can use DMA in the MMC drivers */
  137. sgrf_init();
  138. return 0;
  139. }
  140. #endif
  141. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  142. void board_debug_uart_init(void)
  143. {
  144. /*
  145. * N.B.: This is called before the device-model has been
  146. * initialised. For this reason, we can not access
  147. * the GRF address range using the syscon API.
  148. */
  149. #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  150. struct rk3368_grf * const grf =
  151. (struct rk3368_grf * const)0xff770000;
  152. enum {
  153. GPIO2D1_MASK = GENMASK(3, 2),
  154. GPIO2D1_GPIO = 0,
  155. GPIO2D1_UART0_SOUT = (1 << 2),
  156. GPIO2D0_MASK = GENMASK(1, 0),
  157. GPIO2D0_GPIO = 0,
  158. GPIO2D0_UART0_SIN = (1 << 0),
  159. };
  160. /* Enable early UART0 on the RK3368 */
  161. rk_clrsetreg(&grf->gpio2d_iomux,
  162. GPIO2D0_MASK, GPIO2D0_UART0_SIN);
  163. rk_clrsetreg(&grf->gpio2d_iomux,
  164. GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
  165. #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
  166. struct rk3368_pmu_grf * const pmugrf __maybe_unused =
  167. (struct rk3368_pmu_grf * const)0xff738000;
  168. enum {
  169. /* UART4 */
  170. GPIO0D2_MASK = GENMASK(5, 4),
  171. GPIO0D2_GPIO = 0,
  172. GPIO0D2_UART4_SOUT = (3 << 4),
  173. GPIO0D3_MASK = GENMASK(7, 6),
  174. GPIO0D3_GPIO = 0,
  175. GPIO0D3_UART4_SIN = (3 << 6),
  176. };
  177. /* Enable early UART4 on the PX5 */
  178. rk_clrsetreg(&pmugrf->gpio0d_iomux,
  179. GPIO0D2_MASK | GPIO0D3_MASK,
  180. GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
  181. #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
  182. struct rk3368_grf * const grf =
  183. (struct rk3368_grf * const)0xff770000;
  184. enum {
  185. GPIO2A6_SHIFT = 12,
  186. GPIO2A6_MASK = GENMASK(13, 12),
  187. GPIO2A6_GPIO = 0,
  188. GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
  189. GPIO2A5_SHIFT = 10,
  190. GPIO2A5_MASK = GENMASK(11, 10),
  191. GPIO2A5_GPIO = 0,
  192. GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
  193. };
  194. /* Enable early UART2 on the RK3368 */
  195. rk_clrsetreg(&grf->gpio2a_iomux,
  196. GPIO2A6_MASK, GPIO2A6_UART2_SIN);
  197. rk_clrsetreg(&grf->gpio2a_iomux,
  198. GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
  199. #endif
  200. }
  201. #endif